7650SCB

ICL7650S INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• Guaranteed Max Input Offset Voltage forAll Temperature Ranges
• Low Long-Term and Temperature Drifts of Input Offset Voltage
• Extremely Wide Common Mode
• Guaranteed Minimum Output Source/Sink Current
• Unity-Gain Compensated
• Clamp Circuit to Avoid Overload Recovery Problems and Allow Comparator Use
• Extremely Low Chopping Spikes at Input and Output
• Improved, Direct Replacement for Industry-Standard ICL7650 and other Second-Source Parts Pinouts

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. ICL7650SCPA-1 0 to 70 8 Ld PDIP E8.3 ICL7650SCPD 0 to 70 14 Ld PDIP E14.3 ICL7650SCBA-1 0 to 70 8 Ld SOIC M8.15 ICL7650SCTV-1 0 to 70 8 Pin Metal Can T8.C ICL7650S (PDIP, SOIC) TOP VIEW ICL7650S (METAL CAN) TOP VIEW ICL7650S (PDIP) TOP VIEW C EXTA -IN +IN C EXTB OUTPUT C RETN C EXTB OUTPUT-IN C EXTA +IN V+/CASE C RETN C EXTB C EXTA NC (GUARD) -IN +IN NC (GUARD) INT/EXT EXT CLK IN INT CLK OUT OUTPUT OUT CLAMP C RETN Data Sheet April 2000 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Intersil and Design is a trademark of Intersil Corporation.| Copyright © Intersil Corporation 2000

OSC . MAIN NULL +IN -IN A CAP RETURN C EXTA C EXTB A B C CLAMP OUTPUT N P INTERNAL BIAS A A B C INT/EXT EXT CLK IN CLK OUT EXT CLK IN A = CLK OUT A B C ICL7650S

Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Limiting input current to 100µA is recommended to avoid latchup problems. Typically 1mA is safe, however this is not guaranteed. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsVSUPPL Y =±5V. See Test Circuit, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS Input Offset Voltage(Note 3) VOS 25 - ±0.7 ±5 µV 0 to 70 - ±1 ±8 µV Average Temperature Coefficient of Input Offset Voltage(Note 3) ∆VOS /∆T 0 to 70 - 0.02 - µV/oC Change in Input Offset with Time ∆VOS /∆T 25 - 100 - nV/ √month Input Bias Current|I(+)|, |I(-)| IBIAS 25 - 4 10 pA 0 to 70 - 52 0 pA Input Offset Current|I(-), |I(+)| IOS 25 - 82 0 pA 0 to 70 - 10 40 pA Input Resistance R IN 25 - 10 12 - Ω Large Signal Voltage Gain(Note 3) AVOL R L = 10kΩ , VO =±4V 25 135 150 -d B 0 to 70 130 -- d B Output Voltage Swing (Note 4) V OUT R L = 10kΩ 25 ±4.7 ±4.85 - V R L = 100kΩ 25 - ±4.95 - V Common Mode Voltage Range (Note 3) CMVR 25 -5 -5.2 to +4 3.5 V 0 to 70 -5 - 3.5 V Common Mode Rejection Ratio (Note 3) CMRR CMVR = -5V to +3.5V 25 120 140 -d B 0 to 70 120 -- d B Power Supply Rejection Ratio PSRR VS =±3V to±8V 25 120 140 -d B Input Noise Voltage e N R S = 100Ω , f = DC to 10Hz 25 - 2 - µVP-P Input Noise Current i N f = 10Hz 25 - 0.01 - pA/ √Hz Gain Bandwidth Product GBWP 25 - 2 - MHz Slew Rate SR C L = 50pF, RL = 10kΩ 25 - 2.5 - V/ µs Rise Time t R 25 - 0.2 - µs Overshoot OS 25 - 20 - % Operating Supply Range V+ to V- 25 4.5 - 16 V Supply Current I SUPP No Load 25 - 2 3 mA 0 to 70 - - 3.2 mA Output Source Current I O SOURCE 25 2.9 4.5 - mA 0 to 70 2.3 - - mA ICL7650S

Application Information

The functional diagram shows the major elements of the ICL7650S. There are two amplifiers, the main amplifier, and the nulling amplifier. Both have offset-null capability. The main amplifier is connected continuously from the input to the output, while the nulling amplifier, under the control of the chopping oscillator and clock circuit, alternately nulls itself and the main amplifier. The nulling connections, which are MOSFET gates, are inherently high impedance, and two external capacitors provide the required storage of the nulling potentials and the necessary nulling-loop time constants. The nulling arrangement operates over the full common-mode and power-supply ranges, and is also independent of the output level, thus giving exceptionally high CMRR, PSRR, and A VOL . Careful balancing of the input switches, and the inherent balance of the input circuit, minimizes chopper frequency charge injection at the input terminals, and also the feed forward-type injection into the compensation capacitor, which is the main cause of output spikes in this type of circuit. INTERMODULATION Previous chopper-stabilized amplifiers have suffered from intermodulation effects between the chopper frequency and input signals. These arise because the finite AC gain of the amplifier necessitates a small AC signal at the input. This is seen by the zeroing circuit as an error signal, which is chopped and fed back, thus injecting sum and difference frequencies and causing disturbances to the gain and phase vs frequency characteristics near the chopping frequency. These effects are substantially reduced in the ICL7650S by feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current, in such a way as to cancel that portion of the input signal due to finite AC gain. Since that is the major error contribution to the ICL7650S, the intermodulation and gain/phase disturbances are held to very low values, and can generally be ignored. CAPACITOR CONNECTION The null/storage capacitors should be connected to the C EXTA and CEXTB pins, with a common connection to the C RETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting load current IR drops into the capacitive circuitry. The outside foil, where available, should be connected to C RETN . OUTPUT CLAMP The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing junction, a current path between this point and the OUTPUT pin occurs just before the device output saturates. Thus uncontrolled input differentials are avoided, together with the consequent charge buildup on the correction-storage capacitors. The output swing is slightly reduced. CLOCK The ICL7650S has an internal oscillator, giving a chopping frequency of 200Hz, available at the CLOCK OUT pin on the 14 pin devices. Provision has also been made for the use of an external clock in these parts. The INT/ EXT pin has an internal pull-up and may be left open for normal operation, but to utilize an external clock this pin must be tied to V- to disable the internal clock. The external clock signal may then be applied to the EXT CLOCK IN pin. An internal divide-by-two provides the Output Sink Current I O SINK 25 25 30 - mA 0 to 70 20 - - mA Internal Chopping Frequency f CH Pins 13 and 14 Open 25 120 250 375 Hz Clamp ON Current (Note 5) R L = 100kΩ 25 25 70 - µA Clamp OFF Current (Note 5) -4V ≤ VOUT ≤ +4V 25 - 0.001 5 nA 0 to 70 - - 10 nA NOTES: 3. These parameters are guaranteed by design and characterization, but not tested at temperature extremes because thermocouple effects prevent precise measurement of these voltages in automatic test equipment. 4. OUTPUT CLAMP not connected. See typical characteristic curves for output swing vs clamp current characteristics. 5. See OUTPUT CLAMP under detailed description. 6. All significant improvements over the industry-standard ICL7650 are highlighted inbold italics. Electrical SpecificationsVSUPPL Y =±5V. See Test Circuit, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS ICL7650S OUTPUT R 2 1M Ω C C R 0.1µF 0.1 µF C R 1 1M Ω ICL7650S

desired 50% input switching duty cycle. Since the capacitors are charged only when EXT CLOCK IN is high, a 50% - 80% positive duty cycle is recommended, especially for higher frequencies. The external clock can swing between V+ and V-. The logic threshold will be at about 2.5V below V+. Note also that a signal of about 400 Hz, with a 70% duty cycle, will be present at the EXT CLOCK IN pin with INT/ EXT high or open. This is the internal clock signal before being fed to the divider. In those applications where a strobe signal is available, an alternate approach to avoid capacitor misbalancing during overload can be used. If a strobe signal is connected to EXT CLK IN so that it is low during the time that the overload signal is applied to the amplifier, neither capacitor will be charged. Since the leakage at the capacitor pins is quite low at room temperature, the typical amplifier will drift less than 10µV/s, and relatively long measurements can be made with little change in offset. COMPONENT SELECTION The two required capacitors, C EXTA and CEXTB , have optimum values depending on the clock or chopping frequency. For the preset internal clock, the correct value is 0.1µF , and to maintain the same relationship between the chopping frequency and the nulling time constant this value should be scaled approximately in proportion if an external clock is used. A high quality film type capacitor such as mylar is preferred, although a ceramic or other lower-grade capacitor may prove suitable in many applications. For quickest settling on initial turn-on, low dielectric absorption capacitors (such as polypropylene) should be used. With ceramic capacitors, several seconds may be required to settle to 1µV. STATIC PROTECTION All device pins are static-protected by the use of input diodes. However, strong static fields and discharges should be avoided, as they can cause degraded diode junction characteristics, which may result in increased input-leakage currents. LATCHUP AVOIDANCE Junction-isolated CMOS circuits inherently include a parasitic 4-layer (PNPN) structure which has characteristics similar to an SCR. Under certain circumstances this junction may be triggered into a low-impedance state, resulting in excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails should be applied to any pin. In general, the amplifier supplies must be established either at the same time or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to under 1mA to avoid latchup, even under fault conditions. OUTPUT STAGE/LOAD DRIVING The output circuit is a high-impedance type (approximately 18kΩ ), and therefore with loads less than this value, the chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to load resistance. For example, the open-loop gain will be 17dB lower with a 1kΩ load than with a 10kΩ load. If the amplifier is used strictly for DC, this lower gain is of little consequence, since the DC gain is typically greater than 120dB even with a 1kΩ load. However, for wideband applications, the best frequency response will be achieved with a load resistor of 10kΩ or higher. This will result in a smooth 6dB/octave response from 0.1Hz to 2MHz, with phase shifts of less than 10 degrees in the transition region where the main amplifier takes over from the null amplifier. THERMO-ELECTRIC EFFECTS The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in thermocouple junctions of dissimilar metals, alloys, silicon, etc. Unless all junctions are at the same temperature, thermoelectric voltages typically around 0.1µV/ oC, but up to tens of mV/oC for some materials, will be generated. In order to realize the extremely low offset voltages that the chopper amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components should be enclosed to eliminate air movement, especially that caused by power-dissipating elements in the system. Low thermoelectric-efficient connections should be used where possible and power supply voltages and power dissipation should be kept to a minimum. High-impedance loads are preferable, and good separation from surrounding heat-dissipating elements is advisable. GUARDING Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents of the ICL7650S. Boards must be thoroughly cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination. Even with properly cleaned and coated boards, leakage currents may cause trouble, particularly since the input pins are adjacent to pins that are at supply potentials. This leakage can be significantly reduced by using guarding to lower the voltage difference between the inputs and adjacent metal runs. Input guarding of the 8-pin TO-99 package is accomplished by using a 10-lead pin circle, with the leads of the device formed so that the holes adjacent to the inputs are empty when it is inserted in the board. The guard, which is a conductive ring surrounding the inputs, is connected to a low impedance point that is at approximately the same voltage as the inputs. Leakage currents from high-voltage pins are then absorbed by the guard. ICL7650S

FIGURE 17. OPEN LOOP GAIN AND PHASE SHIFT vs FIGURE 18. VOLTAGE FOLLOWER LARGE SIGNAL PULSE FIGURE 19. VOLTAGE FOLLOWER LARGE SIGNAL PULSE FIGURE 20. N-CHANNEL CLAMP CURRENT vs OUTPUT FIGURE 21. P-CHANNEL CLAMP CURRENT vs OUTPUT VOLTAGE

20 TIME (µs)

The two different responses correspond to the two phases of the clock.

Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L A 1 -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3(JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93

Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpen- dicular to datum . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E14.3(JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 4 1 4 9 Rev. 0 12/93

Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0o 8o 0o 8o - Rev. 0 12/93

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 ICL7650S Metal Can Packages (Can) NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) fromα ,looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. Øb ØD2 Ø e k1 k βØb1 BASE AND SEATING PLANE F Q ØD ØD1 REFERENCE PLANE L A α Øb2Øb1 BASE METAL LEAD FINISH SECTION A-A A A N CL T8.C MIL-STD-1835 MACY1-X8 (A1)

8 LEAD METAL CAN PACKAGE

A 0.165 0.185 4.19 4.70 - Øb 0.016 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 Øb2 0.016 0.024 0.41 0.61 - ØD 0.335 0.375 8.51 9.40 - ØD1 0.305 0.335 7.75 8.51 - ØD2 0.110 0.160 2.79 4.06 - e 0.200 BSC 5.08 BSC - e1 0.100 BSC 2.54 BSC - F - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 L 0.500 0.750 12.70 19.05 1 L1 - 0.050 - 1.27 1 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 - α 45o BSC 45 o BSC 3 β 45o BSC 45 o BSC 3 N8 8 4 Rev. 0 5/18/94