ICL7611_06 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 13

Technical content

Features

  • Input Common Mode Voltage Range Greater Than Supply Rails (ICL7612)
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • Portable Instruments
  • Telephone Headsets
  • Hearing Aid/Microphone Amplifiers
  • Meter Amplifiers
  • Medical Instruments
  • High Impedance Buffers BAL -IN +IN IQ SET OUT BAL Data Sheet September 27, 2006 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN2919.8 September 27, 2006

Ordering Information

PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ICL7611DCBA 7611DCBA 0 to +70 8 Ld SOIC M8.15 ICL7611DCBAZ (Note) 7611DCBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15 ICL7611DCBA-T 7611DCBA 0 to +70 8 Ld SOIC Tape and Reel M8.15 ICL7611DCBAZ-T (Note) 7611DCBAZ 0 to +70 8 Ld SOIC Tape and Reel (Pb-free) M8.15 ICL7611DCPA 7611DCPA 0 to +70 8 Ld PDIP E8.3 ICL7611DCPAZ (Note) 7611DCPAZ 0 to +70 8 Ld PDIP* (Pb-free) E8.3 ICL7612BCPA 7612BCPA 0 to +70 8 Ld PDIP E8.3 ICL7612DCBA 7612DCBA 0 to +70 8 Ld SOIC M8.15 ICL7612DCBAZ (Note) 7612DCBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15 ICL7612DCBA-T 7612DCBA 0 to +70 8 Ld SOIC Tape and Reel M8.15 ICL7612DCBAZ-T (Note) 7612DCBAZ 0 to +70 8 Ld SOIC Tape and Reel (Pb-free) M8.15 ICL7612DCPA 7612DCPA 0 to +70 8 Ld PDIP E8.3 ICL7612DCPAZ (Note) 7612DCPAZ 0 to +70 8 Ld PDIP* (Pb-free) E8.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products em ploy special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ICL7611, ICL7612

3 FN2919.8 September 27, 2006 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 3) θJA (°C/W) (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time. 2. The outputs may be shorted to ground or to either supply, for VSUPPLY ≤10V. Care must be taken to insure that the dissipation rating is not exceeded. 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±5V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) ICL7612B ICL7611D, ICL7612D UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V OS RS ≤ 100kΩ +25 - - 5 - - 15 mV Full - - 7 - - 20 mV Temperature Coefficient of VOS ΔVOS/ΔTR S ≤ 100kΩ - - 15 - - 25 - μV/°C Input Offset Current I OS +25 - 0.5 30 - 0.5 30 pA Full - - 300 - - 300 pA Input Bias Current I BIAS +25 - 1.0 50 - 1.0 50 pA Full - - 400 - - 400 pA Common Mode Voltage Range (ICL7611 Only) V Extended Common Mode Voltage Range (ICL7612 Only) V Output Voltage Swing V OUT IQ = 10μA, RL = 1MΩ +25 ±4.9 - - ±4.9 - - V Large Signal Voltage Gain AVOL VO = ±4.0V, RL =1 MΩ, IQ = 10μA +25 80 104 - 80 104 - dB F u l l 7 5 --7 5 -- d B VO = ±4.0V, RL = 100kΩ, IQ = 100μA +25 80 102 - 80 102 - dB F u l l 7 5 --7 5 -- d B VO = ±4.0V, RL = 10kΩ, IQ = 1mA +25 76 83 - 76 83 - dB F u l l 7 2 --7 2 -- d B ICL7611, ICL7612

4 FN2919.8 September 27, 2006 Unity Gain Bandwidth GBW I Q = 10μA +25 - 0.044 - - 0.044 - MHz IQ = 100μA + 2 5 -0 . 4 8 - -0 . 4 8 - M H z IQ = 1mA +25 - 1.4 - - 1.4 - MHz Input Resistance R IN +25 - 10 12 -- 1 0 12 - Ω Common Mode Rejection Ratio CMRR R S ≤ 100kΩ, IQ = 10μA +25 70 96 - 70 96 - dB RS ≤ 100kΩ, IQ = 100μA +25 70 91 - 70 91 - dB RS ≤ 100kΩ, IQ = 1mA +25 60 87 - 60 87 - dB Power Supply Rejection Ratio (VSUPPLY = ±8V to ±2V) PSRR R S ≤ 100kΩ, IQ = 10μA +25 80 94 - 80 94 - dB RS ≤ 100kΩ, IQ = 100μA +25 80 86 - 80 86 - dB RS ≤ 100kΩ, IQ = 1mA +25 70 77 - 70 77 - dB Input Referred Noise Voltage eN RS = 100Ω, f = 1kHz +25 - 100 - - 100 - nV/ √Hz Input Referred Noise Current iN RS = 100Ω, f = 1kHz +25 - 0.01 - - 0.01 - pA/ √Hz Supply Current (No Signal, No Load) ISUPPLY IQ SET = +5V, Low Bias +25 - 0.01 0.02 - 0.01 0.02 mA IQ SET = 0V, Medium Bias +25 - 0.1 0.25 - 0.1 0.25 mA IQ SET = -5V, High Bias +25 - 1.0 2.5 - 1.0 2.5 mA Channel Separation V O1/VO2 AV = 100 +25 - 120 - - 120 - dB Slew Rate (AV = 1, CL = 100pF, VIN = 8VP-P) SR I Q = 10μA, RL = 1MΩ +25 - 0.016 - - 0.016 - V/ μs IQ = 100μA, RL = 100kΩ +25 - 0.16 - - 0.16 - V/ μs IQ = 1mA, RL = 10kΩ +25 - 1.6 - - 1.6 - V/ μs Rise Time (VIN = 50mV, CL = 100pF) tr IQ = 10μA, RL = 1MΩ +25 - 20 - - 20 - μs IQ = 100μA, RL = 100kΩ +25 - 2 - - 2 - μs IQ = 1mA, RL = 10kΩ +25 - 0.9 - - 0.9 - μs Overshoot Factor (VIN = 50mV, CL = 100pF) OS I Q = 10μA, RL = 1MΩ +25 - 5 - - 5 - % IQ = 100μA, RL = 100kΩ +25 - 10 - - 10 - % IQ = 1mA, RL = 10kΩ +25 - 40 - - 40 - % Electrical Specifications VSUPPLY = ±5V, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) ICL7612B ICL7611D, ICL7612D UNITSMIN TYP MAX MIN TYP MAX Electrical Specifications VSUPPLY = ±1V, IQ = 10μA, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) ICL7612B UNITSMIN TYP MAX Input Offset Voltage V OS RS ≤ 100kΩ +25 - - 5 mV Full - - 7 mV Temperature Coefficient of VOS ΔVOS/ΔTR S ≤ 100kΩ -- 1 5 - μV/°C Input Offset Current I OS +25 - 0.5 30 pA Full - - 300 pA Input Bias Current I BIAS +25 - 1.0 50 pA Full - - 500 pA Extended Common Mode Voltage Range VCMR +25 +0.6 to -1.1 -- V Output Voltage Swing V OUT RL = 1MΩ +25 ±0.98 - - V Full ±0.96 - - V ICL7611, ICL7612

5 FN2919.8 September 27, 2006 Schematic Diagram Large Signal Voltage Gain A VOL VO = ±0.1V, RL =1 MΩ +25 - 90 - dB Full - 80 - dB Unity Gain Bandwidth GBW +25 - 0.044 - MHz Input Resistance R IN +25 - 10 12 - Ω Common Mode Rejection Ratio CMRR R S ≤ 100kΩ +25 - 80 - dB Power Supply Rejection Ratio PSRR R S ≤ 100kΩ +25 - 80 - dB Input Referred Noise Voltage e N RS = 100Ω, f = 1kHz +25 - 100 - nV/ √Hz Input Referred Noise Current i N RS = 100Ω, f = 1kHz +25 - 0.01 - pA/ √Hz Supply Current I SUPPLY No Signal, No Load +25 - 6 15 μA Slew Rate SR A V = 1, CL = 100pF, VIN = 0.2VP-P, RL =1 MΩ Rise Time t r VIN = 50mV, CL = 100pF RL = 1MΩ +25 - 20 - μs Overshoot Factor OS V IN = 50mV, CL = 100pF, RL = 1MΩ +25 - 5 - % Electrical Specifications VSUPPLY = ±1V, IQ = 10μA, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) ICL7612B UNITSMIN TYP MAX INPUT STAGE SETTING STAGE IQ OUTPUT STAGE OUTPUT QN11QN10QN9 CFF = 9pF CC = 33pF QP9 QP8 QP7QP6 6.3V QN7 QN6 QN5 QN4 V+ I Q SET QN8 QN3 QN1 QN2 QP1 QP1 3k3k BAL 100k 900k QP5 QP4QP3 +INPUT -INPUT BAL 6.3V ICL7611, ICL7612

12 FN2919.8 September 27, 2006 ICL7611, ICL7612 Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2919.8 September 27, 2006 ICL7611, ICL7612 Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93