7560

7560 RENESAS | Alldatasheet

Document overview

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Technical content

DESCRIPTION

The 7560 group (A version) is the 8-bit microcomputer based on the 740 family core technology. The 7560 group (A version) has the LCD drive control circuit, an 8- channel A-D converter, D-A converter, serial I/O and PWM as ad- ditional functions. The various microcomputers in the 7560 group (A version) include variations of internal memory size and packaging. For details, re- fer to the section on part numbering. For details on availability of microcomputers in the 7560 group (A version), refer the section on group expansion.

FEATURES

(at 10 MHz oscillation frequency)

• Memory size
• LCD drive control circuit
• 2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage In high-speed mode (f(X
• Power dissipation (at 10MHz oscillation frequency, V CC = 5 V, Ta = 25 °C)

APPLICATIONS

Camera, household appliances, consumer electronics, etc.

7560 Group (A version)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0039-0102Z Rev.1.02 2003.07.31 Rev.1.02 Jul 31, 2003 page 1 of 69

Rev.1.02 Jul 31, 2003 page 2 of 69 Package type : 100P6Q-A PIN CONFIGURATION (TOP VIEW) Fig. 2 Pin configuration (Package type: 100P6Q-A) 1 23456789 1 01 11 21 31 41 51 81 92 02 12 42 5 152535 4 5 5 5 657585 960 61 626 3646 5666 7686 9 7 0 7 1 7 2 7 3747 0 1 M37560MXA-XXXGP S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G VC C VR E F AVSS C O C O COM1 COM0 VL VL VL P A P A P A P A P A D T D P D P C N T P C N T P I N P P 43/φ/ TO U T P 53/ R T P R T P P W P P W P P I N P72 P73 P71 P70/INT0 XCIN XCOUT XIN XOUT VSS P27 P26 P25 P24 P23 P21 P16 P22 P20 P17 RESET P76 P75 P74 P15/SEG39 P14/SEG38 P S E P S E P S E P S E P S E S E G S E G S E G P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E S E G S E G P SC L K A P SO U T A P SI N A P SC L K A P SC L K P TXD P RXD P SR D Y Package type : 100P6S-A Fig. 1 Pin configuration (Package type: 100P6S-A) PIN CONFIGURATION (TOP VIEW) 1 23456789 1 31 41 51 61 71 81 92 02 12 51 52 53 545 5 5 6 5 7585 9 6 0616 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3747 5 7 6 7 7 7 8 7 9 8 M M X A X X X F P SEG9 P 31/ S E P S E P S E P S E P S E S E G S E G S E G S E G S E G S E G P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E P S E VL P 67/ A P 66/ A P 65/ A P 64/ A P 62/ SC L K A P 61/ SO U T A P 60/ SI N A P 57/ A D T D P 56/ D P 55/ C N T P 54/ C N T P 53/ R T P 52/ R T P 51/ P W P 50/ P W P 46/ SC L K P 45/ TXD P 44/ RXD P 43/φ/ TO U T P 42/ I N P 41/ I N P P P P P VL2 VL COM0 COM1 C O VR E F A V S S VC C SEG8 SEG0 SEG1 SEG2 SEG4 SEG5 SEG6 SEG7 SEG3 P72 P73 P71 P70/INT0 XCIN XCOUT XIN XOUT VSS P P26 P P P P21 P16 P P P RESET S E G S E G C O M P 47/ SR D Y P 63/ SC L K A

Rev.1.02 Jul 31, 2003 page 3 of 69 FUNCTIONAL BLOCK DIAGRAM (Package type: 100P6S-A) Fig. 3 Functional block diagram I N N C N T R C N T R D A A D TC P U A X Y S P C H P C L P SR E S E T V C C V S S ( 5 V ( 0 V ) R O M R A M 3 5 9 1 4 0 P 4 P 2 P 0 P 1 P 6 P 7 P 3 P 5 12 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 3 6 3 7 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 1 0 9 3 9 2 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 X C I N X C O U T X I N O U T X C O U T X X C I N S I O V R E F A V S S V L C C V L V L C O M C O M C O M C O M S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G φ X C I N C O U T X 3 8 3 9 S I O P W M φ I N D - A D - A D A T O U T L C D d r i v e c o n t r o l c i r c u i t L C D d i s p l a y R A M b y t e s T i m e r X T i m e r Y T i m e r T i m e r T i m e r D a t a b u s C l o c k g e n e r a t i n g c i r c u i t M a i n c l o c k i n p u t M a i n cl o c k o u t p u t S u b c l o c k o u t p u t S u b c l o c k i n p u t R e s e t K e y i n p u t ( K e y - o n w a k e u p ) i n t e r r u p t R e a l t i m e p o r t f u n c t i o n A - D c o n v e r t e r I O p o r t P I O p o r t P I O p o r t P I O p o r t P I O p o r t P I O p o r t P O u t p u t p o r t P I O p o r t P R e s e t i n p u t S u b c l o c k o u t p u t S u b c l o c k i n p u t W a t c h d o g t i m e r

Rev.1.02 Jul 31, 2003 page 4 of 69 Table 1 Pin description (1) VCC VSS FunctionPin Name Function except a port function

• LCD segment output pins Power source • Apply voltage of power source to V CC, and 0 V to V SS. (For the limits of V CC, refer to “Recom- mended operating conditions”. VREF AVSS RESET XIN XOUT VL1–VL3 C1, C2 COM0–COM3 SEG0–SEG17 P00/SEG26– P07/SEG33 P10/SEG34– P15/SEG39 P16, P17 P20 – P27 P30/SEG18 – P37/SEG25 Analog refer- ence voltage Analog power source Reset input Clock input Clock output LCD power source Charge-pump capacitor pin Common output Segment output I/O port P0 I/O port P1 I/O port P2 Output port P3
• Reference voltage input pin for A-D converter and D-A converter.
• GND input pin for A-D converter and D-A converter.
• Connect to VSS.
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the X IN pin and leave the X OUT pin open. A feedback resistor is built-in.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
• Input 0 – V L3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 when a voltage is multiplied.)
• External capacitor pins for a voltage multiplier (3 times) of LCD control.
• LCD common output pins.
• COM2 and COM3 are not used at 1/2 duty ratio.
• COM3 is not used at 1/3 duty ratio.
• LCD segment output pins.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• I/O direction register allows each 8-bit pin to be pro- grammed as either input or output.
• 6-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• I/O direction register allows each 6-bit pin to be pro- grammed as either input or output.
• 2-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit output.
• CMOS 3-state output structure.
• Port output control is enabled.
• Key input (key-on wake-up) interrupt input pins
• LCD segment output pins

Rev.1.02 Jul 31, 2003 page 5 of 69 Table 2 Pin description (2) FunctionPin Name Function except a port function P40 P41/INT1, P42/INT2 P43/φ/TOUT P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/PWM0, P51/PWM1 P52/RTP0, P53/RTP1 P54/CNTR0, P55/CNTR1 P56/DA1 P57/ADT/DA2 P60/SIN2/AN0, P61/SOUT2/AN1, P62/SCLK21/AN2, P63/SCLK22/AN3 P64/AN4– P67/AN7 P70/INT0 P71–P77 I/O port P4 I/O port P5 I/O port P6 Input port P7 I/O port P7 Sub-clock output Sub-clock input

• 1-bit I/O port.
• CMOS compatible input level.
• N-channel open-drain output structure.
• I/O direction register allows this pin to be individually programmed as either input or output.
• 7-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 1-bit input port.
• INTi interrupt input pins
• System clock φ output pin
• Timer 2 output pin
• Serial I/O1 I/O pins
• PWM output pins
• Real time port output pins
• Timer X, Y I/O pins
• D-A converter output pin
• D-A converter output pin
• A-D external trigger input pin
• A-D converter input pins
• Serial I/O2 I/O pins
• A-D converter input pins XCOUT XCIN
• INT0 interrupt input pin
• 7-bit I/O port.
• CMOS compatible input level.
• N-channel open-drain output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Sub-clock generating circuit I/O pins. (Connect a oscillator. External clock cannot be used.)

Rev.1.02 Jul 31, 2003 page 6 of 69 Fig. 4 Part numbering M 3 7 5 6 0 M F A – X X X F PP r o d u c t R O M s i z e A B C D E F : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. M e m o r y t y p e M M a s k R O M v e r s i o n R O M n u m b e r Package type FP GP P S A P Q A C h a r a c t e r i s t i c s A : A v e r s i o n

Rev.1.02 Jul 31, 2003 page 7 of 69 Renesas expands the 7560 group (A version) as follows. Memory Type Support for mask ROM version. Memory Size Packages Memory Expansion Plan Fig. 5 Memory expansion plan ROM size (bytes) RAM size (bytes) 256 512 768 1024 1280 1536 1792192 2048 2304 2560 32K 28K 24K 20K 16K 12K 52K 48K 44K 40K 36K 56K 60K M37560M8A M37560MFA Produt under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. Currently planning products are listed below. Table 3 Support products As of Jul. 2003 Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Package 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A Part number M37560M8A-XXXFP M37560M8A-XXXGP M37560MFA-XXXFP M37560MFA-XXXGP RAM size (bytes) 102432768 (32638) 61440 (61310) ROM size (bytes) ROM size for User in ( ) 2560

Rev.1.02 Jul 31, 2003 page 8 of 69 CENTRAL PROCESSING UNIT (CPU) The 7560 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. The central processing unit (CPU) has six registers. Figure 6 shows the 740 Family CPU register structure. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as arithmetic data transfer, etc., are executed mainly through the ac- cumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. Figure 9 shows the operations of pushing register contents onto the stack and popping them from the stack. Table 6 shows the push and pop instructions of accumulator or processor status reg- ister. Store registers other than those described in Figure 9 with pro- gram when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. Fig. 6 740 Family CPU register structure A Accumulator b7 b0 b7b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counterPCH NV TB DI ZC Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

Rev.1.02 Jul 31, 2003 page 9 of 69 Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 7 Register push and pop at interrupt generation and subroutine call N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t r e q u e s t h e r e E x e c u t e J S R On-going Routine M S P CH) S S M S P C E x e c u t e R T S (PCL)M ( S ) S S S S (S) (S) + 1 P CH)M S S u b r o u t i n e P O P re t u r n a d d r e s s f r o m s t a c k P u s h r e t u r n a d d r e s s o n s t a c k M (S)( PS) Execute RTI P S S (S) (S) – 1 (S) (S) + 1 I n t e r r u p t S e r v i c e R o u t i n e POP contents of processor status register from stack M S P CH) (S) (S) – 1 M S P C (S) (S) – 1 (PCL)M ( S ) (S) (S) + 1 (S) (S) + 1 (PCH)M ( S ) POP return address from stack I F l a g i s s e t f r o m t o F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k Push contents of processor status register on stack Interrupt request (Note) Interrupt enable bit corresponding to each interrupt source is “1” Interrupt disable flag is “0”

Rev.1.02 Jul 31, 2003 page 10 of 69 [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arith- metic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z) The Z flag is set to “1” if the result of an immediate arithmetic op- eration or a data transfer is “0”, and set to “0” if the result is anything other than “0”.
• Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt gener- ated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
• Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was gen- erated by the BRK instruction. When the BRK instruction is generated, the B flag is set to “1” automatically. When the other interrupts are generated, the B flag is set to “0”, and the proces- sor status register is pushed onto the stack.
• Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed be- tween accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled be- tween memory locations.
• Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set to “1” if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory loca- tion operated on by the BIT instruction is stored in the V flag.
• Bit 7: Negative flag (N) The N flag is set to “1” if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Instructions to set each bit of processor status register to “0” or “1” Instruction setting to “1” Instruction setting to “0” C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

Rev.1.02 Jul 31, 2003 page 11 of 69 [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the system clock control bits, etc. The CPU mode register is allocated at address 003B 16. Fig. 8 Structure of CPU mode register Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Not used (“1” at reading) (Write “1” to this bit at writing) X C switch bit 0 : Oscillation stop 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) System clock selection bit 0 : XIN–XOUT selected (middle-/high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) Do not select CPU mode register ( C P U M ( C M ) : a d d r e s s 0 0 3 B1 b7 b0

Rev.1.02 Jul 31, 2003 page 12 of 69 Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 0000 16 to 00FF 16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF00 16 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 9 Memory map diagram 1 9 2 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 0A3F16 R A M a r e a R A M s i z e b y t e s A d d r e s s X X X 4 0 9 6 F 0 0 01 E D C B A F 0 8 01 E D C B A ROM area ROM size (bytes) A d d r e s s Y Y Y A d d r e s s Z Z Z 010016 000016 004016 FF0016 FFDC16 F F F E1 FFFF16 XXXX16 YYYY16 ZZZZ16 RAM R O M 005416 S F R a r e a N o t u s e d I n t e r r u p t v e c t o r a r e a Reserved ROM area (128 bytes) Z e r o p a g e S p e c i a l p a g e LCD display RAM area R e s e r v e d R O M a r e a

Rev.1.02 Jul 31, 2003 page 13 of 69 Fig. 10 Memory map of special function register (SFR) 0 0 2 01 0 2 1 0 2 2 0 2 3 0 2 4 002516 002616 0 2 7 0 2 8 0 2 9 0 2 002B16 002C16 002D16 0 2 002F16 0 3 0 0 3 1 003216 003316 003416 0 3 5 0 3 6 0 3 7 0 3 8 003916 003A16 0 3 003C16 003D16 003E16 003F16 0 0 0 0 0 1 0 0 2 0 0 3 0 0 4 000516 000616 0 0 7 0 0 8 0 0 9 0 0 000B16 000C16 000D16 0 0 0 0 0 1 0 0 1 1 001216 001316 001416 0 1 5 0 1 6 0 1 7 0 1 8 001916 001A16 001B16 0 1 001D16 001E16 0 1 P o r t P 0 r e g i s t e r ( P 0 ) P o r t P 1 r e g i s t e r ( P 1 ) P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) P o r t P 2 r e g i s t e r ( P 2 ) P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D ) P o r t P 3 r e g i s t e r ( P 3 ) Port P4 register (P4) P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D ) P o r t P 5 r e g i s t e r ( P 5 ) P o r t P 5 d i r e c t i o n r e g i s t e r ( P 5 D ) P o r t P 6 r e g i s t e r ( P 6 ) P o r t P 6 d i r e c t i o n r e g i s t e r ( P 6 D ) P o r t P 7 r e g i s t e r ( P 7 ) Port P7 direction register (P7D) S e r i a l I / O 1 s t a t u s r e g i s t e r ( S I O 1 S T S ) S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) B a u d r a t e g e n e r a t o r ( B R G ) I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) T i m e r 3 r e g i s t e r ( T 3 ) T i m e r X m o d e r e g i s t e r ( T X M ) I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) C P U m o d e r e g i s t e r ( C P U M ) I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) T i m e r X l o w - o r d e r r e g i s t e r ( T X L ) T i m e r Y l o w - o r d e r r e g i s t e r ( T Y L ) Timer 1 register (T1) T i m e r 2 r e g i s t e r ( T 2 ) T i m e r X h i g h - o r d e r r e g i s t e r ( T X H ) T i m e r Y h i g h - o r d e r r e g i s t e r ( T Y H ) P U L L r e g i s t e r A ( P U L L A ) PULL register B (PULLB) T i m e r Y m o d e r e g i s t e r ( T Y M ) Timer 123 mode register (T123M) TO U T/φ o u t p u t c o n t r o l r e g i s t e r ( C K O U T ) Segment output enable register (SEG) L C D m o d e r e g i s t e r ( L M ) A - D c o n t r o l r e g i s t e r ( A D C O N ) A - D c o n v e r s i o n h i g h - o r d e r r e g i s t e r A D H Transmit/Receive buffer register(TB/RB) K e y i n p u t c o n t r o l r e g i s t e r ( K I C ) P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) P o r t P 3 o u t p u t c o n t r o l r e g i s t e r ( P 3 C ) R e s e r v e d a r e a ( N o t e ) S e r i a l I / O 2 c o n t r o l r e g i s t e r ( S I O 2 C O N ) Serial I/O2 register (SIO2) PWM control register (PWMCON) P W M p r e s c a l e r ( P R E P W M ) P W M r e g i s t e r ( P W M ) R e s e r v e d a r e a ( N o t e ) R e s e r v e d a r e a ( N o t e ) Reserved area (Note) Reserved area (Note) D - A 1 c o n v e r s i o n r e g i s t e r ( D A 1 ) D - A 2 c o n v e r s i o n r e g i s t e r ( D A 2 ) D-A control register (DACON) Watchdog timer control register (WDTCON) Note: Do not write to the addresses of reserved area. A - D c o n v e r s i o n l o w - o r d e r r e g i s t e r ( A D L )

Rev.1.02 Jul 31, 2003 page 14 of 69 The I/O ports (ports P0, P1, P2, P4, P5, P6, P7 1–P77) have direc- tion registers. Ports P1 6, P17, P4, P5, P6, and P71–P77 can be set to input mode or output mode by each pin individually. P0 0–P07 and P10-P15 are respectively set to input mode or output mode in a lump by bit 0 of the direction registers of ports P0 and P1 (see Figure 11). When “0” is set to the bit corresponding to a pin, that pin becomes an input mode. When “1” is set to that bit, that pin becomes an output mode. If data is read from a port set to output mode, the value of the port latch is read, not the value of the pin itself. A port set to input mode is floating. If data is read from a port set to input mode, the value of the pin itself is read. If a pin set to input mode is written to, only the port latch is written to and the pin remains floating. Port P3 Output Control Register Bit 0 of the port P3 output control register (address 0007 16) en- ables control of the output of ports P3 0–P37. When the bit is set to “1”, the port output function is valid. When resetting, bit 0 of the port P3 output control register is set to “0” (the port output function is invalid) and pulled up. Fig. 11 Structure of port P0 direction register, port P1 direc- tion register Fig. 12 Structure of port P3 output control register Ports P00 to P07 direction register 0 : Input mode 1 : Output mode Not used (Undefined at reading) (If writing to these bits, write “0”.) Port P0 direction register (P0D : address 000116) b 7 b0 Note: In ports set to output mode, the pull-up control bit becomes invalid and pull-up resistor is not connected. Ports P10 to P15 direction register 0 : Input mode 1 : Output mode Not used (Undefined at reading) (If writing to these bits, write “0”.) Port P16 direction register Port P17 direction register 0 : Input mode 1 : Output mode Port P1 direction register (P1D : address 000316) b 7 b0 Ports P30 to P37 output control bit 0 : Output function is invalid (Pulled up) 1 : Output function is valid (No pull up) Not used (Undefined at reading) (If writing to these bits, write “0”.) Port P3 output control register (P3C : address 000716) b7 b0 Note: In pins set to segment output by segment output enable bits 0, 1 (bits 0, 1 of segment output enable register (address 3816)), this bit becomes invalid and pull-up resistor is not connected.

Rev.1.02 Jul 31, 2003 page 15 of 69 Fig. 13 Structure of PULL register A and PULL register B Pull-up Control By setting the PULL register A (address 0016 16) or the PULL reg- ister B (address 0017 16), ports P0 to P2, P4 to P6 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports set to output mode and the ports are no pulled up. The PULL register A setting is invalid for pins selecting segment output with the segment output enable register and the pins are not pulled up. P00, P01 pull-up control bit P02, P03 pull-up control bit P04–P07 pull-up control bit P10–P13 pull-up control bit P14, P15 pull-up control bit P16, P17 pull-up control bit P20–P23 pull-up control bit P24–P27 pull-up control bit P U L L r e g i s t e r A P U L L A a d d r e s s b 7 b 0 P41–P43 pull-up control bit P44–P47 pull-up control bit P50–P53 pull-up control bit P54–P57 pull-up control bit P60–P63 pull-up control bit P64–P67 pull-up control bit Not used “0” at reading) 0 : D i s a b l e E n a b l e P U L L r e g i s t e r B P U L L B a d d r e s s b7 b 0 Note: The contents of PULL register A and PULL register B do not affect ports set to output mode.

Rev.1.02 Jul 31, 2003 page 16 of 69 Diagram No.Related SFRsInput/OutputNamePin Non-Port FunctionI/O Format Table 6 List of I/O port function (1) P00/SEG26– P07/SEG33 P10/SEG34– P15/SEG39 P16 , P17 P20–P27 P30/SEG18– P37/SEG25 P40 P41/INT1, P42/INT2 P43/φ/TOUT P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/PWM0, P51/PWM1 P52/RTP0, P53/RTP1 P54/CNTR0 P55/CNTR1 P56/DA1 P57/ADT/ DA2 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Input/output, byte unit Input/output, 6-bit unit Input/output, individual bits Input/output, individual bits Output Input/output, individual bits Input/output, individual bits CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD segment output LCD segment output Key input (key-on wake-up) interrupt input LCD segment output INT i interrupt input Timer 2 output System clock φ output Serial I/O1 I/O Real time port output Timer X I/O Timer Y input PULL register A Segment output enable register PULL register A Segment output enable register PULL register A PULL register A Interrupt control register 2 Key input control register Segment output enable register Interrupt edge selection register PULL register B Timer 123 mode register TOUT/φ output control register PULL register B Serial I/O1 control register Serial I/O1 status register UART control register PULL register B PWM control register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B D-A control register PULL register B D-A control register A-D control register (1) (2) (1) (2) (4) (3) (13) (4) (12) (5) (6) (7) (8) (10) (9) (11) (14) (15) (15) Port P3 output control register

Rev.1.02 Jul 31, 2003 page 17 of 69 Pin Name I/O Format Non-Port Function Related SFR S Diagram No.Input/Output Notes 1: How to use double-function ports as function I/O pins, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or V CC before execution of the STP instruction. When an electric potential is at an intermediate potential, a current will flow from V CC to VSS through the input-stage gate and power source current may increase. Table 7 List of I/O port function (2) P60/SIN2/AN0 P61/SOUT2/ AN1 P62/SCLK21/ AN2 P63/SCLK22 / AN3 P64/AN4– P67/AN7 P70/INT0 P71–P77 COM0–COM3 SEG0–SEG17 Port P6 Port P7 Common Segment Input/ output, individual bits Input Input/ output, individual bits Output Output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level N-channel open-drain output LCD common output LCD segment output A-D converter input Serial I/O2 I/O A-D converter input INT 0 interrupt input PULL register B A-D control register Serial I/O2 control register A-D control register PULL register B Interrupt edge selection register (17) (18) (19) (20) (16) (23) (13) (21) (22) LCD mode register

Rev.1.02 Jul 31, 2003 page 18 of 69 Fig. 14 Port block diagram (1) (5) Port P44(4) Ports P16, P17, P2, P41, P42 Pull-up control VL1/VSS VL2/VL3/VCC VL1/VSS VL2/VL3/VCC VL1/VSS VL2/VL3/VCC (1) Ports P01–P07, P11–P15 Data bus Port latch Interface logic level shift circuit Pull-up Port Segment Segment/PortLCD drive timing Segment output enable bit Segment data Port direction register Port direction register (2) Ports P00, P10 Data bus Port latch Interface logic level shift circuit Port Segment Segment/PortLCD drive timing Segment data Port direction register Direction register Pull-up Data bus Port latch Interface logic level shift circuit Port Segment Segment/PortLCD drive timing Segment data Port P3 output control bit Pull-up(3) Port P3 Data bus Port latch Direction register Key input interrupt input INT 1, INT2 interrupt input Except P16, P17 Pull-up control Data bus Port latch Direction register Serial I/O1 enable bit Serial I/O1 input Receive enable bit Segment output enable bit Segment output enable bit Port P3 output control bit

Rev.1.02 Jul 31, 2003 page 19 of 69 Fig. 15 Port block diagram (2) (6) Port P45 (7) Port P46 (8) Port P47 (9) Ports P52,P53 (10) Ports P50,P51 PWM function enable bit PWM output (11) Port P54 Pulse output mode Timer output CNTR0 interrupt input Pull-up control Direction register Data bus Port latch Serial I/O1 output P45/TxD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Serial I/O1 clock output Direction register Data bus Port latch Pull-up controlSerial I/O1 enable bit Serial I/O1 clock input Serial I/O1 synchronous clock selection bit Serial I/O1 mode selection bit Serial I/O1 enable bit Pull-up control Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Port latch Serial I/O1 ready output Direction register Data bus Port latch Pull-up control Real time port control bit Real time port data Pull-up control Direction register Data bus Port latch Pull-up control Direction register Data bus Port latch

Rev.1.02 Jul 31, 2003 page 20 of 69 Fig. 16 Port block diagram (3) (12) Port P43 TOUT/φ output enable bit Timer 2 TOUT output System clock φ output TOUT/φ output selection bit (13) Ports P40,P71–P77 (14) Port P55 CNTR1 interrupt input (15) Ports P56,P57 A-D external trigger input D-A converter output Except P56 (16) Ports P64–P67 (17) Port P60 Analog input pin selection bit A-D converter input Serial I/O2 input DA1, DA2 output enable bits Direction register Port latchData bus Pull-up control Direction register Port latchData bus Direction register Port latchData bus Pull-up control Direction register Port latchData bus Pull-up control Direction register Port latchData bus Pull-up control Analog input pin selection bit A-D converter input Direction register Port latchData bus Pull-up control

Rev.1.02 Jul 31, 2003 page 21 of 69 Fig. 17 Port block diagram (4) (18) Port P61 (19) Port P62 (20) Port P63 Serial I/O2 output Serial I/O2 transmit end signal Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Pull-up control Analog input pin selection bit A-D converter input P61/SOUT2 P-channel output disable bit (21) COM0–COM3 (22) SEG0–SEG17 VL3 VL2 VL1 VSS VL2/VL3 VL1/VSS (23) Port P70 INT0 input Serial I/O2 synchronous clock selection bit Serial I/O2 clock output Serial I/O2 clock input Serial I/O2 port selection bit Synchronous clock output pin selection bit A-D converter input Serial I/O2 clock output A-D converter input Direction register Port latchData bus Pull-up control Direction register Port latchData bus Analog input pin selection bit Pull-up control Direction register Port latchData bus Analog input pin selection bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Data bus The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. The voltage applied to the sources of P- channel and N-channel transistors is the controlled voltage by the bias value. Synchronous clock output pin selection bit

Rev.1.02 Jul 31, 2003 page 22 of 69 Interrupts occur by seventeen sources: seven external, nine inter- nal, and one software. When an interrupt request is accepted, the program branches to the interrupt jump destination address set in the vector address (see Table 8). Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the BRK instruction. An interrupt is accepted if the corresponding interrupt request and enable bits are “1” and the in- terrupt disable flag is “0”. Interrupt enable bits can be set to “0” or “1” by program. Interrupt request bits can be set to “0” by program, but cannot be set to “1” by program. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. When the interrupt disable (I) flag is set to “1”, all interrupt requests except the BRK instruction interrupt and reset are not accepted. When several interrupt requests occur at the same time, the inter- rupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are auto- matically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt jump destination address is read from the vector table into the program counter. 3. The interrupt disable flag is set to “1” and the corresponding in- terrupt request bit is set to “0”. Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset is not an interrupt. Reset has the higher priority than all interrupts. Table 8 Interrupt vector addresses and priority RemarksInterrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT 0 input At detection of either rising or falling edge of INT 1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmit shift or when transmis- sion buffer is empty Interrupt Source LowHigh Priority Vector Addresses (Note 1) Reset (Note 2) INT0 INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 2 Timer 3 CNTR CNTR1 Timer 1 INT2 Serial I/O2 Key input (Key-on wake-up) ADT A-D conversion BRK instruction FFFD FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR 1 input At timer 1 underflow At detection of either rising or falling edge of INT 2 input At completion of serial I/O2 data transmission or reception At falling of conjunction of input level for port P2 (at input mode) At falling edge of ADT input At completion of A-D conversion At BRK instruction execution Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (valid at falling) Valid when ADT interrupt is selected External interrupt (valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt

Rev.1.02 Jul 31, 2003 page 23 of 69 Fig. 18 Interrupt control Fig. 19 Structure of interrupt-related registers ■ Notes on interrupts When setting the followings, the interrupt request bit may be set to “1”.

• When switching external interrupt active edge Related register: Interrupt edge selection register (address 3A 16) Timer X mode register (address 27 16) Timer Y mode register (address 28 16)
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection bit of A-D control reg- ister (bit 6 of address 34 16) When not requiring for the interrupt occurrence synchronous with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (polarity switch bit) or the inter- rupt source selection bit. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). I n t e r r u p t r e q u e s t b i t I n t e r r u p t e n a b l e b i t I n t e r r u p t d i s a b l e f l a g ( I ) BRK instruction Reset Interrupt request acceptance b7 b0 Interrupt edge selection register I N T0 i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t N o t u s e d a t r e a d i n g ( I N T E D G E : a d d r e s s 0 0 3 A1 Interrupt request register 1 I N T0 i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t S e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t b i t S e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t b i t T i m e r X i n t e r r u p t r e q u e s t b i t T i m e r Y i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t Interrupt control register 1 I N T0 i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t S e r i a l I O r e c e i v e i n t e r r u p t e n a b l e b i t S e r i a l I O t r a n s m i t i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t e n a b l e b i t T i m e r Y i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d (IREQ1 : address 003C16) ( I C O N 1 : a d d r e s s 0 0 3 E1 I n t e r r u p t r e q u e s t r e g i s t e r 2 C N T R0 i n t e r r u p t r e q u e s t b i t C N T i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t S e r i a l I O i n t e r r u p t r e q u e s t b i t K e y i n p u t i n t e r r u p t r e q u e s t b i t A D T A D c o n v e r s i o n i n t e r r u p t r e q u e s t b i t N o t u s e d a t r e a d i n g ( I R E Q 2 : a d d r e s s 0 0 3 D1 Interrupt control register 2 CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit Serial I/O2 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (“0” at reading) (Write “0” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16) 0 : Falling edge active 1 : Rising edge active b7 b0 b7 b0 b7 b0 b 7 b0

Rev.1.02 Jul 31, 2003 page 24 of 69 Key Input Interrupt (Key-on Wake Up) The key input interrupt is enabled when any of port P2 is set to in- put mode and the bit corresponding to key input control register is set to “1”. A Key input interrupt request is generated by applying “L” level voltage to any pin of port P2 of which key input interrupt is en- abled. In other words, it is generated when AND of input level goes from “1” to “0”. A connection example of using a key input in- terrupt is shown in Figure 22, where an interrupt request is gener- ated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P2 0–P23. Fig. 20 Connection example when using key input interrupt and port P2 block diagram P o r t P 20 l a t c h P o r t P 20 d i r e c t i o n r e g i s t e r P o r t P 21 l a t c h Port P21 direction register = “0” P o r t P 22 l a t c h Port P22 direction register = “0” Port P23 latch Port P23 direction register = “0” P o r t P 24 l a t c h Port P24 direction register = “1” P o r t P 25 l a t c h P o r t P 25 d i r e c t i o n r e g i s t e r Port P26 latch Port P26 direction register = “1” P o r t P 27 l a t c h Port P27 direction register = “1” P 20 i n p u t P21 input P i n p u t P 3 i n p u t P24 output P 5 o u t p u t P 6 o u t p u t P 7 o u t p u t P U L L r e g i s t e r A B i t P o r t P 2 I n p u t r e a d i n g c i r c u i t P o r t P X x L l e v e l o u t p u t ✽ P c h a n n e l t r a n s i s t o r f o r p u l l u p C M O S o u t p u t b u f f e r Key input interrupt request P 27 ke y i n p u t c o n t r o l b i t P 6 k e y i n p u t c o n t r o l b i t ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ P25 key input control bit P 4 k e y i n p u t c o n t r o l b i t P 3 k e y i n p u t c o n t r o l b i t = “ 1 ” PULL register A Bit 6 = “1” P22 key input control bit = “1” P 1 k e y i n p u t c o n t r o l b i t = “ 1 ” P20 key input control bit = “1”

Rev.1.02 Jul 31, 2003 page 25 of 69 The key input interrupt is controlled by the key input control regis- ter and the port direction register. When enabling the key input interrupt, set “1” to the key input control bit. A key input can be ac- cepted from pins set as the input mode in ports P2 0–P27. Fig. 21 Structure of key input control register P20 key input control bit P21 key input control bit P22 key input control bit P23 key input control bit P24 key input control bit P25 key input control bit P26 key input control bit P27 key input control bit 0 : K e y i n p u t i n t e r r u p t d i s a b l e d K e y i n p u t i n t e r r u p t e n a b l e d Key input control register (KIC : address 001516) b 7 b 0

Rev.1.02 Jul 31, 2003 page 26 of 69 The 7560 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Fig. 22 Timer block diagram “1” P55/CNTR1 “0” P54/CNTR0 Q Q T S “1” Q D Q D “1” Q T S “1” “1” P 43/φ/TOUT XC I N “0” “1” C N T R0 a c t i v e e d g e s w i t c h b i t T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t Real time port control bit “0” f ( XI N) / 1 6 f XC I w h e n φ XC I C N T R1 a c t i v e e d g e s w i t c h b i t Timer Y stop control bit Falling edge detection P e r i o d m e a s u r e m e n t m o d e Timer Y interrupt request Pulse width HL continuously measurement mode Rising edge detection T i m e r Y o p e r a t i n g m o d e b i t s Timer X interrupt request T i m e r X m o d e r e g i s t e r w r i t e s i g n a l P 43 d i r e c t i o n r e g i s t e r P u l s e o u t p u t m o d e P54 latch Timer X stop control bit Timer X write control bit L a t c h Timer X operat- ing mode bits Pulse width measurement mode C N T R 0 a c t i v e e d g e s w i t c h b i t Pulse output mode P54 direction register TO U T o u t p u t a c t i v e e d g e s w i t c h b i t T i m e r 2 w r i t e c o n t r o l b i t Timer 3 count source selection bit T i m e r 2 i n t e r r u p t r e q u e s t Timer 3 interrupt request T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t T i m e r 1 i n t e r r u p t r e q u e s t D a t a b u sR e a l t i m e p o r t c o n t r o l b i t R e a l t i m e p o r t c o n t r o l b i t Timer 3 latch (8) T i m e r 3 r e g i s t e r ( 8 ) Timer 1 latch (8) Timer 1 register (8) Timer 2 latch (8) Timer 2 register (8) Timer X low-order register (8) Timer X (low) latch (8) Timer X (high) latch (8) Timer Y (low) latch (8) Timer Y (high) latch (8) L a t c h P 3 l a t c h f ( X I N) / 1 6 f XC I w h e n φ XC I f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) f ( XI N) / 1 6 f XC I w h e n φ XC I P 52/ R T P0 P 3/ R T P1 RTP0 data for real time port RTP1 data for real time port P 2 d i r e c t i o n r e g i s t e r P 2 l a t c h P 3 d i r e c t i o n r e g i s t e r P 3 l a t c h φ Timer X high-order register (8) Timer Y low-order register (8) T i m e r Y h i g h - o r d e r r e g i s t e r ( 8 ) Q TOUT/φ output selection bit TOUT/φ output enable bit T O U T/φ o u t p u t e n a b l e b i t

Rev.1.02 Jul 31, 2003 page 27 of 69 Timer X is a 16-bit timer and is equipped with the timer latch. The division ratio of timer X is given by 1/(n+1), where n is the value in the timer latch. Timer X is a down-counter. When the contents of timer X reach “0000 16”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the timer X interrupt request bit is set to “1”. Timer X can be selected in one of four modes by the timer X mode register and can be controlled the timer X write and the real time port. (1) Timer mode The timer counts f(X IN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse output mode Each time the timer underflows, a signal output from the CNTR 0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the P5 4/CNTR0 pin to output mode (set “1” to bit 4 of port P5 direction register). (3) Event counter mode The timer counts signals input through the CNTR 0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the P5 CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction reg- ister). (4) Pulse width measurement mode The count source is f(X IN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR 0 active edge switch bit is “0”, the timer counts while the input signal of CNTR 0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR 0 pin is at “L”. When using a timer in this mode, set the P5 4/CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction register).

• Read and write to timer X high-order, low-order registers When reading and writing to the timer X high-order and low-order registers, be sure to read/write both the timer X high- and low-or- der registers. When reading the timer X high-order and low-order registers, read the high-order register first. When writing to the timer X high-order and low-order registers, write the low-order register first. The timer X cannot perform the correct operation if the next operation is per- formed.
• Write operation to the high- or low-order register before reading the timer X low-order register
• Read operation from the high- or low-order register before writing to the timer X high-order register Fig. 23 Structure of timer X mode register T i m e r X m o d e r e g i s t e r T X M a d d r e s s T i m e r X w r i t e c o n t r o l b i t W r i t e v a l u e i n l a t c h a n d t i m e r W r i t e v a l u e i n l a t c h o n l y R e a l t i m e p o r t c o n t r o l b i t R e a l t i m e p o r t f u n c t i o n i n v a l i d R e a l t i m e p o r t f u n c t i o n v a l i d R T d a t a f o r r e a l t i m e p o r t R T d a t a f o r r e a l t i m e p o r t T i m e r X o p e r a t i n g m o d e b i t s b b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e C N T a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m H o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e H p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m L o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e L p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T i n t e r r u p t T i m e r X s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p b7 b0
• Timer X Write Control Which write control can be selected by the timer X write control bit (bit 0) of the timer X mode register (address 0027 16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the timer X register and the timer is updated at next underflow. After reset, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the timer X register. The write operation is independent of timer X count operation, operating or stopping. When the value is written in latch only, a value is simultaneously set to the timer X and the timer X latch if the writing in the high- order register and the underflow of timer X are performed at the same timing. Unexpected value may be set in the high-order timer on this occasion.
• Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1” after set of the real time port data, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the P5 2/RTP0, P53/RTP1 pins to output mode (set “1” to bits 2, 3 of port P5 direction register). ■ Note on CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR 0 active edge switch bit.

Rev.1.02 Jul 31, 2003 page 28 of 69 Timer Y is a 16-bit timer and is equipped with the timer latch. The division ratio of timer Y is given by 1/(n+1), where n is the value in the timer latch. Timer Y is a down-counter. When the contents of timer Y reach “0000 16”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the timer Y interrupt request bit is set to “1”. Timer Y can be selected in one of four modes by the timer Y mode register. (1) Timer mode The timer counts f(X IN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period measurement mode CNTR1 interrupt request is generated at rising or falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for this, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising or falling of CNTR 1 pin input signal is retained until the next valid edge is input. The rising or falling timing of CNTR 1 pin input signal can be discriminated by CNTR 1 interrupt. When using a timer in this mode, set the P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5 direction register). (3) Event counter mode The timer counts signals input through the CNTR 1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the 5/CNTR1 pin to input mode (set “0” to bit 5 of port P5 direction register). (4) Pulse width HL continuously measure- ment mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the P5 5/CNTR 1 pin to input mode (set “0” to bit 5 of port P5 direction register). ■ Note on CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the value of the CNTR 1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal regardless of the value of CNTR 1 active edge switch bit. Fig. 24 Structure of timer Y mode register Timer Y mode register (TYM : address 002816) b7 b0 N o t u s e d a t r e a d i n g T i m e r Y o p e r a t i n g m o d e b i t s b T i m e r m o d e P e r i o d m e a s u r e m e n t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e C N T a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e M e a s u r e t h e f a l l i n g e d g e t o f a l l i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e M e a s u r e t h e r i s i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T i n t e r r u p t T i m e r Y s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p

Rev.1.02 Jul 31, 2003 page 29 of 69 Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers and is equipped with the timer latch. The count source for each timer can be selected by the timer 123 mode register. The division ratio of each timer is given by 1/(n+1), where n is the value in the timer latch. All timers are down-counters. When the contents of the timer reach “00 16”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”. When a value is written to the timer 1 register and the timer 3 reg- ister, a value is simultaneously set as the timer latch and the timer. When the timer 1 register, the timer 2 register, or the timer 3 regis- ter is read, the count value of the timer can be read.

• Timer 2 Write Control Which write can be selected by the timer 2 write control bit (bit 2) of the timer 123 mode register (address 0029 16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer 2 latch by writing data to the timer 2 register and the timer 2 is updated at next underflow. After reset, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the timer 2 latch and the timer 2 at the same time by writing data to the timer 2 register. If the value is written in latch only, a value is simultaneously set to the timer 2 and the timer 2 latch when the writing in the high- order register and the underflow of timer 2 are performed at the same timing.
• Timer 2 Output Control When the timer 2 (T OUT) output is enabled by the T OUT/φ output enable bit and the T OUT/φ output selection bit, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the P4 3/φ/TOUT pin to output mode (set “1” to bit 3 of port P4 direction register). ■ Note on Timer 1 to Timer 3 When the count source of timers 1 to 3 is changed, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may become undefined value because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 25 Structure of timer 123 mode register TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT/φ output enablel bit 0 : TOUT/φ output disabled 1 : TOUT/φ output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output signal 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output signal 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (“0” at reading) Timer 123 mode register (T123M :address 002916) Note: System clock φ is f(XCIN)/2 in the low-speed mode. b 7 b 0

Rev.1.02 Jul 31, 2003 page 30 of 69 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode is selected by setting the se- rial I/O1 mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O mode, the transmitter and the re- ceiver must use the same clock as an operation clock. When an internal clock is selected as an operation clock, transmit or receive is started by a write signal to the transmit buffer regis- ter. When an external clock is selected as an operation clock, serial I/ O1 becomes the state where transmit or receive can be performed by a write signal to the transmit buffer register. Transmit and re- ceive are started by input of an external clock. Fig. 26 Block diagram of clock synchronous serial I/O1 Fig. 27 Operation of clock synchronous serial I/O1 function P 46/ SC L K P 47/ SR D Y P 44/ RXD P45/TXD XI N 1 / 4 F / F Serial I/O1 status register S e r i a l I O c o n t r o l r e g i s t e r R e c e i v e b u f f e r r e g i s t e r Address 001816 Receive shift register R e c e i v e b u f f e r f u l l f l a g ( R B F ) Receive interrupt request Receive clock control circuit Shift clock Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 BRG count source selection bit F a l l i n g e d g e d e t e c t o r Data bus A d d r e s s 0 0 1 81 S h i f t c l o c k Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) T r a n s m i t i n t e r r u p t r e q u e s t Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit buffer register Transmit shift register Transmit clock control circuit R e c e i v e e n a b l e s i g n a l SR D Y D7D0 D1 D2 D3 D4 D5 D6 R B F = “ 1 ” T S C ”T B E = “ 0 ” TBE = “1” TSC = “0” T r a n s m i t a n d r e c e i v e s h i f t c l o c k t o o f t h e i n t e r n a l c l o c k o r a n e x t e r n a l c l o c k S e r i a l o u t p u t TXD S e r i a l i n p u t RXD W r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r a d d r e s s Overrun error (OE) detection Notes 1 : A f t e r d a t a t r a n s f e r r i n g , t h e T x D p i n k e e p s D7 o u t p u t v a l u e . I f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a c a n b e o u t p u t c o n t i n u o u s l y f r o m t h e TXD p i n S e l e c t t h e s e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t f a c t o r b e t w e e n w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d T B E o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d T S C b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r T h e s e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t o c c u r s w h e n t h e r e c e i v e b u f f e r f u l l f l a g R B F b e c o m e s D7D0 D1 D2 D3 D4 D5 D6 ( N o t e 1 ) ( N o t e 3 ) ( N o t e 2 ) (Note 3) ( N o t e 4 )

Rev.1.02 Jul 31, 2003 page 31 of 69 (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) is selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address (0018 16) in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted during transmitting, and the receive buffer register can hold re- ceived one-byte data while the next one-byte data is being re- ceived. Fig. 28 Block diagram of UART serial I/O1 Fig. 29 Operation of UART serial I/O1 function XIN O E P E F E Data bus R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 R e c e i v e s h i f t r e g i s t e r R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t B a u d r a t e g e n e r a t o r Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer register D a t a b u s Transmit shift register Address 001816 Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request Address 001916 S T d e t e c t o r S P d e t e c t o r U A R T c o n t r o l r e g i s t e r Address 001B16 C h a r a c t e r l e n g t h s e l e c t i o n b i t A d d r e s s 0 0 1 A1 B R G c o u n t s o u r c e s e l e c t i o n b i t Transmit interrupt source selection bit S e r i a l I / O 1 s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t Clock control circuit C h a r a c t e r l e n g t h s e l e c t i o n b i t b i t s b i t s S e r i a l I / O 1 c o n t r o l r e g i s t e r P 46/ SC L K Serial I/O1 status register P 44/ RXD P45/TXD T S C = “ 0 ” T B E R B F = “ 0 ” T B E = “ 0 ” T B E = “ 0 ” R B F = “ 1 ” R B F = “ 1 ” S TD0 D1 S P D0 D1S T S P T B E = “ 1 ” T S C S TD0 D1 S P D0 D1S T S P T r a n s m i t b u f f e r r e g i s t e r w r i t e s i g n a l ✽ G e n e r a t e d a t n d b i t i n s t o p b i t m o d e 1 s t a r t b i t o r d a t a b i t s o r p a r i t y b i t o r s t o p b i t s 1 : E r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e R B F f l a g b e c o m e s “ 1 ” ( a t 1 s t s t o p b i t f o r r e c e p t i o n ) . T h e s e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t o c c u r s w h e n t h e r e c e i v e b u f f e r f u l l f l a g R B F b e c o m e s S e l e c t t h e s e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t o c c u r r e n c e f a c t o r b e t w e e n w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d T B E o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d T S C b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r N o t e s S e r i a l o u t p u t T x D S e r i a l i n p u t R x D R e c e i v e b u f f e r r e g i s t e r r e a d s i g n a l T r a n s m i t o r r e c e i v e c l o c k ( N o t e s 1 , 2 ) ( N o t e s 1 , 2 )

Rev.1.02 Jul 31, 2003 page 32 of 69 [Transmit Buffer/Receive Buffer Register (TB/ RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write- only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer regis- ter is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is set to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set to “1”. A write signal to the serial I/O1 status register sets all the error flags (OE, PE, FE, and SE) (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial I/O1 enable bit (SIOE) also sets all the status flags to “0”, includ- ing the error flags. All bits of the serial I/O1 status register are set to “0” at reset, but if the transmit enable bit of the serial I/O1 control register has been set to “1”, the transmit shift register shift completion flag and the transmit buffer empty flag become “1”. [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of the bits which set the data format of an data transmit and receive, and the bit which sets the output structure of the P4 5/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator is the 8-bit counter equipped with a reload register. Set the division value of the BRG count source to the baud rate generator. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. ■ Notes on serial I/O When setting the transmit enable bit to “1”, the serial I/O1 transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronous with the transmission en- abled, take the following sequence. ➀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).

Rev.1.02 Jul 31, 2003 page 33 of 69 Fig. 30 Structure of serial I/O1 control registers BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. S RDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P4 4–P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44–P47 operate as serial I/O pins) Serial I/O1 control register (SIO1CON : address 001A16) b T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d a t r e a d i n g S e r i a l I / O 1 s t a t u s r e g i s t e r S I O S T S a d d r e s s b U A R T c o n t r o l r e g i s t e r U A R T C O N a d d r e s s Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (“1” at reading) b7 b0

Rev.1.02 Jul 31, 2003 page 34 of 69 Serial I/O2 can be used only for clock synchronous serial I/O. For serial I/O2, the transmitter and the receiver must use the same clock as a synchronous clock. When an internal clock is se- lected as a synchronous clock, the serial I/O2 is initialized and, transmit and receive is started by a write signal to the serial I/O2 register. When an external clock is selected as an synchronous clock, the serial I/O2 counter is initialized by a write signal to the serial I/O2 register, serial I/O2 becomes the state where transmission or re- ception can be performed. Write to the serial I/O2 register while S CLK21 is “H” state when an external clock is selected as an syn- chronous clock. Either P62/SCLK21 or P63/SCLK22 pin can be selected as an output pin of the synchronous clock. In this case, the pin that is not se- lected as an output pin of the synchronous clock functions as a I/ O port. [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight control bits for the serial I/O2 functions. After setting to this register, write data to the serial I/O2 register and start transmit and receive. Fig. 31 Structure of serial I/O2 control register Fig. 32 Block diagram of serial I/O2 function S e r i a l I / O 2 c o n t r o l r e g i s t e r S I O C O N a d d r e s s b 7 I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t b i t s f XI f XI f XI f XI f XI f XI S e r i a l I O p o r t s e l e c t i o n b i t I O p o r t SO U T SC L K SC L K s i g n a l o u t p u t P 61/ SO U T P c h a n n e l o u t p u t d i s a b l e b i t C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e T r a n s f e r d i r e c t i o n s e l e c t i o n b i t L S B f i r s t M S B f i r s t S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t E x t e r n a l c l o c k I n t e r n a l c l o c k S y n c h r o n o u s c l o c k o u t p u t p i n s e l e c t i o n b i t SC L K SC L K b 0 b 2 b 1 b 0 Do not select XIN “1” 0 ” 0 ” 1 ” 0 ” 1 ” SC L K N o t e ) / 8 / 1 6 / 3 2 / 6 4 / 1 2 8 / 2 5 6 D a t a b u s S e r i a l I / O 2 i n t e r r u p t r e q u e s t S e r i a l I / O 2 p o r t s e l e c t i o n b i t S e r i a l I / O 2 c o u n t e r ( 3 ) S e r i a l I / O 2 r e g i s t e r ( 8 ) S y n c h r o n o u s c i r c u i t S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t E x t e r n a l c l o c k I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t b i t s D i v i d e r P 3 l a t c h P 63/ SC L K P 2/ SC L K P 1/ SO U T P 0/ SI N P 62 l a t c h P 1 l a t c h N o t e ) N o t e : I t i s s e l e c t e d b y t h e s e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t , t h e s y n c h r o n o u s c l o c k o u t p u t p i n s e l e c t i o n b i t a n d t h e s e r i a l I O p o r t s e l e c t i o n b i t

Rev.1.02 Jul 31, 2003 page 35 of 69 Fig. 33 Timing of serial I/O2 function D7D0 D1 D2 D3 D4 D5 D6 S y n c h r o n o u s c l o c k N o t e Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Serial I/O2 register write signal (Notes 2, 3) S e r i a l I / O 2 i n t e r r u p t r e q u e s t b i t = “ 1 ” : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k , t h e d i v i d e r a t i o c a n b e s e l e c t e d b y s e t t i n g b i t s 0 t o 2 o f t h e s e r i a l I O c o n t r o l r e g i s t e r W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k t h e S O U T p i n g o e s t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n W h e n t h e e x t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k t h e SO U T p i n k e e p s o u t p u t l e v e l a f t e r t r a n s f e r c o m p l e t i o n . H o w e v e r i f s y n c h r o n o u s c l o c k s i n p u t a r e c a r r i e d o n t h e t r a n s m i t d a t a w i l l b e o u t p u t c o n t i n u o u s l y f r o m t h e SO U T p i n b e c a u s e s h i f t s o f s e r i a l I O s h i f t r e g i s t e r i s c o n t i n u e d a s l o n g a s s y n c h r o n o u s c l o c k s a r e i n p u t N o t e s

• Serial I/O2 Operating The serial I/O2 counter is initialized to “7” by writing to the serial I/O2 register. After writing, whenever a synchronous clock changes from “H” to “L”, data is output from the SOUT2 pin. Moreover, whenever a syn- chronous clock changes from “L” to “H”, data is taken in from the SIN2 pin, and 1 bit shift of the serial I/O2 register is carried out si- multaneously. When the internal clock is selected as a synchronous clock, it is as follows if a synchronous clock is counted 8 times.
• Serial I/O2 counter = “0”
• Synchronous clock stops in “H” state
• Serial I/O2 interrupt request bit = “1” The SOUT2 pin is in a high impedance state after transfer is com- pleted. When the external clock is selected as a synchronous clock, if a synchronous clock is counted 8 times, the serial I/O2 interrupt re- quest bit is set to “1”, and the S OUT2 pin holds the output level of D7. However, if a synchronous clock continues being input, the shift of the serial I/O2 register is continued and transmission data continues being output from the S OUT2 pin.

Rev.1.02 Jul 31, 2003 page 36 of 69 PULSE WIDTH MODULATION (PWM) The 7560 group has a PWM function with an 8-bit resolution, using f(XIN) or f(XIN)/2 as a count source. Data Setting The PWM output pins are shared with ports P5 0 and P51. Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an “H” by the PWM register. If PWM count source is f(X IN) and the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1)/f(X IN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz) Output pulse “H” period = PWM period ✕ m/255 (when f(XIN) = 8 MHz) PWM Operation When either bit 1 (PWM 0 function enable bit) or bit 2 (PWM 1 func- tion enable bit) of the PWM control register or both bits are enabled, operation starts from initializing status, and pulses are output starting at “H”. When one PWM output is enabled and that the other PWM output is enabled, PWM output which is enabled to output later starts pulse output from halfway of PWM period (see Figure 37). When the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Fig. 34 Timing of PWM cycle Fig. 35 Block diagram of PWM function 31.875 ✕ m ✕ (n+1) 255 µs PWM output m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when f(XIN) = 8 MHz) D a t a b u s Count source selection bit “0” “ 1 ” P W M p r e s c a l e r p r e l a t c h P W M r e g i s t e r p r e l a t c h PWM prescaler latch P W M r e g i s t e r l a t c h Transfer control circuit P W M c i r c u i t XI N PWM0 function enable bit P 51 / P W M1 PWM prescaler P W M1 f u n c t i o n e n a b l e b i t P o r t P 51 l a c t h P o r t P 50 l a c t h P 50 / P W M0

Rev.1.02 Jul 31, 2003 page 37 of 69 Fig. 37 PWM output timing when PWM register or PWM prescaler is changed Fig. 36 Structure of PWM control register b 7 b P W M c o n t r o l r e g i s t e r P W M C O N a d d r e s s B C o u n t s o u r c e s e l e c t i o n b i t 0:f XI 1:f XI P W f u n c t i o n e n a b l e b i t 0:P W d i s a b l e d 1:P W e n a b l e d P W f u n c t i o n e n a b l e b i t 0:P W d i s a b l e d 1:P W e n a b l e d N o t u s e d a t r e a d i n g T T2 CB T PWM register write signal PWM prescaler write signal (Changes from “A” to “B” during “H” period) (Changes from “T” to “T2” during PWM period) PWM (internal) A B T C T2= stop PWM0 function enable bit PWM1 function enable bit PWM0 output Port PortPWM1 output Port stop Port When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.

Rev.1.02 Jul 31, 2003 page 38 of 69 [A-D Conversion Low-Order Register (ADL)] 001416 [A-D Conversion High-Order Register (ADH)] 003516 The A-D conversion registers are read-only registers that store the result of an A-D conversion . When reading this register during an A-D conversion, the previous conversion result is read. The high-order 8 bits of a conversion result is stored in the A-D conversion high-order register (address 0035 16), and the low-or- der 2 bits of the same result are stored in bit 7 and bit 6 of the A-D conversion low-order register (address 0014 16). Bit 0 of the A-D conversion low-order register is the conversion mode selection bit. When this bit is set to “0”, that becomes the 10-bit A-D mode. When this bit is set to “1”, that becomes the 8-bit A-D mode. [A-D Control Register (ADCON)] 003416 The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 indi- cates the completion of an A-D conversion. The value of this bit re- mains at “0” during an A-D conversion, then it is set to “1” when the A-D conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 is the V REF input switch bit which controls connection of the resistor ladder and the reference voltage input pin (V REF). The resistor ladder is always connected to V REF when bit 4 is set to “1”. When bit 4 is set to “0”, the resistor ladder is cut off from VREF except for A-D conversion performed. When bit 5, which is the AD external trigger valid bit, is set to “1”, A-D conversion starts also by a falling edge of an ADT input. When using an A-D external trigger, set the P5 7/ADT pin to input mode (set “0” to bit 7 of port P5 direc- tion register). Comparison Voltage Generator The comparison voltage generator divides the voltage between AV SS and VREF by 256 (when 8-bit A-D mode) or 1024 (when 10- bit A-D mode), and outputs the divided voltages. Channel Selector The channel selector selects one of the input ports P67/AN7–P60/AN0. Comparator and Control Circuit The comparator and control circuit compare an analog input volt- age with the comparison voltage and store the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD converter interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(X IN) to 500 kHz or more during an A-D conversion. Use the clock divided from the main clock f(XIN) as the system clock Fig. 38 Structure of A-D converter-related registers A-D control register (ADCON : address 003416) A D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d A n a l o g i n p u t p i n s e l e c t i o n b i t s b b b P 60/ A P 61/ A P 62/ A P 63/ A P 64/ A P 65/ A P 66/ A P 67/ A VR E F i n p u t s w i t c h b i t A U T O O N A D e x t e r n a l t r i g g e r v a l i d b i t A D e x t e r n a l t r i g g e r i n v a l i d A D e x t e r n a l t r i g g e r v a l i d b 7 b 0 I n t e r r u p t s o u r c e s e l e c t i o n b i t I n t e r r u p t r e q u e s t a t A D c o n v e r s i o n c o m p l e t e d I n t e r r u p t r e q u e s t a t A D T i n p u t f a l l i n g N o t u s e d ( “ 0 ” a t r e a d i n g ) A-D conversion low-order register (ADL : address 001416) Conversion mode selection bit 0 : 10-bit A-D mode 1 : 8-bit A-D mode Not used (“0” at reading)

• For 10-bit A-D mode A-D conversion result
• For 8-bit A-D mode Not used (undefined at reading) b 7 b 0

Rev.1.02 Jul 31, 2003 page 39 of 69 Fig. 40 A-D converter block diagram Fig. 39 Read of A-D conversion register

• 1 0 - b i t r e a d i n g R e a d a d d r e s s t h e n A D c o n v e r s i o n h i g h o r d e r r e g i s t e r A D H A d d r e s s A D c o n v e r s i o n l o w o r d e r r e g i s t e r A D L A d d r e s s 6) b0 b 7 b b 1 b7 b6 b 5b 4b 3b 2 b 7 b0 b 9b 8b 7 b6 b5 b 4 b3 b 2 b 7 b0 ( h i g h - o r d e r ) l o w - o r d e r ) N o t e : Bi t s 0 t o 5 o f a d d r e s s 0 0 1 41 6 b e c o m e “ 0 ” a t r e a d i n g . b1 b0
• 8 - b i t r e a d i n g R e a d o n l y a d d r e s s A D c o n v e r s i o n h i g h o r d e r r e g i s t e r A D H A d d r e s s C o n v e r s i o n m o d e s e l e c t i o n b i t b i t A D m o d e b i t A D m o d e Comparato r A-D control circuit ADT/A-D interrupt request AVSS VRE P60/SIN2/AN0 Data bus A-D control register b b A-D conversion high-order register Resistor ladder Channel selector P67/ AN7 P66/ AN6 P65/ AN5 P64/ AN4 P63/SCLK22/AN3 P62/SCLK21/AN2 P61/SOUT2/AN1 P57/ADT/DA2 (Address 003516) A-D conversion low-order register (Address 001416)

Rev.1.02 Jul 31, 2003 page 40 of 69 The 7560 group has a D-A converter with 8-bit resolution and 2 channels (DA1, DA2). The D-A converter is started by setting the value in the D-A con- version register. When the DA1 output enable bit or the DA 2 output enable bit is set to “1”, the result of D-A conversion is output from the corresponding DA pin. When using the D-A converter, set the 6/DA1 pin and the P5 7/DA2 pin to input mode (set “0” to bits 6, 7 of port P5 direction register) and the pull-up resistor should be in the OFF state (set “0” to bit 3 of PULL register B) previously. The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V=V REF ✕ n/256 (n=0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are set to “00 16”, the DA1 output enable bit and the DA 2 output enable bit are set to “0”, and the P5 6/DA1 pin and the P5 7/DA2 pin goes to high impedance state. The DA converter is not buffered, so connect an external buffer when driving a low-impedance load. ■ Note on applied voltage to V REF pin When these pins are used as D-A conversion output pins, the Vcc level is recommended for the applied voltage to V REF pin. When the voltage below Vcc level is applied, the D-A conversion accuracy may be worse. Fig. 41 Structure of D-A control register Fig. 42 Block diagram of D-A converter D o u t p u t e n a b l e b i t D i s a b l e d E n a b l e d D o u t p u t e n a b l e b i t D i s a b l e d E n a b l e d N o t u s e d a t r e a d i n g W r i t e t o t h e s e b i t s a t w r i t i n g b 7 b D A c o n t r o l r e g i s t e r D A C O N a d d r e s s 6)000000 Data bus P 56/ D A1 D - A 1 c o n v e r s i o n r e g i s t e r ( 8 ) R - 2 R r e s i s t o r l a d d e r D A 1 o u t p u t e n a b l e b i t D A 1 : a d d r e s s 0 0 3 2 P 7/ D A2 D - A 2 c o n v e r s i o n r e g i s t e r ( 8 ) R - 2 R r e s i s t o r l a d d e r D A 2 o u t p u t e n a b l e b i t D A 2 : a d d r e s s 0 0 3 3

Rev.1.02 Jul 31, 2003 page 41 of 69 Fig. 43 Equivalent connection circuit of D-A converter A VS S VREF 0 ” 1 ” M S B 0 ” “ 1 ” R R R R R R R R R R R2 R L S B R DA i D - A i c o n v e r s i o n r e g i s t e r D A i o u t p u t e n a b l e b i t

Rev.1.02 Jul 31, 2003 page 42 of 69 The 7560 group has the Liquid Crystal Display (LCD) drive control circuit consisting of the following.

• LCD display RAM
• Segment output enable register
• LCD mode register
• Voltage multiplier
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD Fig. 44 Structure of segment output enable register and LCD mode register enable bit is set to “1” (LCD ON) after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 9 Maximum number of display pixels at each duty ratio Duty ratio Maximum number of display pixel 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits S e g m e n t o u t p u t e n a b l e b i t 0 O u t p u t p o r t s P 30– P S e g m e n t o u t p u t S E S E S e g m e n t o u t p u t e n a b l e b i t O u t p u t p o r t s P 36, P S e g m e n t o u t p u t S E S E S e g m e n t o u t p u t e n a b l e b i t I O p o r t s P 00– P S e g m e n t o u t p u t S E S E S e g m e n t o u t p u t e n a b l e b i t I O p o r t s P 06, P S e g m e n t o u t p u t S E S E S e g m e n t o u t p u t e n a b l e b i t I O p o r t P S e g m e n t o u t p u t S E S e g m e n t o u t p u t e n a b l e b i t I O p o r t s P 11– P S e g m e n t o u t p u t S E S E L C D o u t p u t e n a b l e b i t D i s a b l e d E n a b l e d N o t u s e d a t r e a d i n g W r i t e t o t h i s b i t a t w r i t i n g Segment output enable register (SEG : address 003816) b7 b0 LCD mode register (LM : address 003916) Duty ratio selection bits b1b0 0 0 : Not used 0 1 : 2 duty (use COM0, COM1) 1 0 : 3 duty (use COM0–COM2) 1 1 : 4 duty (use COM0–COM3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Voltage multiplier control bit 0 : Voltage multiplier disable 1 : Voltage multiplier enable LCD circuit divider division ratio selection bits b6b5 0 0 : Clock input 0 1 : 2 division of Clock input 1 0 : 4 division of Clock input 1 1 : 8 division of Clock input LCDCK count source selection bit (Note) 0 : f(XCIN)/32 1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) N o t e : L C D C K i s a c l o c k f o r a L C D t i m i n g c o n t r o l l e r . b 7 b0

Rev.1.02 Jul 31, 2003 page 43 of 69 Fig. 45 Block diagram of LCD controller/driver D a t a b u s T i m i n g c o n t r o l l e r L C D d i v i d e r f ( XI N) / 8 1 9 2 f XC I i n l o w s p e e d m o d e f ( XC I N) / 3 2 C O M 0 C O M 1 C O M 2 C O M 3VS S VL 1 VL 2 VL E G E G E G E G A d d r e s s 0 0 4 01

6 A d d r e s s 0 0 4 11

1 ” 0 ” L C D C K L C D C K c o u n t s o u r c e s e l e c t i o n b i t L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s B i a s c o n t r o l b i t L C D e n a b l e b i t D u t y r a t i o s e l e c t i o n b i t s 2 2 S e l e c t o rS e l e c t o rS e l e c t o r S e l e c t o r S e l e c t o rS e l e c t o r L C D d i s p l a y R A MA d d r e s s 0 0 5 3 P 4/ S E G3 0/ S E G1 8 P 5/ S E G3 L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r C1 C2 V o l t a g e m u l t i p l i e r c o n t r o l b i t L e v e l S h i f t L e v e l S h i f t L e v e l S h i f t L e v e l S h i f t S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r B i a s c o n t r o l L C D o u t p u t e n a b l e b i t VC C

Rev.1.02 Jul 31, 2003 page 44 of 69 Voltage Multiplier (3 Times) The voltage multiplier performs threefold boosting. This circuit in- puts a reference voltage for boosting from LCD power input pin VL1. Set each bit of the segment output enable register and the LCD mode register in the following order for operating the voltage mul- tiplier. 1. Set the segment output enable bits (bits 0 to 5) of the seg- ment output enable register to “0” or “1”. 2. Set the duty ratio selection bits (bits 0 and 1), the bias con- trol bit (bit 2), the LCD circuit divider division ratio selection bits (bits 5 and 6), and the LCDCK count source selection bit (bit 7) of the LCD mode register to “0” or “1”. 3. Set the LCD output enable bit (bit 6) of the segment output enable register to “1” (enabled). Apply the limit voltage or less to the V L1 pin. 4. Set the voltage multiplier control bit (bit 4) of the LCD mode register to “1” (voltage multiplier enabled). However, be sure to select 1/3 bias for bias control. When voltage is input to the V L1 pin during operating the voltage multiplier, voltage that is twice as large as V L1 occurs at the V L2 pin, and voltage that is three times as large as V L1 occurs at the VL3 pin. ■ Notes on Voltage Multiplier When using the voltage multiplier, apply the limit voltage or less to the V L1 pin, then set the voltage multiplier control bit to “1” (en- abled). When not using the voltage multiplier, set the LCD output enable bit to “1”, then apply proper voltage to the LCD power input pins L1–VL3). When the LCD output enable bit is set to “0” (disabled) (during reset is included), the V L3 pin is connected to V CC inside of this microcomputer. When the voltage exceeding V CC is applied to VL3, apply VL3 voltage after setting the LCD output enable bit to “1” (enabled). Fig. 46 Example of circuit at each bias Table 10 Bias control and applied voltage to V L1–VL3 Bias value 1/3 bias 1/2 bias Voltage value VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD VL2=VL1=1/2 VLCD Note : V LCD is the maximum value of supplied voltage for the LCD panel. Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (V L1–VL3), apply the voltage shown in Table 10 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). R R R R 1/2 bias R R VCC VL VL VL R1 = R2 = R3 VCC VL3 VL2 VL1 VL VL VL Open Open C o n t r a s t c o n t r o l Open Open Contrast control 1 / 3 b i a s w h e n n o t u s i n g t h e v o l t a g e m u l t i p l i e r 1 / 3 b i a s w h e n u s i n g t h e v o l t a g e m u l t i p l i e r

Rev.1.02 Jul 31, 2003 page 45 of 69 (frequency of count source for LCDCK) (divider division ratio for LCD)f(LCDCK)= f(LCDCK) duty ratioFrame frequency= Fig. 47 LCD display RAM map Common Pin and Duty Ratio Control The common pins (COM 0–COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). After reset, the V CC (VL3) voltage is output from the common pins. LCD Display RAM Addresses 0040 16 to 005316 are the designated RAM for the LCD display. When “1” are written to these addresses, the correspond- ing segments of the LCD display panel are turned on. LCD Drive Timing The frequency of internal signal LCDCK decided LCD drive timing and the frame frequency can be determined with the following equation:Table 11 Duty ratio control and common pins used Duty ratio Common pins used Notes 1: COM2 and COM3 are open. 2: COM3 is open. Bit 1 Bit 0 COM0, COM1 (Note 1) COM0–COM2 (Note 2) COM0–COM3 Duty ratio selection bits Segment Signal Output Pins Segment signal output pins are classified into the segment-only pins (SEG 0–SEG 17), the segment or output port pins (SEG 18– SEG25), and the segment or I/O port pins (SEG 26–SEG39). Segment signals are output according to the bit data of the LCD RAM corresponding to the duty ratio. After reset, a V CC (=VL3) voltage is output to the segment-only pins and the segment/out- put port pins are the high impedance condition and pulled up to V CC (=VL3) voltage. Also, the segment/I/O port pins(SEG 26–SEG39) are set to input mode as I/O ports, and V CC (=VL3) is applied to them by pull-up resistor. 0 0 4 01 B i t A d d r e s s S E G1 S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E 76543210 C O M3 C O M0C O M2 C O M1 C O M0 COM3 COM2 C O M1 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG30 SEG32 SEG34 SEG36 SEG38

Rev.1.02 Jul 31, 2003 page 46 of 69 Fig. 48 LCD drive waveform (1/2 bias) I n t e r n a l s i g n a l L C D C K t i m i n g 1 / 4 d u t y V o l t a g e l e v e l VL3 VL2=VL1 VSS VL3 VSS C O M C O M C O M C O M SEG0 OFF ON OFF ON COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 / 3 d u t y VL3 VL2=VL1 VSS VL3 VSS O F F O N O NO F F ON O F F / 2 d u t y COM C O M C O M S E G C O M C O M SEG0 VL3 VL2=VL1 VSS VL3 VSS O F FO N OFFO N OFFO N O F FO N C O M 0 C O M 2 C O M

1 COM0 C

0 COM2

C O M 1 C O M 0 C O M

1 COM0

Rev.1.02 Jul 31, 2003 page 47 of 69 Fig. 49 LCD drive waveform (1/3 bias) I n t e r n a l s i g n a l L C D C K t i m i n g 1 / 4 d u t y Voltage level VL VS S C O M C O M C O M C O M S E G O F FO N O F FO N C O M

3 COM2 C

/ 3 d u t y O F F O N O NO F F ON O F F / 2 d u t y COM COM1 C O M S E G C O M C O M S E G OFFON OFFON OFFON OFFON VL VL VS S VL VL VL VS S VL1 VL3 VS S VL3 VL VSS VL VL VS S COM0 COM2 COM1 COM0 COM2 COM1 COM0 COM2 COM1 C O M 0 C O M 1 C O M

0 COM1 C

Rev.1.02 Jul 31, 2003 page 48 of 69 The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 6- bit watchdog timer H. At reset or writing to the watchdog timer control register (address 0037 16), the watchdog timer is set to “3FFF16”. When any data is not written to the watchdog timer con- trol register (address 0037 16) after reset, the watchdog timer is stopped. The watchdog timer starts to count down from “3FFF 16” by writing to the watchdog timer control register and an internal re- set occurs at an underflow. Accordingly, when using the watchdog timer function, write the watchdog timer control register before an underflow. The watchdog timer does not function when writing to the watchdog timer control register has not been done after reset. When not using the watchdog timer, do not write to it. When the watchdog timer control register is read, the following values are read:

• value of high-order 6-bit counter
• value of STP instruction disable bit
• value of count source selection bit. When the STP instruction disable bit is “0”, the STP instruction is enabled. The STP instruction is disabled when this bit is set to “1”. If the STP instruction which is disabled is executed, it is processed as an undefined instruction, so that a reset occurs internally. This bit can be set to “1” but cannot be set to “0” by program. This bit is “0” after reset. When the watchdog timer H count source selection bit is “0”, the detection time is set to 8.19 s at f(X CIN) = 32 kHz and 32.768 ms at f(XIN) = 8 MHz. When the watchdog timer H count source selection bit is “0”, the detection time is set to 32 ms at f(X CIN) = 32 kHz and 128 µs at f(XIN) = 8 MHz. There is no difference in the detection time be- tween the middle-speed mode and the high-speed mode. Fig. 50 Block diagram of watchdog timer Fig. 51 Structure of watchdog timer control register Fig. 52 Timing of reset output XIN Data bus XCIN “1” “0” Internal system clock selection bit (Note) “0” “1”1/16 Watchdog timer H count source selection bit Reset circuit Undefined instruction Reset “3F16” is set when watchdog timer is written to. Internal reset RESET Reset release time wait “FF16” is set when watchdog timer is written to. STP instruction STP instruction disable bit Watchdog timer H (6) Watchdog timer L (8) Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode. b 7 b 0 W a t c h d o g t i m e r r e g i s t e r W D T C O N a d d r e s s S T P i n s t r u c t i o n d i s a b l e b i t S T P i n s t r u c t i o n e n a b l e d S T P i n s t r u c t i o n d i s a b l e d W a t c h d o g t i m e r H c o u n t s o u r c e s e l e c i o n b i t W a t c h d o g t i m e r L u n d e r f l o w f XI o r f XC I W a t c h d o g t i m e r H ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t ) F F i s s e t t o t h e w a t c h d o g t i m e r b y w r i t i n g v a l u e s t o t h i s a d d r e s s I n t e r n a l r e s e t s i g n a l W a t c h d o g t i m e r d e t e c t i o n A p p r o x . 1 m s ( f ( XI N) = 8 M HZ) f ( X I

Rev.1.02 Jul 31, 2003 page 49 of 69 TOUT/φ OUTPUT FUNCTION The system clock φ or timer 2 divided by 2 (T OUT output) can be output from port P4 3 by setting the TOUT/φ output enable bit of the timer 123 mode register and the T OUT/φ output control register. Set the P4 3/φ/TOUT pin to output mode (set “1” to bit 3 of port P4 direction register) when outputting T OUT/φ. Fig. 53 Structure of T OUT/φ φφ φφ output-related registers TO U T/φ o u t p u t c o n t r o l b i t S y s t e m c l o c k φ o u t p u t TO U T o u t p u t N o t u s e d a t r e a d i n g TOUT/φ output control register (CKOUT : address 002A16) b7 b0 Timer 123 mode register (T123M : address 002916) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT/φ output enable bit 0 : TOUT/φ output disabled 1 : TOUT/φ output enabled Timer 2 write control bit 0 : Write data in latch and timer 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (“0” at reading) b 7 b 0

Rev.1.02 Jul 31, 2003 page 50 of 69 Fig. 54 Example of reset circuit RESET CIRCUIT When the power source voltage is within limits, and main clock XIN-XOUT is stable, or a stabilized clock is input to the X IN pin, if the RESET pin is held at an “L” level for 2 µs or more, the micro- computer is in an internal reset state. Then the RESET pin is returned to an “H” level, reset is released after approximate 8200 cycles of f(X IN), the program in address FFFD 16 (high-order byte) Fig. 55 Reset Sequence and address FFFC 16 (low-order byte). Make sure that the reset in- put voltage is less than 0.2 V CC(min.) for the power source voltage of VCC(min.). *VCC(min.) = Minimum value of power supply voltage limits applied to VCC pin VC CR E S E T VC CR E S E T Power source voltage detection circuit VC C R E S E T P o w e r o n . 2 V C C l e v e l O s c i l l a t i o n s t a b i l i z e d µs XI N 0 V 0 V N o t e N o t e: R e s e t r e l e a s e v o l t a g e V c c = V c c ( m i n . ) A DL F F F C FFFD A DH,U n d e f i n e d XI N : A p p r o x . 8 2 0 0 c y c l e s N o t e : T h e f r e q u e n c y o f s y s t e m c l o c k φ i s f ( XI N) d i v i d e d b y 8 . R e s e t a d d r e s s f r o m v e c t o r t a b l e RESET I n t e r n a l r e s e t A d d r e s s Data SYNC S y s t e m c l o c k φ XI N A DH A DLU n d e f i n e dU n defined U n d e f i n e d

Rev.1.02 Jul 31, 2003 page 51 of 69 Fig. 56 Internal state of microcomputer immediately after reset Note: The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined Register contentsAddress 000116 0 0 0 31 0 0 0 51 0 0 0 71 0 0 0 91 0 0 0 B1 0 0 0 D1 0 0 0 F1 0 0 1 41 0 0 1 61 001716 001916 0 1 001B16 0 0 1 D1 002016 0 0 2 11 0 0 2 21 0 0 2 31 0 0 2 41 0 0 2 51 002616 002716 002816 002916 0 2 0 2 0 0 3 21 0 0 3 31 0 0 3 41 0 0 3 61 0 0 3 71 003816 0 0 3 91 003A16 0 3 0 0 3 C1 003D16 003E16 003F16 (PS) ( P CH) (PCL) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (1) (2) (3) (4) (5) (6) (7) (8) (9) (35) (36) (37) (38) (39) (40) (41) (42) (43) T i m e r Y l o w o r d e r r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P U L L r e g i s t e r B T i m e r Y h i g h o r d e r r e g i s t e r S e r i a l I O c o n t r o l r e g i s t e r U A R T c o n t r o l r e g i s t e r T i m e r X h i g h o r d e r r e g i s t e r Timer X low-order register Timer X mode register T i m e r Y m o d e r e g i s t e r T i m e r m o d e r e g i s t e r S e r i a l I O s t a t u s r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r A D c o n t r o l r e g i s t e r Segment output enable register L C D m o d e r e g i s t e r P U L L r e g i s t e r A Interrupt edge selection register C P U m o d e r e g i s t e r Interrupt request register 1 I n t e r r u p t r e q u e s t r e g i s t e r Interrupt control register 1 I n t e r r u p t c o n t r o l r e g i s t e r Processor status register P r o g r a m c o u n t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P o u t p u t c o n t r o l r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r T i m e r r e g i s t e r T i m e r r e g i s t e r T i m e r r e g i s t e r A D c o n v e r s i o n l o w o r d e r r e g i s t e r 111000 0 0 100000 0 0 001111 1 1 1 0010 0 00 0016 0016 0016 0016 0016 0016 FF16 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 0016 0016 0016 3F16 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 Contents of address FFFD16 Contents of address FFFC16 D-A control register W a t c h d o g t i m e r c o n t r o l r e g i s t e r D-A1 conversion register D-A2 conversion register S e r i a l I O c o n t r o l r e g i s t e r TOUT/φ output control register PWM control register W a t c h d o g t i m e r h i g h o r d e r )(44) W a t c h d o g t i m e r l o w o r d e r FF16 0116 0016 00010 0 00 3F16 FF16(45) 0 0 1 51 e y i n p u t c o n t r o l r e g i s t e r 0016 ✕✕ 0000 1 0

Rev.1.02 Jul 31, 2003 page 52 of 69 Fig. 57 Oscillator circuit Fig. 58 External clock input circuit CLOCK GENERATING CIRCUIT The 7560 group has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub-clock X CIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting an oscil- lator between X IN and X OUT (XCIN and X COUT ). Use the circuit constants in accordance with the oscillator manufacturer’s recom- mended values. No external resistor is needed between X IN and XOUT since a feed-back resistor exists on-chip. However, an exter- nal feed-back resistor is needed between X CIN and XCOUT since a resistor does not exist between them. To supply a clock signal externally, input it to the X IN pin and make the XOUT pin open. The sub-clock oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external oscillator to oscillate. Immediately after poweron, only the X IN oscillation circuit starts oscillating, and X CIN and XCOUT pins go to high-impedance state. Frequency Control (1) Middle-speed mode The clock input to the X IN pin is divided by 8 and it is used as the system clock φ. After reset, this mode is selected. (2) High-speed mode The clock input to the X IN pin is divided by 2 and it is used as the system clock φ. (3) Low-speed mode

• The clock input to the X CIN pin is divided by 2 and it is used as the system clock φ.
• A low-power consumption operation can be realized by stopping the main clock in this mode. To stop the main clock, set the main clock stop bit of the CPU mode register to “1”. When the main clock is restarted, after setting the main clock stop bit to “0”, set enough time for oscillation to stabilize by pro- gram. Note: If you switch the mode between middle/high-speed and low- speed, stabilize both X IN and X CIN oscillations. The suffi- cient time is required for the sub clock to stabilize, espe- cially immediately after poweron and at returning from stop mode. When switching the mode between middle/high- speed and low-speed, set the frequency in the condition that f(X IN) > 3•f(XCIN). Oscillation Control (1) Stop mode If the STP instruction is executed, the system clock φ stops at an “H” level, and main and sub clock oscillators stop. In this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. Before the STP instruction, set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits are set to timer 1, high-order 8 bits are set to timer 2). Either f(X IN) or f(X CIN) divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are set to “0”. Set the timer 1 and timer 2 interrupt enable bits to “0” before ex- ecuting the STP instruction. Oscillation restarts at reset or when an external interrupt is re- ceived, but the system clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize when a ceramic resonator is used. (2) Wait mode If the WIT instruction is executed, only the system clock φ stops at an “H” state. The states of main clock and sub clock are the same as the state before the executing the WIT instruction, and oscilla- tion does not stop. Since supply of internal clock φ is started im- mediately after the interrupt is received, the instruction can be ex- ecuted immediately. XC I N CI N COUTCCIN CC O U T Rf R d XC O U T XI N XO U T XI N XO U T E x t e r n a l o s c i l l a t i o n c i r c u i t O p e n V CC VSS CC I N CC O U T R f R d X C I N XC O U T

Rev.1.02 Jul 31, 2003 page 53 of 69 Fig. 59 Clock generating circuit block diagram WIT instruction STP instruction System clock φ S R Q STP instruction S R Q M a i n c l o c k s t o p b i t S R Q T i m e r 2T i m e r 11 / 2 1 / 4 XI N XO U T XC O U TXC I N Interrupt request R e s e t T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t L o w - s p e e d m o d e M i d d l e - / H i g h - s p e e d m o d e Sy s t e m c l o c k s e l e c t i o n b i t (N o t e) Middle-speed mode High-speed mode or Low-speed mode N o t e : W h e n u s i n g t h e s u b c l o c k f o r t h e s y s t e m c l o c k φ, s e t t h e XC s w i t c h b i t t o “ 1 ” . M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t “1” “0” “ 1 ” “ 0 ” I n t e r r u p t d i s a b l e f l a g I XC switch bit (Note) “ 1 ” “ 0 ”

Rev.1.02 Jul 31, 2003 page 54 of 69 Fig. 60 State transitions of system clock N o t e s 1: Switch the mode according to the arrows shown between the mode blocks. (Do not switch between the mode directly without an arrow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3: When the stop mode is ended, a delay time can be set by timer 1 and timer 2. 4: Timer and LCD operate in the wait mode. 5: Wait until oscillation stabilizes after oscillating the main clock before the switching from the low-speed mode to middle-/high-speed mode. 6: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the system clock. CM4 : Xc switch bit 0: Oscillation stop 1: XCIN, XCOUT CM5 : Main clock (XIN–XOUT) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7 : System clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) C P U m o d e r e g i s t e r C P U M a d d r e s s b7 b4 R e s e t C M6 “0”“ 1 ” C M6 “ 0 ”“ 1 ” C M5 0 ”“ 1 ” C M 0 ”“ 1 ” M C “ 0 ” 1 ” 0 ” 1 ” C M C M 6“ 1 ” “ C M6 “0”“1” C M 0 ”“ 1 ” C M 0 ”“ 1 ” C M7 = 0 ( 8 M H z s e l e c t e d ) C M i d d l e s p e e d C M H z o s c i l l a t i n g C k H z s t o p p e d M i d d l e - s p e e d m o d e f M H z ) C M6 “ 0 ”“ 1 ” C M4 0 ”“ 1 ” C M 0 ”“ 1 ” CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) H i g h - s p e e d m o d e f M H z CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) M i d d l e - s p e e d m o d e f M H z CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) H i g h - s p e e d m o d e f M H z C M4 C M6 “ 0 ” 1 ” 0 ” 1 ” C M C M 6“ 1 ” “ CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) Low-speed mode (f(φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) L o w- s p e e d m o d e f k H z CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) L o w- s p e e d m o d e f k H z CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) L o w- s p e e d m o d e f k H z

Rev.1.02 Jul 31, 2003 page 55 of 69 The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags (T flag, D flag, etc.) which affect program execution. Interrupt When the contents of an interrupt request bits are changed by the program, execute a BBC or BBS instruction after at least one in- struction. This is for preventing executing a BBC or BBS instruction to the contents before change. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports Use instructions such as LDM and STA, etc., to set the port direc- tion registers. The contents of the port direction registers cannot be read. The following cannot be used:

• LDA instruction
• The memory operation instruction when the T flag is “1”
• The bit-test instruction (BBC or BBS, etc.)
• The read-modify-write instruction (calculation instruction such as ROR etc., bit manipulation instruction such as CLB or SEB etc.)
• The addressing mode which uses the value of a direction regis- ter as an index Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit en- able bit, the receive enable bit, and the S RDY output enable bit to “1”. The TxD pin of serial I/O1 retains the level then after transmission is completed. In serial I/O2 selecting an internal clock, the S OUT2 pin goes to high impedance state after transmission is completed. In serial I/O2 selecting an external clock, the S OUT2 pin retains the level then after transmission is completed. A-D Converter The input to the comparator is combined by internal capacitors. Therefore, since conversion accuracy may be worse by losing of an electric charge when the conversion speed is not enough, make sure that f(X IN) is at least 500 kHz during an A-D conver- sion. The normal operation of A-D conversion cannot be guaranteed when performing the next operation:
• When writing to CPU mode register during A-D conversion op- eration
• When writing to A-D control register during A-D conversion op- eration
• When executing STP instruction or WIT instruction during A-D conversion operation Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the system clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the system clock φ depends on the main clock division ratio selection bit and the system clock selection bit.

Rev.1.02 Jul 31, 2003 page 56 of 69 Countermeasures Against Noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20 mm).

• Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is com- pletely initialized. This may cause a program runaway. Fig. 62 Wiring for clock I/O pins (2) Connection of bypass capacitor across V SS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Fig. 61 Wiring for the RESET pin ➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for oscillation from other V SS patterns.
• Reason If noise enters clock I/O pins, clock waveforms may be de- formed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the V SS level of an oscil- lator, the correct clock will not be input in the microcomputer. Fig. 63 Bypass capacitor across the V SS line and the V CC line RESETReset circuit Noise VSSVSS Reset circuit V SS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K.

Rev.1.02 Jul 31, 2003 page 57 of 69 (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful espe- cially when range of voltage or/and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows.

• Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise oc- curs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise.
• Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines ➁ Installing oscillator away from signal lines where potential levels change frequently Fig. 64 Wiring for a large current signal line/ Wiring of signal lines where potential levels change frequently (4) Analog input The analog input pin is connected to the capacitor of a compara- tor. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A-D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A-D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A-D conversion accuracy, and the amount of proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evalua- tion for each product of every after confirming product specification. XI N XO U T VS S M i c r o c o m p u t e r Mutual inductance L a r g e c u r r e n t G N D M XI N XO U T VS S C N T R D o n o t c r o s s N.G.

Rev.1.02 Jul 31, 2003 page 58 of 69 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical cop- ies) or one floppy disk.

• For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/

Rev.1.02 Jul 31, 2003 page 59 of 69

ELECTRICAL CHARACTERISTICS

Table 12 Absolute maximum ratings RECOMMENDED OPERATING CONDITIONS Table 13 Recommended operating conditions (1) (V CC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Power source voltage Power source voltage A-D, D-A conversion reference voltage Analog power source voltage Analog input voltage AN 0–AN7 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 2.1 V CC VCC VCC VSS VLI VREF AVSS VIA Symbol Parameter Limits Min. V V V V V V V V V V V V V V Unit 4.5 4.0 3.0 2.0 3.0 2.0 1.8 1.8 0.15 ✕ f+1.3 1.3 2.0 AV SS 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 1.8 Typ. Max. Power source voltage (Note 1) VO VO VO Pd Topr Tstg –0.3 to 6.5 VPower source voltage Input voltage P0 0–P07, P10–P17, P20–P27, P40–P47, P50–P57, P60–P67 Input voltage P7 0–P77 Input voltage V L1 Input voltage V L2 Input voltage V L3 Input voltage C 1, C2 Input voltage RESET, X IN Output voltage C 1, C2 VCC VI Symbol Parameter Conditions Ratings Unit All voltages are based on V SS. Output transistors are cut off. VI VI VI VI VI VI VO VO VO Output voltage P0 0–P07, P10–P15, P30–P37 Output voltage P1 6, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77 Output voltage V L3 Output voltage V L2, SEG0–SEG17 Output voltage X OUT Power dissipation Operating temperature Storage temperature At output port At segment output Ta = 25°C –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VCC –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 V V V V V V V V V V V V V V mW High-speed mode Middle-speed mode Low-speed mode At start oscillating (Note 2) At using voltage multiplier f(X IN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz Notes 1: When using the A-D or D-A converter, refer to “A-D Converter Characteristics” or “D-A Converter characteristics”. 2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions. f: This is an oscillator’s oscillation frequency. For example, when oscillation frequency is 8 MHz, substitute “8”.

Rev.1.02 Jul 31, 2003 page 60 of 69 V V “H” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53, P56, P61, P64–P67, P71–P77 “H” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET X IN “L” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53, P56, P61, P64–P67, P71–P77 “L” input voltage P20–P27, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET X IN Table 14 Recommended operating conditions (2) (V CC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max. “H” input voltage “H” input voltage V IH VIH VIH VIH VIL VIL VIL VIL “L” input voltage “L” input voltage 0.7 V CC

0.8 VCC

V CC VCC VCC VCC

0.3 VCC

0.2 VCC

V V V V V V P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P40, P71–P77 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P40, P71–P77 (Note 1) P00–P07, P10–P15, P30–P37 (Note 2) “H” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 2) 0–P07, P10–P15, P30–P37 (Note 2) “L” peak output current P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 2) 0, P71–P77 (Note 2) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 3) 0–P07, P10–P15, P30–P37 (Note 3) “L” average output current P1 6, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 3) 0, P71–P77 (Note 3) –20 –20 –10 –10 –1.0 Table 15 Recommended operating conditions (3) (V CC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA Unit Typ. Max. “H” peak output current “L” peak output current “L” peak output current “H” average output current “H” average output current “L” average output current “L” average output current I OH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) –5.0 5.0 –0.5 –2.5 2.5 5.0 mA mA mA mA mA mA mA mA I OL(avg) mA10

Rev.1.02 Jul 31, 2003 page 61 of 69 Table 16 Recommended operating conditions (4) (V CC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Input frequency for timers X and Y (duty cycle 50%) f(CNTR0) f(CNTR1) Symbol Parameter Limits Min. MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz Unit Typ. Max. (VCC < 2.0 V) High-speed mode High-speed mode (4.0 V ≤ V CC < 4.5 V) High-speed mode (2.0 V ≤ V CC < 4.0 V) Middle-speed mode (Note 3) Middle-speed mode (Note 3) Middle-speed mode (Note 3) 32.768 5.0 2✕ VCC–4 VCC 5✕ VCC–8 10.0 4✕ VCC–8 2✕ VCC 10.0 8.0 6.0 Main clock input oscillation frequency (Note 1) Sub-clock input oscillation frequency (At duty 50 %) (Notes 2, 3) f(XIN) f(XCIN) Test conditions Notes 1: When using the A-D or D-A converter, refer to “A-D Converter Characteristics” or “D-A Converter characteristics”. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(X CIN) < f(XIN)/3. 3: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions.

Rev.1.02 Jul 31, 2003 page 62 of 69 IOL = 10 mA IOL = 3.0 mA IOL = 2.5 mA VCC = 2.2 V IOL = 5 mA IOL = 1.5 mA IOL = 1.25 mA VCC = 2.2 V VOL IOH = –1 mA IOH = –0.25 mA VCC = 2.2 V IOH = –5 mA IOH = –1.5 mA IOH = –1.25 mA VCC = 2.2 V VVCC–2.0“H” output voltage P00–P07, P10–P15, P30–P37 Symbol Parameter Limits Min. Unit 0.5 Typ. Max.Test conditions VOH 2.0 0.5 Table 17 Electrical characteristics (1) (V CC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) IOL = 10 mA IOL = 5 mA VCC = 2.2 V VCC = 2.0 V to 5.0 V VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” V CC = 5 V, VI = VSS Pull-ups “on” V CC = 2.2 V, VI = VSS Pull-ups “on” VI = VSS VI = VSS VCC = 5.0 V, VO = VCC, Pullup ON Output transistors “off” VCC = 2.2 V,VO = VCC, Pullup ON Output transistors “off” V O = VCC, Pullup OFF Output transistors “off” V O = VSS, Pullup OFF Output transistors “off” “H” output voltage P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 “L” output voltage P00–P07, P10–P15, P30–P37 “L” output voltage P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 “L” output voltage P40, P71–P77 Hysteresis INT0–INT2, ADT, CNTR0, CNTR1, P20–P27 Hysteresis S CLK, RXD, SIN2 Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P40–P47, P50–P57, P60–P67, P70–P77 “H” input current RESET “H” input current X IN “L” input current P00–P07,P10–P17, P20–P27,P41–P47, P50–P57, P60–P67 “L” input current P4 0, P70–P77 “L” input current RESET “L” input current X IN Output load current P30–P37 VOH VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH ILOAD VCC–2.0 VCC–0.5 –60.0 –5.0 0.5 0.5 4.0 –120.0 –20.0 –4.0 2.0 0.5 0.5 5.0 5.0 –5.0 –240.0 –40.0 –5.0 –5.0 –240.0 –40.0 V V V V V V V V V V µA µA µA µA µA µA µA µA I IL VCC–0.8 VCC–0.8 V V V0.8 V0.8 0.3 V µA µA µA Output leak current P30–P37 ILEAK 5.0 –5.0 µA µA –120.0 –20.0 –60.0 –5.0

Rev.1.02 Jul 31, 2003 page 63 of 69 Table 18 Electrical characteristics (2) (V CC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) V5.5

• High-speed mode, V CC = 5 V f(XIN) = 10 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• High-speed mode, V CC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• High-speed mode, V CC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter stop
• Low-speed mode, V CC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, V CC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, V CC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, V CC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” V L1 = 1.8 V Symbol Parameter Limits Min. UnitTyp. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC Power source current 4.5 VRAM RAM retention voltage At clock stop mode 1.8 IL1 Power source current (VL1) (Note) Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 0039 16) is “1”. 4.0 0.9 4.5 8.0 1.8 9.0 1.0 mA mA µA µA µA µA µA mA9.0 µA µA 0.1 4.0

Rev.1.02 Jul 31, 2003 page 64 of 69 Table 19 A-D converter characteristics (1) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted) 8-bit A-D mode (when conversion mode selection bit (bit 0 of address 001416) is “1”) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 2.7 to 5.5 V Bits LSB 150 µSConversion time Ladder resistor Reference power source input current tCONV RLADDER IVREF kΩ µA µA Table 21 D-A converter characteristics (VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution VCC = VREF = 5 V VCC = VREF = 2.7 V Bits µs kΩ mA 2.5 1.0 2.0 Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “00 16”, and excluding currents flowing through the A-D resistance ladder. (Note) Setting time Output resistor t su RO 4 3.2 Absolute accuracy Analog port input currentI IA IVREF Reference power source input current 100 200 5.0 VREF = 5 V Table 20 A-D converter characteristics (2) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted) 10-bit A-D mode (when conversion mode selection bit (bit 0 of address 001416) is “0”) 12.5 (Note) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution Absolute accuracy (excluding quantization error) V CC = VREF = 2.7 to 5.5 V Bits LSB 150 µSConversion time Ladder resistor Reference power source input current tCONV RLADDER IVREF kΩ µA Analog port input currentI IA µA 100 200 5.0 V REF = 5 V 15.5 (Note) Note: When the internal trigger is used in the middle-speed mode, the max. value of t CONV is 14 µS. Note: When the internal trigger is used in the middle-speed mode, the max. value of t CONV is 17 µS.

Rev.1.02 Jul 31, 2003 page 65 of 69 Table 22 Timing requirements (1) (V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) 100 1000/(4✕ Vcc-8) 200 1000/(2✕ Vcc-4) 105 105 800 370 370 220 100 1000 400 400 200 200 Note: When bit 6 of address 001A 16 is “1”. Divide this value by four when bit 6 of address 001A 16 is “0”. Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD–SCLK1) th(SCLK1–RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(RXD–SCLK2) th(SCLK2–RXD) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Typ. Max.

Rev.1.02 Jul 31, 2003 page 66 of 69 Table 23 Timing requirements (2) (V CC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) 125 1000/(10✕ Vcc-12) 1000/V CC 1000/(5✕ Vcc-8) tc(CNTR)/2–20 tc(CNTR)/2–20 Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns Unit Typ. Max. Note: When bit 6 of address 001A 16 is “1”. Divide this value by four when bit 6 of address 001A 16 is “0”. twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD–SCLK1) th(SCLK1–RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(RXD–SCLK2) th(SCLK2–RXD) 230 230 2000 950 950 400 200 2000 950 950 400 200 ns ns ns ns ns ns ns ns ns ns ns ns (VCC < 2.0 V) (VCC < 2.0 V) (VCC < 2.0 V) (VCC < 2.0 V)

Rev.1.02 Jul 31, 2003 page 67 of 69 Table 24 Switching characteristics (1) (V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Note: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B 16) is “0”. Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note) Serial I/O1 output valid time (Note) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time 140 0.2 ✕ tC (SCLK2) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns Unit tC (SCLK1)/2–30 tC (SCLK1)/2–30 –30 Typ. Max. twH(SCLK1) twL(SCLK1) td(SCLK1–TXD) tv(SCLK1–TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2–SOUT2) tv(SCLK2–SOUT2) tf(SCLK2) Table 25 Switching characteristics (2) (V CC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns Unit Notes1: When the P4 5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B 16) is “0”. 2: XOUT and XCOUT pins are excluded. Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time 350 100 100 0.2 ✕ tC (SCLK2) 100 Symbol Parameter Limits Min. tC (SCLK1)/2–100 tC (SCLK1)/2–100 –30 Max. twH(SCLK1) twL(SCLK1) td(SCLK1–TXD) tv(SCLK1–TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2–SOUT2) tv(SCLK2–SOUT2) tf(SCLK2) Typ. tC (SCLK2)/2–160 tC (SCLK2)/2–160 tC (SCLK2)/2–240 tC (SCLK2)/2–240 Fig. 65 Circuit for measuring output switching characteristics M e a s u r e m e n t o u t p u t p i n 100 pF C M O S o u t p u t Note: When P71–P77, P40 and bit 4 of the UART control register (address 001B16) is “1” (N-channel open- drain output mode). N-channel open-drain output (Note) 1 kΩ 100 pF M e a s u r e m e n t o u t p u t p i n

Rev.1.02 Jul 31, 2003 page 68 of 69 Fig. 66 Timing diagram I N N C N T R0, C N T 0.2VCC tW L I N T 0.8VCC tWH(INT) 0.2VCC 0.2VCC 0.8VCC 0.8VCC 0.2VCC tW L XI 0.8VCC tWH(XIN) tC(XIN) XI N 0.2VCC VC C tW(RESET) RESET tf tr V C C tWL(CNTR) V C C tWH(CNTR) tC(CNTR) td SC L K TXD td SC L K -SO U T tv(SCLK1-TXD), tv(SCLK2-SOUT2) tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) th(SCLK1-RXD), th(SCLK2-SIN2) tsu(RXD-SCLK1), tsu(SIN2-SCLK2) TXD SOUT2 RXD SIN2 SCLK1 SCLK2

Rev.1.02 Jul 31, 2003 page 69 of 69 LQFP100-P-1414-0.50 Weight(g) – 0.63 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100P6Q-A Plastic 100pin 14✕14mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E HE L y Dimension in Millimeters HD 0.225 – –I2 0.9 ––MD 14.4 ––ME 14.4 10°0° 0.1 1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e E HE 5026 HD D A F y 100 Lp 0.45 0.6 0.25 0.75 0.08x b x M A1 A2 L Detail F Lp c MD l2 b2 ME e Recommended Mount Pad MMP QFP100-P-1420-0.65 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 100P6S-A Plastic 100pin 14✕20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E HE L y Dimension in Millimeters HD 0.35 – –I2 1.3 ––MD 14.6 ––ME 20.6 10°0° 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8 3.05 e e e E c HE HD D MD ME A F A1 A2 L y Recommended Mount Pad Detail F 100 x– – 0.13 b x M MMP

REVISION HISTORY

Rev. Date Description Page Summary

7560 Group (A version) Data Sheet

1.00 Feb. 18, 2003 1.02 Jul. 31, 2003 First edition issued Power dissipation revised. Table 1 Pin description (1) V CC VSS; Function description revised. Fig.5 Memory expansion plan revised. Fig.14 Port block diagram (1); (4) Ports P1 6, P17,P2, P41, P42 and (5) Port P44 revised. Fig.15 Port block diagram (2); (7) Port P4 6 and (11) Port P54 revised. Fig.16 Port block diagram (3); (14) Port P5 5, (15) Ports P56, P57 and (17) Port P60 revised. Fig.17 Port block diagram (4); (19) Port P6 2 revised. Fig.40 A-D converter block diagram Voltage Multiplier (3 Times) Description of order for operating the voltage multiplier revised. ROM ORDERING METHOD revised. Table 16 Recommended operating conditions (4); f(CNTR 0) f(CNTR1) revised. Table 18 Electrical characteristics (2); I CC revised. Table 19 A-D converter characteristics (1); Note revised. Table 20 A-D converter characteristics (2); Note revised. Table 22 Timing requirements (1); tc(S CLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised. Table 23 Timing requirements (2); tc(S CLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised. Table 25 Switching characteristics (2) ; t r(SCLK1) tf(SCLK1) revised.

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