7555CBA

ICM7555_06 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 12

Technical content

Features

• Exact Equivalent in Most Cases for SE/NE555/556 or TLC555/556
• Low Supply Current
• Normal Reset Function - No Crowbarring of Supply During Output Transition
• Can be Used with Higher Impedance Timing Elements than Regular 555/6 for Longer RC Time Constants
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Output Source/Sink Driver can Drive TTL/CMOS
• Outputs have Very Low Offsets, HI and LO
• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Precision Timing
• Pulse Generation
• Sequential Timing
• Time Delay Generation
• Pulse Width Modulation
• Pulse Position Modulation
• Missing Pulse Detector Pinouts ICM7555 (8 LD PDIP, SOIC) TOP VIEW ICM7556 (14 LD PDIP, CERDIP) TOP VIEW GND TRIGGER OUTPUT RESET VDD DISCHARGE THRESHOLD CONTROL VOLTAGE DISCHARGE THRESH- CONTROL RESET OUTPUT TRIGGER GND VDD DISCHARGE THRESHOLD CONTROL RESET OUTPUT TRIGGER VOLTAGE VOLTAGE OLD Data Sheet August 24, 2006

2 FN2867.9 August 24, 2006

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # ICM7555CBA 7555 CBA 0 to +70 8 Ld SOIC M8.15 ICM7555CBA-T 7555 CBA 0 to +70 8 Ld SOIC Tape and Reel M8.15 ICM7555CBAZ (Note) 7555 CBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15 ICM7555CBAZ-T (Note) 7555 CBAZ 0 to +70 8 Ld SOIC (Pb-free) Tape and Reel M8.15 ICM7555IBA 7555 IBA -25 to +85 8 Ld SOIC M8.15 ICM7555IBAT 7555 IBA -25 to +85 8 Ld SOIC Tape and Reel M8.15 ICM7555IBAZ (Note) 7555 IBAZ -25 to +85 8 Ld SOIC (Pb-free) M8.15 ICM7555IBAZ-T (Note) 7555 IBAZ -25 to +85 8 Ld SOIC (Pb-free) Tape and Reel M8.15 ICM7555IPA 7555 IPA -25 to +85 8 Ld PDIP E8.3 ICM7555IPAZ (Note) 7555 IPAZ -25 to +85 8 Ld PDIP (Pb-free) E8.3 ICM7556IPD ICM7556IPD -25 to +85 14 Ld PDIP E14.3 ICM7556IPDZ (Note) ICM7556IPDZ -25 to +85 14 Ld PDIP (Pb-free) E14.3 ICM7556MJD ICM7556MJD -55 to +125 14 Ld Cerdip F14.3 **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ICM7555, ICM7556

3 FN2867.9 August 24, 2006 Absolute Maximum Ratings Thermal Information Input Voltage Trigger, Control Voltage, Threshold, Operating Conditions Temperature Range Thermal Resistance (Typical, Note 2) θ JA (°C/W) θJC (°C/W) (SOIC - Lead Tips Only) * Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +0.3V or less than V- -0.3V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply of the ICM7555 and ICM7556 must be turned on first. 2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details. PARAMETER SYMBOL TEST CONDITIONS TA = +25°C (NOTE 4) -55°C TO +125°C UNITSMIN TYP MAX MIN TYP MAX Static Supply Current I DD ICM7555 V DD = 5V 40 200 300 μA VDD = 15V 60 300 300 μA ICM7556 V DD = 5V 80 400 600 μA VDD = 15V 120 600 600 μA Monostable Timing Accuracy R A = 10K, C = 0.1μF, VDD = 5V 2 % 858 1161 μs Drift with Temperature (Note 3) VDD = 5V 150 ppm/ °C VDD = 10V 200 ppm/ °C VDD = 15V 250 ppm/ °C Drift with Supply (Note 3) VDD = 5V to 15V 0.5 0.5 %/V Astable Timing Accuracy R A = RB = 10K, C = 0.1μF, VDD = 5V 2 % 1717 2323 μs Drift with Temperature (Note 3) VDD = 5V 150 ppm/ °C VDD = 10V 200 ppm/ °C VDD = 15V 250 ppm/ °C Drift with Supply (Note 3) V DD = 5V to 15V 0.5 0.5 %/V Threshold Voltage V TH VDD = 1 5 V 6 26 77 16 1 7 2 % V DD Trigger Voltage V TRIG VDD = 1 5 V 2 83 23 62 7 3 7 % V DD Trigger Current I TRIG VDD = 15V 10 50 nA Threshold Current I TH VDD = 15V 10 50 nA Control Voltage V CV VDD = 1 5 V 6 26 77 16 1 7 2 % V DD ICM7555, ICM7556

4 FN2867.9 August 24, 2006 Functional Diagram Reset Voltage V RST VDD = 2V to 15V 0.4 1.0 0.2 1.2 V Reset Current I RST VDD = 15V 10 50 nA Discharge Leakage I DIS VDD = 15V 10 50 nA Output Voltage V OL VDD = 15V, ISINK = 20mA 0.4 1.0 1.25 V VDD = 5V, ISINK = 3.2mA 0.2 0.4 0.5 V VOH VDD = 15V, ISOURCE = 0.8mA 14.3 14.6 14.2 V VDD = 5V, ISOURCE = 0.8mA 4.0 4.3 3.8 V Discharge Output Voltage V DIS VDD = 5V, ISINK = 15mA 0.2 0.4 0.6 V VDD = 15V, ISINK = 15mA 0.4 V Supply Voltage (Note 3) V DD Functional Operation 2.0 18.0 3.0 16.0 V Output Rise Time (Note 3) t R RL = 10M, CL = 10pF, VDD = 5V 75 ns Output Fall Time (Note 3) t F RL = 10M, CL = 10pF, VDD = 5V 75 ns Oscillator Frequency (Note 3) fMAX VDD = 5V, RA = 470Ω, RB = 270Ω, C = 200pF 1M H z NOTES: 3. These parameters are based upon characterization data and are not tested. 4. Applies only to military temperature range product (M suffix). PARAMETER SYMBOL TEST CONDITIONS TA = +25°C (NOTE 4) -55°C TO +125°C UNITSMIN TYP MAX MIN TYP MAX THRESHOLD CONTROL VOLTAGE 5 3 TRIGGER COMPARATORR GND B COMPARATOR A R VDD OUTPUT n DISCHARGE OUTPUT DRIVERS FLIP-FLOP RESET4 R NOTE: This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs. TRUTH TABLE THRESHOLD VOLTAGE TRIGGER VOLTAGE RESET OUTPUT DISCHARGE SWITCH Don’t Care Don’t Care Low Low On >2/3(V+) > 1/3(V+) High Low On <2/3(V+) > 1/3(V+) High Stable Stable Don’t Care < 1/3(V+) High High Off NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD. ICM7555, ICM7556

9 FN2867.9 August 24, 2006 ICM7555, ICM7556 Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05

10 FN2867.9 August 24, 2006 ICM7555, ICM7556 Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A- 0.210 - 5.33 4 A1 0.015 - 0.39 -4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 -5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93

11 FN2867.9 August 24, 2006 ICM7555, ICM7556 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpen- dicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E14.3 (JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A- 0.210 - 5.33 4 A1 0.015 - 0.39 -4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 -5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 4 1 4 9 Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2867.9 August 24, 2006 ICM7555, ICM7556 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa CA - BM DS S eA F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)

14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D- 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 -7 α 90° 105° 90° 105° - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M- 0.0015 - 0.038 2, 3 N1 4 1 4 8 Rev. 0 4/94