7548

7548 RENESAS | Alldatasheet

Document overview

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Technical content

Rev.2.00 Mar 15, 2007 Page 1 of 70 REJ03B0210-0200 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

DESCRIPTION

The 7548 Group is the 8-bit microcomputer based on the 740 family core technology. The 7548 Group has an 8-bit timer, 16-bit timer, serial interface, A/D converter, power-on reset circuit and the low voltage detection circuit. Also, the Function set ROM is equipped.

FEATURES

(at 8 MHz oscillation frequency, double-speed mode)

• Memory size
• Programmable I/O ports (UART or clock synchronous) (connect to external ceramic resonator or quartz-crystal oscillator, 32 kHz quartz-crystal oscillation available)
• Power source voltage XIN oscillation frequency (at ceramic resonator, in double-speed mode) XIN oscillation frequency (at ceramic resonator, in high-speed mode) High-speed on-chip oscillator oscillation frequency Low-speed on-chip oscillator oscillation frequency APPLICATION Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, etc.

7548 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0210-0200 Rev.2.00 Mar 15, 2007

Rev.2.00 Mar 15, 2007 Page 2 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 1. Pin configuration (PLSP0020JB-A type) P13/AN3/KEY3/T2OUT P12/AN2/KEY2/CMP2 P11/AN1/KEY1/CMP1 P10/AN0/KEY0/CMP0 P07(LED7)/SRDY P06(LED6)/SCLK P05(LED5)/TxD P04(LED4)/RxD P03(LED3)/CAP0 P02(LED2) RESET P15/AN5/KEY5 P14/AN4/KEY4 P20/XOUT/XCOUT VSS VCC P21/XIN/XCIN CNVSS P00(LED0)/INT0 P01(LED1)/INT1 M37548G3/G2/G1FP PIN Configuration (top view)

Rev.2.00 Mar 15, 2007 Page 3 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 2. Pin configuration (42S1M type) CNVSS VCC NC NC NC M37549RLSS P30 P31 P13/AN3/KEY3/T2OUT P12/AN2/KEY2/CMP2 P11/AN1/KEY1/CMP1 P10/AN0/KEY0/CMP0 P07(LED7)/SRDY P06(LED6)/SCLK RESET P17/AN7/KEY7 P15/AN5/KEY5 P14/AN4/KEY4 P20/XOUT/XCOUT VSS P16/AN6/KEY6 P21/XIN/XCIN P00(LED0)/INT0 P01(LED1)/INT1 P05(LED5)/TxD P04(LED4)/RxD P03(LED3)/CAP0 P02(LED2) NC NC VSS NC NC NC NC NC NC NC NC NC NC NC NC PIN Configuration (top view) Package type: 42S1M

Rev.2.00 Mar 15, 2007 Page 4 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. PERFORMANCE OVERVIEW Table 1 Performance overview Parameter Function Number of basic instructions 71 Instruction execution time 0.25 µs (Minimum instruction, oscillation frequency 8 MHz, double-speed mode) Oscillation frequency 8 MHz (Maximum) Memory sizes ROM M37548G1 2K bytes × 8 bits M37548G2 4K bytes × 8 bits M37548G3 6K bytes × 8 bits RAM M37548G1 192 bytes × 8 bits M37548G2 256 bytes × 8 bits M37548G3 256 bytes × 8 bits I/O port P0 0-P07 I/O 1-bit × 8, LED direct drive ports P10-P15 I/O 1-bit × 6 P20 Output 1-bit × 1 P21 I/O 1-bit × 1 Interrupt Source 13 sources, 13 vectors Timer 8-bit × 2, 16-bit × 1 Output compare 3-channel Input capture 1 channel Serial interface 8-bit × 1 (UART or clock synchronous) A/D converter 10-bit resolution × 6 channel Watchdog timer 16-bit × 1 Power-on reset circuit Built-in Low voltage detection circuit Built-in Clock generating circuit Built-in (exter nal ceramic resonator or quartz-crystal oscillator, external 32-kHz quartz-crystal oscillator available) (built-in high/low-speed on-chip oscillator) Function set ROM area Function set ROM Function set RO M is assigned to address FFD8 16 to FFDA16. Valid/invaid of low voltage detection circuit can be selected. Oscillation mode can be selected. Enable/disable of watchdog timer and STP instruction can be selected. ROM code protect ROM code prot ect is assigned to address FFDB 16. Read/write the built-in QzROM by serial programmer is disabled by setting “00” to ROM code protect. Power source voltage (at ceramic resonator) Double- speed mode at 8 MHz oscillation 4.5 to 5.5 V at 2 MHz oscillation 2.4 to 5.5 V at 1 MHz oscillation 2.2 to 5.5 V High- speed mode at 8 MHz oscillation 4.0 to 5.5 V at 4 MHz oscillation 2.4 to 5.5 V at 1 MHz oscillation 1.8 to 5.5 V Power source voltage (at high-speed on- chip oscillator) Double- speed mode at 4 MHz oscillation 4.0 to 5.5 V Power source voltage (at low-speed on- chip oscillator) Double- speed mode at 250 kHz oscillation 1.8 to 5.5 V Power dissipation TBD Operating temperature range -20 to 85 °C Device structure CMOS sillicon gate 42-pin shrink ceramic PIGGY BACK (42S1M)

Rev.2.00 Mar 15, 2007 Page 5 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 3. FUNCTIONAL BLOCK DIAGRAM Timer 1(8) RESET 3 8 CNV SS Reset input P1(6) 22 0 1 811 9 1 7 P0(8) 16 15 14 13 12 11 10 9 R A M R O M A X Y S PCLPCH PS C P U VSS VCC XIN/XCIN XOUT /XCOUT Reset Timer A(16) Reset Reset P2(2) Capture (16)SIO (8)Compare (16) A/D converter (10) Clock generating circuit INT0 INT1 I/O port P2 Key-on wakeup I/O port P0 Clock input Clock output FUNCTIONAL BLOCK DIAGRAM (Package: PLSP0020JB-A) Watchdog timer Timer 2 (8) Prescaler 12 (8) Low voltage detection circuit Power-on reset circuit I/O port P1

Rev.2.00 Mar 15, 2007 Page 6 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. PIN DESCRIPTION NOTE: 1. The oscillation circuit is built in the P2 0/XOUT/XCOUT pin and the P21/XIN/XCIN pin. When the Vcc of the microcomputer is lower than the operation lower bound voltage even if these pins are used as I/O ports, the oscillation circuit is connected and undefined values may be output from these pins. Table 2 Pin description Pin Name Function Function expect a port function VCC,VSS Power source Apply voltage of 1.8 to 5.5 V to Vcc, and 0 V to Vss. CNVSS CNVSS Controls the operation mode of the chip. Connected to VSS. RESET Reset input Reset input pin for active “L” P00(LED0)/INT0 P01(LED1)/INT1 I/O port P0 •8-bit I/O port.

• I/O direction register allows each pin to be individu- ally programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Whether a built-in pull-up resistor is to be used or not can be determined by program.
• High drive capacity for LED drive port can be selected by program. Interrupt input pin 2(LED2) P03(LED3)/CAP0 Capture input pin P04(LED4)/RXD P05(LED5)/TXD P06(LED6)/SCLK P07(LED7)/SRDY Serial interface function pin P10/AN0/KEY0/CMP0 P11/AN1/KEY1/CMP1 P12/AN2/KEY2/CMP2 I/O port P1 •6-bit I/O port.
• I/O direction register allows each pin to be individu- ally programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Whether a built-in pull-up resistor is to be used or not can be determined by program. Input pins for A/D converter Key-input (key-on wake up interrupt input) pin Compare output pin 3/AN3/KEY3/T2OUT Timer 2 output pin P14/AN4/KEY4 P15/AN5/KEY5 P20/XOUT/XCOUT P21/XIN/XCIN (Note) I/O port P2 •2-bit I/O port. (P20/XOUT/XCOUT is only for output)
• I/O direction register allows each pin to be individu- ally programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Function set ROM allows pins to be used as clock pins. Pins X IN and XOUT, or pins XCIN and XCOUT, can be used as clock pins by connecting a ceramic resonator, crystal oscillator, or 32 kHz crystal oscillator between them. Alternately, an external clock may be input to the 0/XOUT/XCOUT pin. In this case, the P21/XIN/XCIN pin can be used as an I/O port.

Rev.2.00 Mar 15, 2007 Page 7 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. GROUP EXPANSION Renesas plans to expand the 7548 group as follow: Memory Type Support for QzROM version and emulator MCU. Memory Size Packages Fig 4. Memory expansion plan Currently supported products are listed below. NOTE: 1. ROM size includes the function set ROM. 192 256 M37548G1 M37548G3 RAM size (bytes) ROM size (bytes) **: Under development Note: Products under development ···the development schedule and specification may be revised without notice. M37548G2 Table 3 List of supported products Part number ROM size (bytes) ROM size for User () RAM size (bytes) Package Remarks M37548G3-XXXFP 6144 (6014) 256 PLSP0020JB-A QzROM version M37548G3FP QzROM version (blank) M37548G2-XXXFP 4096 (3966) 256 PLSP0020JB-A QzROM version M37548G2FP QzROM version (blank) M37548G1-XXXFP 2048 (1918) 192 PLSP0020JB-A QzROM version M37548G1FP QzROM version (blank) M37549RLSS − 256 42S1M Emulator MCU

Rev.2.00 Mar 15, 2007 Page 8 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 fa mily instruction set. Refer to the table of 740 family addres sing modes and machine-language instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL for details on each instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions cannot be used. 2. The MUL and DIV instructions can be used. 3. The WIT instruction can be used. 4. The STP instruction can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index register X (X), Index register Y (Y)] Both index register X and index re gister Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to “1”, the value contained in index register X becomes the address for the second OPERAND. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack a ddress are fixed. The operations of pushing register cont ents onto the stack and popping them from the stack are shown in Figure 6. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. Fig 5. 740 Family CPU register structure Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag b7 b0 b15 Program Counter Stack Pointer Index Register Y Index Register X AccumulatorA X Y S PC LPCH CZIDBTVN b7 b0 b7 b0 b7 b0 b7 b0 b7 b0

Rev.2.00 Mar 15, 2007 Page 9 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 6. Register push and pop at interrupt generation and subroutine call Interrupt request (Note) M(S)←(PCH) (S)←(S) − 1 M(S)←(PCL) (S)←(S) − 1 Execute RTS Subroutine (S)←(S) + 1 (PCL)←M(S) (S)←(S) + 1 (PCH)←M(S) M(S)←(PCH) (S)←(S) − 1 M(S)←(PCL) (S)←(S) − 1 M(S)←(PS) (S)←(S) − 1 Interrupt Service Routine (S)←(S) + 1 (PS)←M(S) (S)←(S) + 1 (PCL)←M(S) (S)←(S) + 1 (PCH)←M(S) Execute JSR Execute RTI Store Return Address on Stack Store Contents of Processor Status Register on Stack I Flag “0” to “1” Fetch the Jump Vector Restore Contents of Processor Status Register Restore Return Address Restore Return Address Store Return Address on Stack Note : The condition to enable the interrupt → Interrupt enable bit is “1” Interrupt disable flag is “0” On-going Routine Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack P op instruction from stack Accumulator PHA PLA Processor status register PHP PLP

Rev.2.00 Mar 15, 2007 Page 10 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. [Processor status register (PS)] The processor status register is an 8-bit register consisting of flags which indicate the status of th e processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Ov erflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V , N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. Bit 1: Zero flag (Z) The Z flag is set if the resu lt of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruct ion. Interrupts are disabled when the I flag is “1”. When an interrupt occurs, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is serviced. Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. The saved processor status is the only place where the break flag is ever set. Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory lo cations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations and direct data tr ansfers are enabled between memory locations, i.e. be tween memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation perf ormed on data in memory location 1 and memory locatio n 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to - 128. When the BIT instructio n is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. [CPU mode register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B 16. Fig 7. Structure of CPU mode register The processor mode bits can be written only once after releasing reset. Always set them to “00 2”. After written, rewriting any data to these bits is disabled because they are locked. (Emulator MCU is excluded.) Also, the stack page bit (bit 2) is not locked. In order to prevent error-writing to the processor mode bits (at program runaway), write the CPU mode register at the start of the program that runs after releasing reset. Table 5 Set and clear instructions of each bit of processor status register C flag Z flag I flag D flag B flag T flag V flag N flag Set instruction SEC − SEI SED − SET −− Clear instruction CLC − CLI CLD − CLT CLV −CPU mode register (CPUM: address 003B16, initial value: 0016) Processor mode bits b1b0 0 0 : Single-chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Disable (returns “0” when read) b7 b0

Rev.2.00 Mar 15, 2007 Page 11 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Memory

• Special Function Register (SFR) Area The SFR area in the zero page contains control registers such as I/O ports and timers.
• RAM RAM is used for data storage a nd for a stack area of subroutine calls and interrupts.
• R O M The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. The user area includes the function set ROM area.
• Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors.
• Zero Page The 256 bytes from addresses 0000 16 to 00FF 16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
• Special Page The 256 bytes from addresses FF00 16 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
• Function set ROM Area [Renesas shipment test area] Figure 8 shows the Assignment of Function set ROM area. The random data are set to the Renesas shipment test areas (addresses FFD4 16 to address FFD716). Do not rewrite the data of these areas. When the checksum is included in the user program, avoid assigning it to these areas. [Function set ROM data] FSROM0, FSROM1, FSROM2 Function set ROM data 0 to 2 (addresses FFD8 16 to FFDA16) are used to set modes of peripheral functions. By setting values to these ar eas, the operation mode of each peripheral function are set after releasing reset. Refer to the descriptions of peripheral functions for the details of operation of peripheral functions.
• Clock circuit
• Watchdog timer
• Low voltage detection circuit [ROM code protect] Address FFDB 16 of QzROM version is ROM code protect address and cannot be used for programming. “00 16” is written into this address when selecting the protect bit write by using a serial programmer and selecting protect enabled for writing shipment by Renesas Tech nology corp.. When “00 16” is set to the ROM code protect address, the protect function is enabled, so that reading or writing from/to the corresponding area is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer. As for the QzROM product shipped after writing, “00 16” (protect enabled) or “FF 16” (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing. The writing of “00 16” or “FF16” can be selected as ROM option setup (“MASK option” written in the mask file converter) when ordering. <Notes> (1) Because the contents of RAM are indefinite at reset, set initial values before using. (2) Do not access to the reserved area. (3) Random data is written into the Renesas shipment test area and the reserved ROM area. Do not rewrite the data in these areas. Data of these area ma y be changed without notice. Accordingly, do not include th ese areas into programs such as checksum of all ROM areas. (4) The QzROM values in function set ROM data 0 to 2 set the operating modes of the various peripheral functions after an MCU reset is released. Do not fail to set the value for the selected function. Bits designated with a fixed value of 1 or 0 must be set to the designated value.

Rev.2.00 Mar 15, 2007 Page 12 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 8. Memory map diagram RAM ROM 010016 000016 004016 044016 FF0016 XXXX16 FFFE16 FFFF16 YYYY16 ZZZZ16 192 00FF 16

2 F800 16 F88016

4 F000 16 F08016

Renesas shipment test area Renesas shipment test area Renesas shipment test area Renesas shipment test area Function set ROM data 0 ROM code protect RAM area RAM capacity (bytes) address XXXX16 ROM area ROM capacity (K bytes) address YYYY16 address ZZZZ16 Function set ROM SFR area Disable Interrupt vector area Zero page Special page Reserved ROM area Reserved ROM area (128 bytes) User ROM area Function set ROM area Reserved area

6 E800 16 E88016

Rev.2.00 Mar 15, 2007 Page 13 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 9. Memory map of special function register (SFR) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) (Note 1) Port P3 direction register (P3D) (Note 2) Reserved Reserved Reserved Reserved Port P0 drive capacity control register (DCCR) Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Key-on wakeup input selection register (KEYS) Capture/Compare register (low-order) (CRAL) Capture/Compare register (high-order) (CRAH) Capture/Compare register R/W pointer (CCRP) Compare output mode register (CMOM) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Reserved Reserved Transmit/Receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer mode register (TM) Timer count source set register (TCSS) Compare register re-load register (CMPR) Capture/Compare port register (CCPR) Capture/Compare status register (CCSR) Compare interrupt source set register (CISR) Capture software trigger register (CSTR) Capture mode register (CAPM) Reserved AD control register (ADCON) AD conversion register (low-order) (ADL) AD conversion register (high-order) (ADH) Clock mode register (CLKM) Oscillation stop detection register (CLKSTP) Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Notes 1: Port P3 pins are nothing. 2: Set “03 16” to the port P3 direction register, though the port P3 pins are nothing. 3: Do not access to the reserved addresses.

Rev.2.00 Mar 15, 2007 Page 14 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 10. Structure of Function set ROM data 0 Fig 11. Structure of Function set ROM data 1 Fig 12. Structure of Function set ROM data 2 Low voltage detection circuit valid bit 0: Low voltage detection circuit invalid 1: Low voltage detection circuit valid Set “0” to this bit certainly. Set “1” to this bit certainly. Function set ROM data 0 (FSROM0: address FFD816) Oscillation method selection bits (Note 1) b1 b0 0 0: Clock pins not used (P20/XOUT and P21/XIN are used as I/O ports) 0 1: Ceramic resonator or quarts-crystal oscillator 1 0: 32 kHz quarts-crystal oscillator 1 1: External clock input (P2 1/XIN pin is used as I/O port) Low voltage detection circuit valid bit in the stop mode (Note 2) 0: Low voltage detection circuit invalid in the stop mode 1: Low voltage detection circuit valid in the stop mode Set “0” to these bits certainly. Set “1” to this bit certainly. Function set ROM data 1 FSROM1 (FFD916) Notes 1: The P20/XOUT and P21/XIN pins build in an on-chip oscillator. Even if these pins are used as I/O ports, the oscillator circuit is enabled when the MCU’s Vcc voltage drops below the operation limit voltage. In this case these pins may output undefined values. 2: When the Low voltage detection circuit is set to be valid in the stop mode, the dissipation current in the stop mode is increased. Watchdog timer source clock selection bit 0 : Low-speed on-chip oscillator/16 1 : System clock/16 Watchdog timer start selection bit 0 : Start watchdog timer 1 : Stop watchdog timer Watchdog timer H count source initial value selection bit 0 : Initial value of bit 7 of WDTCON after reset release is “0” 1 : Initial value of bit 7 of WDTCON after reset release is “1” STP instruction function selection bit 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution Low-speed on-chip oscillator control bit (Note 1) 0 : Stop of low-speed on-chip oscillator disabled 1 : Stop of low-speed on-chip oscillator enabled Set “0” to these bits certainly. Function set ROM data 2 FSROM2 (FFDA16) Note 1: If “0” is set to this bit, it is not possible to write “1” to bit 0 in the clock mode register. Also, the low-speed on-chip oscillator does not stop even if the STP instruction is executed.

Rev.2.00 Mar 15, 2007 Page 15 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Ea ch bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When “1” is set to the bit corr esponding to a pin, this pin becomes an output port. When “0 ” is set to the bit, the pin becomes an input port. When data is read from a pin se t to output, not the value of the pin itself but the value of port latc h is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to , only the port latch is written to and the pin remains floating.

• If the port P20 is used as output port, write “1” to the port P20 direction register after reset.
• Set “1” to bits 6 and 7 of the port P1 direction register.
• Set “1” to bits 0 and 1 of the port P3 direction register. [Port P0 drive capacity control register] DCCR By setting the Port P0 drive ca pacity control re gister (address 000C16), the drive capacity of the N-channel output transistor for the port P0 can be selected. [Pull-up control registers] PULL0, PULL1 By setting the pull-up cont rol registers (address 000D 16 and 000E16), ports P0 and P1 can exert pull-up control by program. However, this is valid only when the port direct ion registers are set to input. When they are set to output, setting “pull-up on” does not pull up the ports. Fig 13. Structure of port P0 drive capacity control register Fig 14. Structure of port P0 pull-up control register Fig 15. Structure of port P1 control register Fig 16. Structure of port P3 direction register b7 b0 Port P00 drive capacity selection bit Port P01 drive capacity selection bit Port P02 drive capacity selection bit Port P03 drive capacity selection bit Port P04 drive capacity selection bit Port P05 drive capacity selection bit Port P06 drive capacity selection bit Port P07 drive capacity selection bit 0: weakness 1: strength Port P0 drive capacity control register (DCCR: address 000C16, initial value: 0016) b7 b0 P00 pull-up control bit P01 pull-up control bit P02 pull-up control bit P03 pull-up control bit P04 pull-up control bit P05 pull-up control bit P06 pull-up control bit P07 pull-up control bit 0: Pull-up is disabled 1: Pull-up is enabled Port P0 pull-up control register (PULL0: address 000D16, initial value: 0016) b7 b0 P10 pull-up control bit P11 pull-up control bit P12 pull-up control bit P13 pull-up control bit P14 pull-up control bit P15 pull-up control bit Set “0” to these bits certainly 0: Pull-up OFF 1: Pull-up ON Port P1 pull-up control register (PULL1: address 000E16, initial value: 0016) b7 b0 Set “1” to these bits certainly Not used (returns “0” when read) Port P3 direction register (P3D: address 000716, initial value: 0016) Note: Set “0316” to the port P3 direction register, though the port P3 pins are nothing.

Rev.2.00 Mar 15, 2007 Page 16 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Table 6 I/O port function table NOTE: 1. Function set ROM data 1 is included in the function set ROM area. Pin Name I/O format Non-port f unction SFRs related each pin P00(LED0)/INT0 P01(LED1)/INT1 I/O port P0 CMOS compatible input level CMOS 3-state output External interrupt input Interrupt edge selection register Port P0 drive capacity control register Port P0 pull-up control register P02(LED2) Port P0 drive capacity control register Port P0 pull-up control register P03(LED3)/CAP0 Capture input Capture/Compare port register Port P0 drive capacity control register Port P0 pull-up control register P04(LED4)/RXD Serial interface input/ output Serial I/O control register Port P0 drive capacity control register Port P0 pull-up control register P05(LED5)/TXD Serial I/O control register UART control register Port P0 drive capacity control register Port P0 pull-up control register 6(LED6)/SCLK Serial I/O control register Port P0 drive capacity control register Port P0 pull-up control register 7(LED7)/SRDY Serial I/O control register Port P0 drive capacity control register Port P0 pull-up control register P10/AN0/KEY0/CMP0 P11/AN1/KEY1/ CMP1P12/AN2/KEY2/ CMP2 I/O port P1 Compare output Key input interrupt A/D conversion input Capture/Compare port register Port P1 pull-up control register Key-on wakeup input selection register AD control register 3/AN3/KEY3/T2OUT Timer 2 output Key input interrupt A/D conversion input Timer mode register Port P1 pull-up control register Key-on wakeup input selection register AD control register 4/AN4/KEY4 P15/AN5/KEY5 Key input interrupt A/D conversion input Port P1 pull-up control register Key-on wakeup input selection register AD control register 0/XOUT/XCOUT I/O port P2 CMOS 3-state output Clock pin Function set ROM data 1 (Note) Clock mode register P21/XIN/XCIN CMOS compatible input level CMOS 3-state output Clock pin Function set ROM data 1 (Note) Clock mode register

Rev.2.00 Mar 15, 2007 Page 17 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 17. Block diagram of pins (1) INT0 input Data bus Port latch Pull-up control bit (1) Port P00 Drive capacity control bit Data bus INT1 input (2) Port P01 (3) Port P02 (4) Port P03 CAP0 input (5) Port P04 Serial I/O input Receive enable bit Serial I/O enable bit (6) Port P05 Transmit enable bit P05/TXD P-channel output disable bit (7) Port P06 Serial I/O mode selection bit Serial I/O enable bit Serial I/O synchronous clock selection bit Serial I/O clock output (8) Port P07 SRDY output enable bit Serial I/O ready output represents a parasitic diode. No current flow is possible. Ensure that the input voltage to each pin does not exceed the absolute maximum rating. Note: Port latch Direction register Direction register Pull-up control bit Drive capacity control bit Pull-up control bit Direction register Data bus Port latch Drive capacity control bit Pull-up control bit Data bus Direction register Port latch Drive capacity control bit Pull-up control bit Direction register Port latchData bus Drive capacity control bit Data bus Pull-up control bit Direction register Port latch Drive capacity control bit Pull-up control bit Direction register Port latchData bus Drive capacity control bit Pull-up control bit Direction register Port latchData bus Drive capacity control bit Serial I/O output Serial I/O enable bit Serial I/O enable bit Serial I/O clock input Serial I/O mode selection bit Serial I/O enable bit

Rev.2.00 Mar 15, 2007 Page 18 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 18. Block diagram of pins (2) Compare output port selection bit Compare output Port latch (10) Port P13 Timer2 output P13/T2OUT output valid bit A/D converter input Key-on wakeup input selection bit Analog input pin selection bit Key input interrupt (11) Ports P14, P15 (Note) (12) Ports P20, P21 Pull-up control at STP P20/XOUT/XCOUT Oscillation mode selection bit (function set ROM data 1) P21/XIN/XCIN Note: Set to “1” the port P20 direction register. Clock input (13) CNVss Mode setting signal input QzROM programming power supply Reset signal input (14) RESET (9) Ports P10, P11, P12 Data bus Pull-up control bit Direction register Pull-up control bit Direction register Port latchData bus Data bus Pull-up control bit Direction register Port latch Direction register Port latchData bus Key-on wakeup input selection bit Analog input pin selection bit Key-on wakeup input selection bit Analog input pin selection bit A/D converter input Key input interrupt A/D converter input Key input interrupt Direction register Port latchData bus represents a parasitic diode. No current flow is possible. Ensure that the input voltage to each pin does not exceed the absolute maximum rating. Note:

Rev.2.00 Mar 15, 2007 Page 19 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Termination of unused pins

• Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. Output ports: Open. Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). We recommend processing unused pins through a resistor which can secure IOH (avg) or IOL (avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc. Table 7 Termination of unused pins Pin Termination 0/INT0 Perform termination of I/O port. P01/INT1 P02 P03 P04/RXD P05/TXD P06/SCLK P07/SRDY P10/AN0/KEY0/CMP0 P11/AN1/KEY1/CMP1 P12/AN2/KEY2/CMP2 P13/AN3/KEY3/T2OUT P14/AN4/KEY4 P15/AN5/KEY5 P20/XOUT/XCOUT Set the direction register to “1”, and perform termination of output port. P21/XIN/XCIN Perform termination of I/O port.

Rev.2.00 Mar 15, 2007 Page 20 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Interrupts Interrupts occur by 13 different sources : 5 external sources, 7 internal sources and 1 software source.

• Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt di sable flag. When the interrupt enable bit and the interrupt reque st bit are set to “1” and the interrupt disable flag is set to “0”, an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority.
• Interrupt operation Upon acceptance of an interrup t the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the progra m counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding inter- rupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destina- tion address is read from the vector table into the program counter. [Interrupt edge selection register] INTEDGE The valid edge of external interrupt INT 0 and INT 1 can be selected by the interrupt edge selection bit, respectively. [Key-on wakeup input selection register] KEYS Either of enable or disable of key-on wakeup for pins P1 0 to P15 can be selected by the key- on wakeup input selection bit, respectively. Fig 19. Structure of key-on wakeup input selection register
• Notes on use (1) When setting the followings, the interrupt request bit may be set to “1”.
• When switching external interrupt active edge related register: Interrupt edge selection register (address 003A 16) Capture mode register (address 003216) When not requiring th e interrupt occurren ce synchronized with these setting, take the following sequence. 1. Set the corresponding interrupt enable bit to “0” (disabled). 2. Set the interrupt edge select bit (active edge switch bit, trig- ger mode bit). 3. Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. 4. Set the corresponding interrupt enable bit to “1” (enabled). b7 b0 Key-on wakeup input selection register KEYS (000F16), initial value: 0016 Port P10 key-on wakeup input selection bit Port P11 key-on wakeup input selection bit Port P12 key-on wakeup input selection bit Port P13 key-on wakeup input selection bit Port P14 key-on wakeup input selection bit Port P15 key-on wakeup input selection bit Set “0” to these bits certainly 0: Disable 1: Enable

Rev.2.00 Mar 15, 2007 Page 21 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Table 8 Interrupt vector address and priority NOTES: 1. Vector addressed contain inter nal jump destination addresses. 2. Reset function in the same way as an interrupt with the highest priority. Interrupt source Priority Vector addresses (Note 1) Interrupt request generating conditions RemarksHigh- order Low- order Reset (Note 2) 1 FFFD 16 FFFC16 At reset input Non-maskable Serial I/O receive 2 FFFB 16 FFFA16 At completion of serial I/O data receive V alid only when serial I/O is selected Serial I/O transmit 3 FFF9 16 FFF816 At completion of serial I/O transmit shift or when transmit buffer is empty Valid only when serial I/O is selected INT0 4F F F 7 16 FFF616 At detection of either rising or falling edge of INT0 input External interrupt (active edge selectable) INT1 5F F F 5 16 FFF416 At detection of either rising or falling edge of INT1 input External interrupt (active edge selectable) Key-on wakeup 6 FFF3 16 FFF216 At falling of conjunction of input logical level for port P1 (at input) External interrupt (valid at falling edge) Capture 7 FFF1 16 FFF016 At detection of either rising or falling edge of Capture 0 input External interrupt (active edge selectable) Compare 8 FFEF 16 FFEE16 At compare matched Compare in terrupt source is selected. Timer A 9 FFED 16 FFEC16 At timer A underflow Timer 21 0 F F E B 16 FFEA16 At timer 2 underflow A/D conversion 11 FFE9 16 FFE816 At completion of A/D conversion Timer 11 2 F F E 7 16 FFE616 At timer 1 underflow STP release timer underflow Not used 13 FFE5 16 FFE416

14 FFE3 16 FFE216

15 FFE1 16 FFE016

16 FFDF 16 FFDE16

BRK instruction 17 FFDD 16 FFDC16 At BRK instruction execution Non-maskable software interrupt

Rev.2.00 Mar 15, 2007 Page 22 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 20. Interrupt control Fig 21. Structure of Interrupt-related registers Interrupt disable flag I Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset b7 b0 INT0 interrupt edge selection bit 0: Falling edge active 1: Rising edge active INT 1 interrupt edge selection bit 0: Falling edge active 1: Rising edge active Not used (returns “0” when read) Interrupt edge selection register (INTEDGE: address 003A16, initial value: 0016) b7 b0 Interrupt request register 1 (IREQ1: address 003C16, initial value: 0016) Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up interrupt request bit Capture interrupt request bit Compare interrupt request bit Timer A interrupt request bit 0: No interrupt request issued 1: Interrupt request issued b7 b0 b7 b0 b7 b0 Interrupt request register 2 (IREQ2: address 003D16, initial value: 0016) Timer 2 interrupt request bit A/D conversion interrupt request bit Timer 1 interrupt request bit Not used (returns “0” when read) (Do not write “1” to this bit) 0: No interrupt request issued 1: Interrupt request issued Interrupt control register 1 (ICON1: address 003E16, initial value: 0016) Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit Capture interrupt enable bit Compare interrupt enable bit Timer A interrupt enable bit 0: Interrupts disabled 1: Interrupts enabled Interrupt control register 2 (ICON2: address 003F16, initial value: 0016) Timer 2 interrupt enable bit A/D conversion interrupt enable bit Timer 1 interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0: Interrupts disabled 1: Interrupts enabled

Rev.2.00 Mar 15, 2007 Page 23 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Key Input Interrupt (Key-On Wakeup) A key-on wakeup interrupt request is generated by applying “L” level to any pin of port P1 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 22, where an in terrupt request is generated by pressing one of the keys provid ed as an active-low key matrix which uses ports P10 to P13 as input ports. Fig 22. Connection example when using key input interrupt and port P1 block diagram Port PXx level output Key input interrupt request * P-channel transistor for pull-up CMOS output buffer bit 5 = Port P15 latch Port P15 Direction register = * P15 output bit 4 = Port P14 latch Port P14 Direction register = * P14 output bit 3 = Port P13 latch Port P13 Direction register = * P13 input bit 2 = Port P12 latch Port P12 Direction register = * P12 input bit 1 = Port P11 latch Port P11 Direction register = * P11 input bit 0 = Port P10 latch Port P10 Direction register = *** P10 input Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Port P10 key-on wakeup selection bit “L” “0” “0” “1” “1” “1” “1” “1” “1” “0” “0” “0” “0” Port P1 Input read circuit Port P1 pull-up control register Port P1 pull-up control register Port P1 pull-up control register Port P1 pull-up control register Port P1 pull-up control register Port P14 key-on wakeup selection bit Port P13 key-on wakeup selection bit Port P12 key-on wakeup selection bit Port P1 pull-up control register Port P11 key-on wakeup selection bit Port P15 key-on wakeup selection bit

Rev.2.00 Mar 15, 2007 Page 24 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Timers The 7548 Group has two 8-bit time rs (timer 1 and timer 2) and one 16-bit timer (timer A). Timer 1 and timer 2 share the same 8-bit prescaler (prescaler 12). Each timer and prescaler has a separate timer latch and prescaler latch. The division ratio of every timer and prescaler is 1/(n+1), where n is the value of the timer latch or prescaler latch. The timers decrement at each count clock input. When the count value reaches “0”, an underflow occurs at the next count pulse. The value of the corresponding timer latch is reloaded into the timer at underflow and counti ng is continued. When a timer underflow occurs, the interrupt request bit corresponding to each timer is set to “1”.

• Prescaler 12 (PRE12) Prescaler 12 is an 8-bit prescaler that counts the signal selected by the prescaler 12 count source selection bit. The count source can be selected from φSOURCE/16 and X CIN input clock. Writing to prescaler 12 writes the value to both the prescaler latch and prescaler. Reading from prescaler 12 read s the prescaler 12 count value. The initial value is set to “FF 16” after reset. The division ratio of prescaler 12 is 1/(n+1), where n is the setting value. Prescaler 12 cannot stop counting by software.
• Timer 1 (T1) Timer 1 is an 8-bit timer that counts the prescaler 12 output. When Timer 1 underflows, the timer 1 interrupt request bit is set to “1”. Writing to timer 1 writes the value to both the timer 1 latch and timer 1. Reading from timer 1 reads the timer 1 count value. The initial value is set to “01 16” after reset. The division ratio of timer 1 is 1/(m+1), where m is the setting value. This gives that the division ratio of prescaler 12 and timer 1 is 1/((n+1) × (m+1)), where n is the prescaler 12 setting value and m is the timer 1 setting value. Timer 1 cannot stop counting by software.
• Timer 2 (T2) Timer 2 is an 8-bit timer that counts the signal selected by the timer 2 count source selection bit. The count source can be selected from among φSOURCE/16, /256, prescaler 12 output, and timer A output signal. Timer 2 counts the selected co unt source and sets the timer 2 interrupt request bit to “1” at underflow. When writing to timer 2, the value of the timer 2 write control bit can be used to select a write to both the timer 2 latch and timer 2 or a write to only the timer 2 latch. Reading from timer 2 reads the timer 2 count value. Timer 2 starts counting from “FF 16” after reset. The division ratio of timer 2 is 1/(n+1), where n is the timer 2 setting value. Timer 2 stops when the timer 2 count stop bit is set to “1”. When the P1 3/T2OUT output valid bit is set to “1”, the polarity of the waveform output from the P1 3/T2OUT pin can be inverted at each timer 2 underflow. The out put start level of the T2 OUT pin can be selected using the T2 OUT polarity switch bit. When this bit is set to 0, the output starts at “H” level. When this bit is set to “1”, the output starts at “L” level.
• Notes on Timers 1 and 2 (1) Reading from and Writing to Timer 1 and 2 and Prescaler 12 If the timer/prescaler count source clock and φSOURCE are different clocks, the timers and prescaler cannot be read or written. Select the same clock to enable read and write operations. Note that timer 2 can be read and written even using a different clock while its counting is stopped.

1 Prescaler 12 and timer 1 cannot be read/written in the

following conditions: Prescaler 12 count source: X CIN input clock φSOURCE: Clock other than XCIN input clock

2 Timer 2 cannot be read/written during counting in the

following conditions: Timer 2 count source: Prescaler 12 Prescaler 12 count source: X CIN input clock φSOURCE: Clock other than XCIN input clock or Timer 2 count source: Timer A underflow Timer A count source: XCIN input clock φSOURCE: Clock other than XCIN input clock or Timer 2 count source: Timer A underflow Timer A count source: low-speed on-chip oscillator output φSOURCE: Clock other than low-speed on-chip oscillator (2) Count Source of Prescaler 12 The X CIN input clock can be selected as the prescaler count source only if the 32 kHz quartz crystal oscillator is selected by the oscillation method selection bit in FSROM1.

Rev.2.00 Mar 15, 2007 Page 25 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 23. Structure of timer mode register Fig 24. Structure of timer count source set register Fig 25. Block diagram of timer 1 and timer 2 b7 b0 Timer mode register (TM: address 002B16, initial value: 0016) Not used (return “0” when read) Timer 2 count stop bit 0: Count start 1: Count stop 3/T2OUT output valid bit 0: Pulse output invalid (I/O port) 1: Pulse output valid OUT polarity selection bit 0: Start from “H” level 1: Start from “L” level Timer 2 write control bit 0: Write to latch and timer simultaneously 1: Write to only latch Timer A write control bit 0: Write to latch and timer simultaneously 1: Write to only latch Timer A count stop bit 0: Count start 1: Count stop Not used (return “0” when read) b7 b0 Timer count source set register (TCSS: address 002C16, initial value: 0016) Timer 2 count source selection bit b1 b0 0 0 : φSOURCE/16 0 1 : φSOURCE/256 1 0 : Prescaler 12 output 1 1 : Timer A underflow signal Timer A count source selection bit (Note 1) b4 b3 b2 0 0 0 : φSOURCE/16 0 0 1 : φSOURCE/2 0 1 0 : φSOURCE/32 0 1 1 : φSOURCE/64 1 0 0 : φSOURCE/128 1 0 1 : φSOURCE/256 1 1 0 : Low-speed on-chip oscillator output 1 1 1 : X CIN input clock (32 kHz quartz crystal oscillation) Prescaler 12 count source selection bit 0 : φSOURCE/16 1 : XCIN input clock (32 kHz quartz crystal oscillation) Not used (return “0” when read) Note 1: φSOURCE is the clock selected by bits 5 and 4 in the clock mode register (003716). The timer count sources are not affected by bits 7 and 6, the CPU clock dividing ratio select bits. Data bus Timer 1 interrupt request φSOURCE/16 XCIN input clock (32 kHz quartz crystal oscillation) Data bus Prescaler 12 latch (8) Timer 1 latch (8) Prescaler 12 (8) Timer 1 (8) φSOURCE/256 φSOURCE/16 Timer 2 count stop bit Timer 2 count source selection bit Prescaler 12 count source selection bit Timer 2 interrupt request Timer 2 latch (8) Timer 2 (8)Timer A underflow Timer 2 write control bit Toggle flip-flop T Q Q P13/T2OUT output valid bit RT2OUT polarity selection bit “1” “0” P13/T2OUT output valid bit Port P13 latch Port P13 direction register P13/T2OUT

Rev.2.00 Mar 15, 2007 Page 26 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Timer A (TA) Timer A is a 16-bit timer and c ounts the signal selected by the timer A count source selection bit. The count source of Timer A can be selected from among φSOURCE/2, /16, /32, /64, /128, /256, low-speed on-ship oscillator clock, and X CIN input clock. Timer A counts the selected count source and sets the timer A interrupt request bit to “1”. When writing to timer A, the se tting value of the timer A write control bit can be used to select a write to both the timer A latch and timer or a write to only the timer A latch. Reading from timer A reads the timer A count value. Be sure to write to and read from the low-order and the higher order of timer A in the following order:

• R e a d Read the high-order of Timer A (TAH) first, and the low- order of Timer A (TAL) next. Always read both of the registers.
• Write Write to the low-order of Timer A (TAL) first and the high-order of Timer A next. Always read both of the registers. Counting starts from “FFFF 16” after reset. The division ratio of timer A is 1/(n+1), where n is the timer A setting value. Timer A stops when the timer A count stop bit is set to “1”. Timer A can be used as the t iming timer for in put capture and output compare functions.
• N o t e s o n T i m e r A (1) Timer Value Setting When the timer A write control bit is set to “write to only latch”, written data is written to only to the latch even when the timer is stopped. To set the initial setting value when the timer is stopped, select “Write to timer and latch simultaneously” beforehand. (2) Reading from and Writing to Timer A If the timer A count source clock and φSOURCE are different clocks, timer A cannot be read or written during its counting. Select the same clock or set timer A to stop counting to enable read and write operations.
• Timer A cannot be read/written in the following conditions: Timer A count source: X CIN input clock φSOURCE: Clock other than XCIN input clock or Timer A count source: Low-speed on-chip oscillator output φSOURCE: Clock other than low-speed on-chip oscillator (3) Count Source of Timer A The X CIN input clock can be selected as the count source of timer A only if the 32 kHz quartz crysta l oscillator is selected by the oscillation method selection bit in FSROM1. Fig 26. Block diagram of timer A Data bus Low-speed on-chip oscillator output φSOURCE/256 φSOURCE/128 φSOURCE/64 φSOURCE/32 φSOURCE/16 φSOURCE/2 Timer A (low-order) latch (8) XCIN input clock (32 kHz quart crystal oscillator) Timer A (high-order) latch (8) Timer A (low-order) (8) Timer A (high-order) (8) Timer A write control bit Timer A interrupt request Compare Capture Timer A count stop bit Timer A count source selection bits

Rev.2.00 Mar 15, 2007 Page 27 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Output compare 7548 group has 3-output compare channels. Each channel (0 to 2) has the same function and can be used to output waveform by using count value of Timer A. Three output compare channels share the registers with the input capture (one channel), but their individual circuits operate independently so that all the ch annels can be used at the same time. To use each compare channel, set “1” to the compare x (x = 0, 1, 2, 3) output port bit and se t the port direction register corresponding to compare channel to output mode. The compare value for each channel is set to the capture/compare register (low-order) and capture/compare register (high-order). Writing to the register for each channel is controlled by setting value of capture/compare register RW pointer. Writing to each register is in the following order; 1. Set the corresponding compare latch to the capture/compare register RW pointer. 2. Write a value to the capture/compare register (low-order) and capture/compare register (high-order). (It doesn’t care even if either low-order or high-order is written early.) 3. Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21) re-load bit. When “1” is set to the compare latch y re-load bit, the value set to the compare register is loaded to compare latch when the next timer underflow. After loading, re-load bit is set to “0” automatically. When the count value of timer A matches the compare latch setting value, a trigger to the compare output circuit is generated. The trigger can be enabled or disabled using the compare x trigger enable bit. When the compare x trigger enable bit is set to 1, the output waveform from the port is as follows.

• When the value of the compare x output level latch is “0” High level at compare latch x0 match Low level at compare latch x1 match
• When the value of the compare x output level latch is “1” Low level at compare latch x0 match High level at compare latch x1 match The output waveform does not ch ange if the compare x trigger enable bit is set to 0, so the port output remains fixed at high or low level. The compare output level of each channel can be confirmed by reading the compare x output status bit. Compare interrupt is available when match of each compare channel and timer count value. Th e interrupt request from each channel can be disabl ed or enabled by setting value of compare latch y interrupt source selection bit.
• Notes on Output Compare (1) If timer A is stopped, when a value is written to the capture/ compare register it is immediately transferred to the compare latch. In addition, if timer A is stopped and the compare x trigger enable bit is set to “1”, the output latch is initialized. (2) Do not write the same data to both of compare latch x0 and x1. (3) When setting value of the compare latch is larger than timer setting value, compare matc h signal is not generated. Accordingly, the output waveform is fixed to “L” or “H” level. However, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. Accordingly, compare interrupt occurs. (4) When the compare x trigger enable bit is cleared to “0” (disabled), the match trigger to the waveform output circuit is disabled, and the output wave form can be fixed to “L” or “H” level. However, in this case, the compare match signal is generated. Accordingly, compare interrupt occurs. Fig 27. Structure of capture/compare register Fig 28. Structure of capture/compare register RW pointer Fig 29. Structure of compare register re-load register Fig 30. Structure of capture/compare port register b7 b0 Capture/Compare register (low-order) (CRAL: address 001016, initial value: 0016) b7 b0 Capture/Compare register (high-order) (CRAH: address 001116, initial value: 0016) b7 b0 Capture/Compare register RW pointer (CCRP: address 001216, initial value: 0016) Capture/Compare register RW pointer b2 b1 b0 0 0 0 : Compare latch 00 0 0 1 : Compare latch 01 0 1 0 : Compare latch 10 0 1 1 : Compare latch 11 1 0 0 : Compare latch 20 1 0 1 : Compare latch 21 1 1 0 : Capture latch 00 1 1 1 : Capture latch 01 Not used (returns “0” when read) b7 b0 Compare register re-load register (CMPR: address 002D16, initial value: 0016) Compare latch 00, 01 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 10, 11 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 20, 21 re-load bit 0: Re-load disabled 1: Re-load at next underflow Not used (returns “0” when read) b7 b0 Capture/Compare port register (CCPR: address 002E16, initial value: 0016) Capture input port bits 0: Capture from P03 1: Low-speed on-chip oscillator/16 Compare 0 output port bit 0: P10 is I/O port 1: P10 is Compare 0 output Compare 1 output port bit 0: P11 is I/O port 1: P11 is Compare 1 output Compare 2 output port bit 0: P12 is I/O port 1: P12 is Compare 2 output Not used (returns “0” when read)

Rev.2.00 Mar 15, 2007 Page 28 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 31. Structure of compare output mode register Fig 32. Structure of capture/compare status register Fig 33. Structure of compare interrupt source register b7 b0 Compare output mode register (CMOM: address 001316, initial value: 0016) Compare 0 output level latch 0: Positive 1: Negative Compare 1 output level latch 0: Positive 1: Negative Compare 2 output level latch 0: Positive 1: Negative Compare 0 trigger enable bit 0: Disabled 1: Enabled Compare 1 trigger enable bit 0: Disabled 1: Enabled Compare 2 trigger enable bit 0: Disabled 1: Enabled Not used (returns “0” when read) b7 b0 Capture/Compare status register (CCSR: address 002F16, initial value: 0016) Compare 0 output status bit 0: “L” level output 1: “H” level output Compare 1 output status bit 0: “L” level output 1: “H” level output Compare 2 output status bit 0: “L” level output 1: “H” level output Capture 0 status bit 0: latch 00 captured 1: latch 01 captured Not used (returns “0” when read) b7 b0 Compare interrupt source register (CISR: address 003016, initial value: 0016) Compare latch 00 interrupt source bit Compare latch 01 interrupt source bit Compare latch 10 interrupt source bit Compare latch 11 interrupt source bit Compare latch 20 interrupt source bit Compare latch 21 interrupt source bit Not used (returns “0” when read) 0: Disabled 1: Enabled

Rev.2.00 Mar 15, 2007 Page 29 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 34. Block diagram of compare output circuit Fig 35. Block diagram of compare channel 0 Timer A latch Timer A counter Compare channel 0 Compare latch 00 Compare latch 01 Output waveform latch 0P10/CMP0 Compare channel 1 Compare channel 2 P11/CMP1 P12/CMP2 Data bus Compare buffer 00 (16) Compare latch 00 (16) Compare buffer 01 (16) Compare latch 01 (16) Compare register Capture/Compare register R/W pointer (001216, bits 0 to 2) Compare latch 00, 01 reload bit (002D16, bit 0) Timer A counter (16) Output waveform latch 0 Compare 0 trigger enable bit (001316, bit 3) Compare 0 output level latch (001316, bit 0) Compare 0 output status bit (002F16, bit 0) P10/CMP0 Compare latch 00 interrupt source selection bit (003016, bit 0) Compare latch 01 interrupt source selection bit (003016, bit 1) Compare interrupt Compare 0 output port selection bit (001E16, bit 2) I/O port

Rev.2.00 Mar 15, 2007 Page 30 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 36. Output compare mode (general waveform) Fig 37. Output compare mode (compare register write timing) Timer A count clock Timer A underflow Timer A count value Compare interrupt Compare latch 01 000B000C000D000E000F0000000100020003000400050006000700080009000A000B000C 010 000B 0005 Re-load the count value Compare latch 00 Compare 00 match Compare 01 match Compare output Compare status bit Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register. Timer A count clock Timer A underflow Timer A count value Compare latch 00, 01 re-load signal Compare latch 01 000B000C000D000E000F0000000100020003000400050006000700080009000A000B000C 010 000B 0005 Compare latch 00 Compare latch 00 write Compare latch 01 write Compare latch 00, 01 re-load bit Compare status bit 000C 000E Compare 00 match Compare 01 match Compare output Compare interrupt Re-load the count value

Rev.2.00 Mar 15, 2007 Page 31 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Input capture 7548 group has 1-input capture channel and can be used to capture count value of Timer A. Input capture shares the regist ers with three output capture channels, but their individual circuits operate independently so that all the channels can be used at the same time. To use input capture, set the input capture port selection bits. If P03 is selected, set the P03 direction register to 0. When an input capture trigger is input to the input capture circuit, the count value of timer A is saved to the capture latches. The timer count value at the rising edge of the external input trigger is saved to capture latch 00, and the timer count value at the falling edge of the external input trigger is saved to capture latch 01. Capture latch 00 and capture latch 01 can be read using the following procedure. 1. Set the capture/compare register R/W pointer to the read target address. 2. Read the high-order bits of the capture/compare registers, then read the low-order bits of the capture/compare regis- ters. (Read both the capture/compare registers in the sequence of high-order bits followed by low-order bits.) The count value of timer can be retained by software by capture y (y = 00, 01, 10, 11) software trigger bit too. When “1” is set to this bit, count value of timer is retained to the corresponded capture latch. When reading from the capture y software trigger bit is executed, “0” is read out.

• Notes on Input Capture
• When the low-speed on-chip oscillator output or X CIN input clock is selected as the coun t source of timer A, input capture can be used only if the same clock source is selected as φSOURCE and as the count source of timer A.
• When writing “1” to capture y so ftware trigger bit of capture latch 00 and 01 at the same time, or external trigger and software trigger occur simultan eously, if capture latches 00 and 01 are input simultaneously, the set value of capture 0 status bit is undefined.
• When setting the interrupt active edge selection bit and noise filter clock selection bit of cap ture 0 the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. (1) Set the capture interrupt enable bit to “0” (disabled). (2) Set the interrupt edge selection bit or noise filter clock selection bit. (3) Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. (4) Set the capture interrupt enable bit to “1” (enabled).
• When the capture interrupt is us ed as the interrupt for return from stop mode, set the capture 0 noise filter clock selection bits to “00 (Filter stop)”. Fig 38. Structure of capture software trigger register Fig 39. Structure of capture mode register b7 b0 Capture software trigger register (CSTR: address 003116, initial value: 0016) Capture latch 00 software trigger bit Capture 00 software trigger occurs by setting “1” to this bit. (returns “0” when read) Capture latch 01 software trigger bit Capture 01 software trigger occurs by setting “1” to this bit. (returns “0” when read) Not used (returns “0” when read) b7 b0 Capture 0 interrupt edge selection bits b1 b0 0 0 : Rising and falling edge 0 1 : Rising edge 1 0 : Falling edge 1 1 : Not available Capture 0 noise filter clock selection bits b1 b0 0 0 : Filter stop 0 1 : f (X IN) 1 0 : f (XIN)/8 1 1 : f (XIN)/32 Not used (returns “0” when read) Capture mode register (CAPM: address 003216, initial value: 0016)

Rev.2.00 Mar 15, 2007 Page 32 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 40. Block diagram of capture channel 0 Fig 41. Capture input waveform (capture interrupt edge selection bit = “rising edge”) Fig 42. Capture input waveform (capture interrupt edge selection bit = “rising and falling edge”) Data bus Capture registerCapture/Compare register RW pointer (001216, bits 0-2) Capture latch 0 (16)Capture trigger Capture pointer Capture latch 0x software trigger bits (003116, bits 0, 1) P03/ CAP0 Capture latch 00 (16) Capture latch 01 (16) Rising Falling Capture 0 interrupt edge selection bits (003216, bits 0, 1) Capture Interrupt Timer A counter (16) Digital filter Capture 0 status bit (002F16, bit 3) Low-speed on-chip oscillator/16 Capture 0 noise filter clock selection bits (003216, bits 2, 3) Capture 0 input port selection bit (002E16, bit 0) Timer A underflow Capture input wave Timer A count value Capture latch 00 000B000C000D000E000F000000020003000400050006000700080009000B000C XXXX Re-load the timer A count value Capture latch 01 Capture 0 interrupt Capture 0 status bit XXXX 101 000A 0001 000C 0005 000F 01 0 Overwrite 0001000A Timer A underflow 000B000C000D000E000F0000000100020003000400050006000700080009000A000B000C XXXX XXXX 101 000A 0001 000C 0005 000F 01 0 Capture input wave Timer A count value Capture latch 00 Capture latch 01 Capture 0 interrupt Capture 0 status bit Re-load the timer A count value Overwrite

Rev.2.00 Mar 15, 2007 Page 33 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Serial Interface

• Serial I/O Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/ O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register (bit 6) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Fig 43. Block diagram of clock synchronous serial I/O Fig 44. Operation of clock synchronous serial I/O function Serial I/O control register Receive buffer register 1 Receive shift register 1 Clock control circuit 1/4Baud rate generatorφSOURCE Clock control circuitFalling-edge detector Transmit buffer register Transmit shift register Serial I/O status register F/F Address 001816 Receive buffer full flag (RBF) Receive interrupt request (RI) Shift clock Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Address 001C16 BRG count source selection bit Address 001816 Shift clock Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Address 001A16 Data bus Data bus P06/SCLK P04/RXD P05/TXD P07/SRDY D0 D1 D2 D3 D4 D5 D6 D0 D1 D2 D3 D4 D5 D6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD Write pulse to receive/transmit buffer register 1 (address 001816) Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal S RDY

Rev.2.00 Mar 15, 2007 Page 34 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift re gisters each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig 45. Block diagram of UART serial I/O Fig 46. Operation of UART serial I/O function OE PE FE Data bus Data bus Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer register Transmit shift register Address 001816 Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 ST detector SP detector UART control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O1 status register Serial I/O 1 control register P06/SCLK P04/RXD P05/TXD φSOURCE TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 TBE=1 TSC=1* STD0 D1 SP D 0 D1ST SP Transmit or receive clock Transmit buffer write signal Serial output TXD Receive buffer read signal Serial input RXD * Generated at 2nd bit in 2-stop-bit mode1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. STD0 D1 SP D 0 D1ST SP

Rev.2.00 Mar 15, 2007 Page 35 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. [Transmit buffer register/r eceive buffer register (TB/ RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O status register (SIOSTS)] 001916 The read-only serial I/O status re gister consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detect ed at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O control register (SIOCON)] 001A The serial I/O control register c onsists of eight control bits for the serial I/O function. [UART control register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchro nous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P05/TxD pin. [Baud rate generator (BRG)] 001C16 The baud rate generator determin es the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.

• Notes on Serial I/O
• Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occu rrence synchronized with the transmission enabled, take the following sequence. 1. Set the serial I/O transmit interrupt enable bit to “0” (dis- abled). 2. Set the transmit enable bit to “1”. 3. Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. 4. Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O is enabled. The functions of P0 6 and P07 are switched with the setting values of a serial I/O mode selection bit and a serial I/O synchronous clock selection bit as follows. (1) Serial I/O mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O synchronous clock selection bit “0” : P06 pin turns into an output pin of a synchronous clock. “1” : P06 pin turns into an input pin of a synchronous clock. Setup of a SRDY output enable bit (SRDY) “0” : P07 pin can be used as a normal I/O pin. “1” : P07 pin turns into a SRDY output pin. (2) Serial I/O mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O synchronous clock selection bit “0” : P06 pin can be used as a normal I/O pin. “1” : P06 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P0 7 pin. It can be used as a normal I/O pin.

Rev.2.00 Mar 15, 2007 Page 36 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 47. Structure of serial I/O1-related registers Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift inprogress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) UART control register (UARTCON: address 001B 16, initial value: E016) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) BRG count source selection bit (CSS) 0: φSOURCE 1: φSOURCE/4 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. S RDY output enable bit (SRDY) 0: P07 pin operates as ordinary I/O pin 1: P07 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P0 4 to P07 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P0 4 to P07 operate as serial I/O pins) Serial I/O control register (SIOCON: address 001A16, initial value: 0016) Serial I/O status register (SIOSTS: address 001916, initial value: 8016) b0 b7 b0 b7 b0

Rev.2.00 Mar 15, 2007 Page 37 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. A/D Converter The functional blocks of the A/D converter are described below. [AD conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/D conversion. [AD control register] ADCON The AD control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 3 is the AD conversion clock selection bit. When “0” is set to this bit, the A/D conversion clock is φSOURCE/2 and the A/D conversion time is 122 cycles of φSOURCE. When “1” is set to this bit, the A/D conversion clock is φSOURCE and the A/D conversion time is 61 cycles of φSOURCE. Bit 4 is the AD conversion completi on bit. The value of this bit remains at “0” during A/D conv ersion, and changes to “1” at completion of A/D conversion. A/D conversion is started by setting this bit to “0”. [Comparison voltage generator] The comparison voltage generato r divides the voltage between VSS and VCC by 1024, and outputs the divided voltages. [Channel selector] The channel selector se lects one of ports P1 5/AN5 to P10/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circ uit compares an analog input voltage with the comparison voltage and stores its result into the AD conversion register. When A/D conversion is completed, the control circuit sets the AD co nversion completion bit and the A/ D interrupt request bit to “1 ”. Because the comparator is constructed linked to a capacitor, set φSOURCE in order that the A/D conversion clock is 250 kHz or over during A/D conversion.

• Notes on A/D converter As for AD translation accuracy , on the following operating conditions, accuracy may become low. (1) When V CC voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at V CC = 3.0 V or more is recommended. (2) When X CIN or the low-speed on-chip oscillator is selected as φSOURCE, the A/D converter cannot be used. Fig 48. Structure of AD control register Fig 49. Structure of AD conversion register AD control register (ADCON: address 003416, initial value: 1016) Analog input pin selection bits 000: P10/AN0 001: P11/AN1 010: P12/AN2 011: P13/AN3 100: P14/AN4 101: P15/AN5 110: Not available 111: Not available A/D conversion clock selection bit 0: φSOURCE/2 1: φSOURCE A/D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns “0” when read) b7 b0 Read 8-bit (Read only address 003516) (Address 003516) Read 10-bit (read in order address 003616, 003516) (Address 003616) (Address 003516) Note: High-order 6-bit of address 003616 returns “0” when read. b7 b0 b9 b8 b7 b0 b6 b5 b4 b3 b2 b1 b0 b7 b0 b8 b7 b6 b5 b4 b3 b2

Rev.2.00 Mar 15, 2007 Page 38 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 50. Block diagram of A/D converter Channel selector A/D control circuit AD conversion register (low-order) Resistor ladder VCC VSS Comparator A/D interrupt request P10/AN0 P11/AN1 P12/AN2 P13/AN3 P14/AN4 P15/AN5 b7 b0 Data bus AD control register (Address 003416) AD conversion register (high-order) (Address 003616) (Address 003516) φSOURCE φSOURCE/2

Rev.2.00 Mar 15, 2007 Page 39 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16- bit counter. The operation of the watchdog timer is controlled by bits 2 to “0” in function set ROM data 2 and the watchdog timer control register.

• Watchdog timer disable bit When the watchdog timer disable bit (bit 1 in function set ROM data 2(FSROM2)) is set to “0”, the watchdog timer is enabled and starts counting after reset. Setting this bit to “1” does not operate the watchdog timer. This bit cannot be rewritten by executing the instruction. To use the watchdog timer, always set this bit to “0”. After reset, the watchdog timer cannot start counting by a program.
• Watchdog timer source clock selection bit The count source of the watchdog timer is selected by the watchdog timer source clock se lection bit (bit 0 in FSROM2). This bit cannot be rewritten by executing the instruction. When this bit is set to “0”, the count source is always set to the low-speed on-chip oscillator output/16. When this bit is set to “1”, the count source is set to φSOURCE/ 16. φSOURCE is changed by setting the clock selection bits (bits 5 and 4 in the clock mode register (CLKM: address 003716)).
• Watchdog timer H count source selection bit The count source of watchdog timer H is selected by the watchdog timer control register (WDTCON: address 003916). When the watchdog timer H count source selection bit (bit 7 in WDTCON) is set to “0”, the count source is set to an underflow signal from watch dog timer L. When this bit is set to “1”, the clock selected as the count source of watchdog timer L is input to watchdog timer H. The initial value of this bit after releasing reset can be set by the bit 2 in FSROM2.
• Watchdog Timer Operation Resetting or writing any data to WDTCON sets watchdog timer H to “FF16” and watchdog timer L to “FF 16”. When the watchdog timer starts, the selected clock is counted and internal reset occurs by the watchdog timer H underflow. Writing to WDTCON is usually programmed to be performed before underflow. Reading WDTCON reads the values of the high-order 6 bits in the watchdog timer H counter and the watch dog timer count source selection bit. The following shows the time to watchdog timer underflow after writing to the watchdog timer control register. The example applies when the X IN input clock is selected as φSOURCE and f(XIN) = 8 MHz.
• Watchdog timer H count source selection bit = 0: 131.072 ms
• Watchdog timer H count source selection bit = 1: 512 µs Fig 51. Structure of Function set ROM data 2 Fig 52. Structure of watchdog timer control register Fig 53. Block diagram of watchdog timer Watchdog timer source clock selection bit 0 : Low-speed on-chip oscillator/16 1 : System clock/16 Watchdog timer start selection bit 0 : Start watchdog timer 1 : Stop watchdog timer Watchdog timer H count source initial value selection bit 0 : Initial value of bit 7 of WDTCON after reset release is “0” 1 : Initial value of bit 7 of WDTCON after reset release is “1” STP instruction function selection bit 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution Low-speed on-chip oscillator control bit (Note 1) 0 : Stop of low-speed on-chip oscillator disabled 1 : Stop of low-speed on-chip oscillator enabled Set “0” to these bits certainly. Function set ROM data 2 FSROM2 (FFDA16) Note 1: If “0” is set to this bit, it is not possible to write “1” to bit 0 in the clock mode register. Also, the low-speed on-chip oscillator does not stop even if the STP instruction is executed. Watchdog timer H (read only for high-order 6-bit) Not used (returns “0” when read) Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : Low-speed on-chip oscillator/16 or φSOURCE/16 Watchdog timer control register (Note) (WDTCON: address 003916, initial value: X01111112) b7 b0 Note: The initial value of this register is changes by setting of function set ROM data 2. Watchdog timer H (8) Data bus Watchdog timer L (8) “FF16” is set at WDTCON writing φSOURCE Low-speed on-chip oscillator Watchdog timer source clock selection bit (bit 0 of FSROM2) Watchdog timer start selection bit (bit 1 of FSROM2) Reset circuit Internal reset STP instruction function selection bit (bit 3 of FSROM2) STP Instruction Reset pin input Watchdog timer H count source selection bit (bit 7 of WDTCON) Watchdog timer H count source initial value selection bit (bit 2 of FSROM2) FSROM2: Function set ROM data 2 WDTCON: Watchdog timer control register CPUM: CPU mode register “FF 16” is set at WDTCON writing Initial value setting after releasing reset

Rev.2.00 Mar 15, 2007 Page 40 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change.

• Notes on Watchdog Timer (1) The watchdog time r operates in wait mode. To prevent underflow, write to the watchdog timer control register. The watchdog timer stops in st op mode, but starts counting at the same time as exiting stop mode. After exiting stop mode, it continues counting dur ing oscillation stabilization time. To prevent underflow during the period, the watchdog timer H count source selection bit (bit 7) in the watchdog timer control register (address 0039 16) should be set to “0” before executing the STP instruction. Note that the watchdog timer continues counting even if the STP instruction is executed in the following two conditions:

1 Stopping the low-speed on-chip oscillator: Disabled (bit

4 in FSROM2) Source clock of the watchd og timer: Low-speed on-chip oscillator/16 (bit 0 in FSROM2)

2 Stopping the low-speed on-chip oscillator: Disabled (bit

4 in FSROM2) Source clock of the watchdog timer: φSOURCE (bit 0 in FSROM2) φSOURCE: Low-speed on-chip oscillator (bits 5 and 4 in CLKM) (2) STP instruction fu nction selection bit The function of the STP instruction can be selected by the bit 2 in FSROM2. This bit cannot be used for rewriting by executing the STP instruction.

• When this bit is set to “0”, stop mode is entered by executing the STP instruction.
• When this bit is set to “1”, internal reset occurs by executing the STP instruction.

Rev.2.00 Mar 15, 2007 Page 41 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Power-on Reset Circuit Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. To use the built-in power-on re set circuit, leave the RESET pin open (the pull-up resistor is built-in). Low Voltage Detection Circuit The built-in low voltage detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the power source voltage drops below a set value (Typ.1.95 V). The low voltage detection circuit is valid by setting “1” to bit 0 of the function set ROM data 0. Also, when “1” is set to bit 2 of the function set ROM data 1, the low voltage detection circuit can be valid even in the stop mode. The low voltage detection circuit is stopped in the stop mode by setting “0” to this bit, so that the power dissipation is reduced. Fig 54. Operation waveform diagram of power-on reset circuit Fig 55. Operation waveform diagram of low voltage detection circuit Fig 56. Timing diagram at reset VCC (Note) Power-on reset circuit output Internal reset signal Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.Reset released Reset state Power-on VCC Internal reset signal Reset voltage (Typ:1.95 V) Microcomputer starts operation by the built-in on-chip oscillator. ? ? FFFC FFFD ADH,ADL ? ? ADL ADH Reset address from the vector table Low-speed on-chip oscillator clock Internal CPU clock φ ? ? ? ? ? ? RESET Internal reset signal SYNC Address Data 9 to 16 cycles of internal CPU clock φ

Rev.2.00 Mar 15, 2007 Page 42 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 57. Timing diagram at reset Notes 1: X : Undefined 2: The content of other registers is undefined when the microcomputer is reset. The initial values must be surely set before you use it. 3: Do not access to the SFR area including nothing. 4: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial values of this bit at reset are changed. 001016 001116 001216 001316 001416 001516 Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) 001916Serial I/O status register (SIOSTS) 001A16Serial I/O control register (SIOCON) 001B16UART control register (UARTCON) 003016 003116 003216 003416AD control register (ADCON) 003716 003816Oscillation stop detection register (CLKSTP) 003916Watchdog timer control register (WDTCON) 003A16Interrupt edge selection register (INTEDGE) 003B16CPU mode register (CPUM) 003C16Interrupt request register 1 (IREQ1) 003D16Interrupt request register 2 (IREQ2) 003E16Interrupt control register 1 (ICON1) 003F16Interrupt control register 2 (ICON2) Clock mode register (CLKM) Port P0 drive capacity control register (DCCR) 000116Port P0 direction register (P0D) 000316 000516 000716 000C16 000D16 000E16 000F16 Timer A (low-order) (TAL) Timer A (high-order) (TAH) 002816Prescaler 12 (PRE12) 002916Timer 1 (T1) 002A16 002B16 002C16 002D16 002E16 Timer count source set register (TCSS) 002F16 Port P1 direction register (P1D) Port P2 direction register (P2D) Port P3 direction register (P3D) Capture/Compare register (low-order) (CRAL) Key-on wakeup input selection register (KEYS) Capture/Compare register (high-order) (CRAH) Capture/Compare register R/W pointer (CCRP) Compare output mode register (CMOM) Compare register re-load register (CMPR) Capture/Compare port register (CCPR) Capture/Compare status register (CCSR) Capture software trigger register (CSTR) Compare interrupt source set register (CISR) Capture mode register (CAPM) Timer mode register (TM) Timer 2 (T2) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) 0016 0016 0016 0016 0016 0016 0016 0016 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 Note 4 0 0016 0016 FF16 FF16 FF16 FF16 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016

Rev.2.00 Mar 15, 2007 Page 43 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Clock Circuit The clock circuit includes the X IN clock (ceramic oscillator or crystal oscillator can be used), XCIN clock (32 kHz oscillator can be used), external clock input, high-speed on-chip oscillator, and low-speed on-chip oscillator. Pins P20/XOUT/XCOUT and P21/XIN/XCIN can be shared for the ports, XIN oscillation, and XCIN oscillation. Use the oscillation method select ion bits (bits 1 and bit 0 in function set ROM data 1 (FSROM1)) to set the function of these pins.

• Ceramic Resonator or Crystal Oscillator Set the oscillation method sel ection bits (bits 1 and bit 0 in FSROM1) to “012”, and connect the resonator (or the oscillator) and external circuit with the shortest wiring length possible. The constants of the oscillator circuit differ depending on the resonator. Use the values recommended by the resonator manufacturer. (An external feedb ack resistor may be necessary under some conditions.) Setting the X IN /X CIN oscillation control bit to “0” starts oscillation. This bit is sets to “0” after reset.
• 32 kHz Crystal Oscillator Set the oscillation method selection bits to “102”, and connect the 32 kHz crystal oscillator and external circuit with the shortest wiring length possible. The constants of the oscillator circuit differ depending on the resonator. Use the values recommended by the resonator manufacturer. (An external feedb ack resistor may be necessary under some conditions.) Setting the X IN /X CIN oscillation control bit to “0” starts oscillation. This bit is sets to “0” after reset.
• External Clock Input Set the oscillation method selection bits to “112”, and connect the clock source to the P2 0/XOUT pin. In this case, the P2 1/XIN pin can be used as an I/O port.
• High-Speed On-Chip Oscillator The high-speed on-chip oscillator is stopped after reset. Setting the high-speed on-chip os cillator oscillation control bit (bit 1 in CLKM) to “0” starts osci llation. This bit is sets to “1” after reset.
• Low-Speed On-Chip Oscillator The low-speed on-chip oscillator au tomatically starts oscillating after reset. Setting the low-speed on-chip osc illator oscillation control bit (bit 0 in CLKM) to “1” stops oscillation. This bit is sets to “0” after reset. If the low-speed on-chip oscillator control bit (bit 4 in FSROM2) is set to “0” and stopping the low-speed on-chip oscillator is disabled, the low-speed on-chip oscillator oscillation control bit cannot be set to “1” and oscillation cannot be stopped. Also, the oscillator does not stop even when the STP instruction is executed.
• Using No Oscillator Pins (P2 0 as output port and P2 1 as I/O port) To use only an internal on-chi p oscillator, set the oscillation method selection bits to “002”. The P20/XOUT pin can be used as an output port and the P21/XIN pin can be used as an I/O port. Fig 58. Structure of function set ROM data 1 Fig 59. External circuit of ceramic resonator Fig 60. External circuit of 32 kHz quarts-crystal oscillator Fig 61. External clock input circuit Oscillation method selection bits (Note 1) b1 b0 0 0: Clock pins not used (P20/XOUT and P21/XIN are used as I/O ports) 0 1: Ceramic resonator or quarts-crystal oscillator 1 0: 32 kHz quarts-crystal oscillator 1 1: External clock input (P21/XIN pin is used as I/O port) Low voltage detection circuit valid bit in the stop mode (Note 2) 0: Low voltage detection circuit invalid in the stop mode 1: Low voltage detection circuit valid in the stop mode Set “0” to these bits certainly. Set “1” to this bit certainly. Function set ROM data 1 FSROM1 (FFD916) Notes 1: The P20/XOUT and P21/XIN pins build in an on-chip oscillator. Even if these pins are used as I/O ports, the oscillator circuit is enabled when the MCU’s Vcc voltage drops below the operation limit voltage. In this case these pins may output undefined values. 2: When the Low voltage detection circuit is set to be valid in the stop mode, the dissipation current in the stop mode is increased. M37548 XIN XOUT Rd COUTCIN Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer’s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on- chip, insert a feedback resistor between XIN and XOUT following the instruction. M37548 XCIN XCOUT Rd COUTCIN Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer’s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between X IN and XOUT following the instruction. M37548 P21 XOUT I/O port External oscillation circuit Vcc Vss Connect the external clock to the P20/XOUT pin, not the P21/XIN pin.

Rev.2.00 Mar 15, 2007 Page 44 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 62. Structure of clock mode register

• Note on Clock Circuit
• Switching to XIN/XCIN Oscillator After a reset is cleared, operatio n starts using the low-speed on- chip oscillator. When switching to X IN/XCIN oscillator, make sure to set a sufficient wait duration with the on-chip oscillator to allow the XIN/XCIN oscillator to stabilize. Low-speed on-chip oscillator oscillation control bit (Notes 1, 2, and 4) 0: Oscillation start 1: Oscillation stop High-speed on-chip oscillator oscillation control bit (Notes 2 and 4) 0: Oscillation start 1: Oscillation stop XIN oscillation control bit (Notes 2 and 4) 0: Oscillation start 1: Oscillation stop Oscillation stabilization time set bit after release of the STP instruction 0: Timer 1 set to “0116” and prescaler 12 to “FF16” automatically 1: Un-automatically Clock selection bits (Notes 3 and 4) b5 b4 0 0 : Low-speed on-chip oscillator 0 1 : High-speed on-chip oscillator 1 0 : X IN/XCIN oscillation, External clock 1 1 : Not available Clock division ratio selection bit b7 b6 0 0 : φSOURCE/8 (low-speed mode) 0 1 : φSOURCE/4 (middle-speed mode) 1 0 : φSOURCE/2 (high-speed mode) 1 1 : No division (double-speed mode) Clock mode register (CLKM: address 003716, initial value: 0216) Notes 1: When stopping the low-speed on-chip oscillator is disabled by setting the low-speed on-chip oscillator control bit (bit 4 in FSROM2), “1” cannot be written to this bit. The low-speed on-chip oscillator does not stop even in stop mode. 2: “1” cannot be written to the oscillation control bits (bits 2 to 0) of the clock selected as φSOURCE by the clock selection bits. 3: When “oscillation pins not used” is set by the oscillation method selection bits (bits 1 and 0 in FSROM1), “102” cannot be written to these bits. 4: Do not change the values of the clock selection bits and the clock oscillation control bits at the same time using a single instruction. Always use different instructions to rewrite these values.

Rev.2.00 Mar 15, 2007 Page 45 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Oscillation Control

• Clock mode register Clock mode register contains th e oscillation control bits of each oscillation circuits, clock selection bits and etc
• Clock selection bits φSOURCE can be selected by the clock selection bits (bits 5 and 4 in clock mode register). φSOURCE can be selected from low- speed on-chip oscillator, high-speed on-chip oscillator, XIN/XCIN oscillation or external clock i nput by the clock selection bits. φSOURCE is also used to the clock for peripheral functions. When the oscillation method selection bits (bits 1 and 0 in FSROM1) is set to “00 2” (oscillation pins not used), setting the clock selection bits to “10 2” (XIN/XCIN oscillation, external clock input) is disabled.
• Clock division ratio selection bit The internal clock φ is generated by dividing φSOURCE. Select the division ratio using the clock division ration selection bits (bits 7 and 6 in CLKM). The division ratio can be selected from among φSOURCE/8 (low-speed mode), /4 (middle-speed mode), /2 (high-speed mode), and no division (double-speed mode). Table 9 shows the division ratio (mode) settings. When releasing reset, the low-speed on-chip oscillator is selected as φSOURCE, and φSOURCE/8 is selected as the internal clock. The high-speed on-chip oscillator is stopped at this time. If an oscillation circuit is connected to the clock pin, oscillation starts. To switch φSOURCE to XIN/XCIN oscillation, generate wait time using the on-chip oscillator until the oscillation is stabilized. −: can be “0” or “1”, no change in outcome Table 9 Setting the clock division (mode) φSOURCE CLKM FSROM1 FSROM2 Clock division ratio selection bits Clock selection bits XIN/XCIN oscillation control bit High-speed on-chip oscillator oscillation control bit Low-speed on-chip oscillator oscillation control bit Oscillation method selection bits Low-speed on- chip oscillator control bit Bit 7, 6 Bit 5, 4 Bit 2 Bit 1 Bit 0 Bit 1, 0 Bit 4 XIN Double-speed 11 10 0 −− 01 − High-speed 10 10 0 −− 01 − Middle-speed 01 10 0 −− 01 − Low-speed 00 10 0 −− 01 − XCIN Double-speed 11 10 0 −− 10 − High-speed 10 10 0 −− 10 − Middle-speed 01 10 0 −− 10 − Low-speed 00 10 0 −− 10 − External clock Double-speed 11 10 −− − 11 − High-speed 10 10 −− − 11 − Middle-speed 01 10 −− − 11 − Low-speed 00 10 −− − 11 − High-speed on-chip oscillator Double-speed 11 01 − 0 −−− High-speed 10 01 − 0 −−− Middle-speed 01 01 − 0 −−− Low-speed 00 01 − 0 −−− Low-speed on-chip oscillator Double-speed 11 00 −− 0 − 1/0 High-speed 10 00 −− 0 − 1/0 Middle-speed 01 00 −− 0 − 1/0 Low-speed 00 00 −− 0 − 1/0 bit Mode

Rev.2.00 Mar 15, 2007 Page 46 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change.

• Stop mode When the STP instruction is executed, the internal clock φ stops at an “H” level and the XIN/XCIN and on-chip oscillator stops. At this time, timer 1 is set to “0116” and prescaler 12 is set to “FF16” when the oscillation stabilization time set bit after release of the STP instruction is “0”. On the other hand, timer 1 and prescaler 12 are not set when the above bit is “1”. Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. When an external interr upt is accepted, oscillation is restarted but the internal clock φ remains at “H” until timer 1 underflows. As soon as timer 1 underflows, the internal clock φ is supplied. This is because when a ceramic resonator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an “L” level to the RESET pin while oscillation becomes stable, or set the wait time by on-chip oscillator operation after system is released from reset until the oscillation is stabled.
• W a i t m o d e If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operati on can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed.
• Note on Oscillation Control For use with the oscillation stabilization set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 12 after fully appreciating the oscillation stabilization time of the oscillator to be used.

Rev.2.00 Mar 15, 2007 Page 47 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 63. Block diagram of internal clock generating circuit “00”: Low-speed modeHigh-speed on-chip oscillator (HSOCO) Timing φ (Internal clock)φSOURCE “10”: High-speed mode Clock division ratio selection bits WIT instruction Low-speed on-chip oscillator (LSOCO) “01”: Middle-speed mode “11”: Double-speed mode Peripheral function clock generation circuit (1/1 to 1/256) Clock selection bits High-speed on-chip oscillator oscillation control bit Low-speed on-chip oscillator oscillation control bit Prescaler 12Timer 1 Oscillation stabilization time set timer after release of the STP instruction SQ R Reset Interrupt disable flag I Interrupt request XIN/XCIN oscillation control bit Bits 0 and 1 of FSROM1: setting of the oscillation method setection bits “00”: Clock pins not used P21/XIN/XCIN Port P21 control circuit P20/XOUT/XCOUT Port P20 control circuit “10” “01” “00” It is not possible to write “1” to the low-speed on-chip oscillator oscillation control bit if low-speed on-chip oscillator stop has been disabled by bit 4 in FSROM2. Also, the low-speed on-chip oscillator does not stop even if the STP instruction is executed. XIN oscillation cannot be selected as φSOURCE if clock pins not used is selected. P21/XIN/XCIN Port P21 control circuit P20/XOUT/XCOUT “11”: External clock input Noise filter P21/XIN/XCIN P20/XOUT/XCOUT Rf “10”: 32 kHz quartz- crystal oscillation P21/XIN/XCIN P20/XOUT/XCOUT Rf “01”: Ceramic or quartz- crystal oscillation 1/1 to 1/256 Peripheral function (Note 2) (Note 2) Reset SQ R QS STP instruction STP instructionR Notes 1: The oscillation circuit is built in the P20/XOUT/XCOUT pin and the P21/XIN/XCIN pin. When the Vcc of the microcomputer is lower than the operation lower bound voltage even if these pins are used as I/O ports, the oscillation circuit is connected and undefined values may be output from these pins. 2: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.

Rev.2.00 Mar 15, 2007 Page 48 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 64. φSOURCE state transition

• XIN HSOCO “S” LSOCO “S” xx10x011 X IN “O” HSOCO “O”
• LSOCO xx00x000 X IN “S” HSOCO “S”
• LSOCO xx00x110 X IN “S”
• HSOCO LSOCO “S” xx01x101
• XIN HSOCO “O” LSOCO “S” xx10x001 X IN “O” HSOCO “S”
• LSOCO xx00x010 X IN “S” HSOCO “O”
• LSOCO xx00x100
• XIN HSOCO “O” LSOCO “O” xx10x000 X IN “O”
• HSOCO LSOCO “O” xx01x000
• XIN HSOCO “S” LSOCO “O” xx10x010 X IN “S”
• HSOCO LSOCO “O” xx01x100 X IN “O”
• HSOCO LSOCO “S” xx01x001 High-speed on-chip oscillator (HSOCO): oscillation start b1=0 XIN oscillation: oscillation start (Note 3) b2=0 Low-speed on-chip oscillator (LSOCO): oscillation start b0=0 φSOURCE selection HSOCO (b5,4=0,1) X IN (b5,4=1,0)(Note 3) XIN Stop (b2=1)Oscillation (b2=0) HSOCO Oscillation (b1=0) Stop (b1=1) φSOURCE selection HSOCO(b5,4=0,1) LSOCO(b5,4=0,0) LSOCO Stop (b0=1)Oscillation (b0=0) HSOCOOscillation (b1=0) Stop(b1=1) φSOURCE selection XIN (b5,4=1,0) (Note 3) LSOCO (b5,4=0,0) LSOCO Stop (b0=1) Oscillation (b0=0) XIN Oscillation (b2=0) Stop(b2=1) b5,4 (Note 3) b5,4 b5,4(Note 3) b1,0 b0(Note 1) b0(Note 1) b0(Note 1) b5,4 (Note 3) b2,0 (Note 1) b2 b5,4 b2,1 (Note 1) b0(Note 1) b2,0 (Note 1) b1,0 (Note 1) b2,1 [Remarks] Reset released State transition of clock mode register CLKM (address: 003716) setting value and clock (When XIN oscillation is used. The same applies when XCIN oscillation and external clock input are used.) X IN “O” HSOCO “S”
• LSOCO xx00x010 b5,4 (Note 3) (Note 2) XIN, HSOCO, LSOCO, and respective oscillation and stop status in each mode are shown. The symbol (•) indicates φSOURCE (oscillation) selected by the clock selection bits. “O” indicates oscillation and “S” indicates stopping. The values such as “xx00x010” indicate the values (binary) of the clock mode register in the mode. The arrow (bx) indicates a bit in the clock mode register, showing a transition by changing the bit values. Entering the mode should be performed according to the arrows. Wait mode and stop mode can be entered from all modes, and the original mode is returned after exiting. Notes 1: When stopping the low-speed on-chip oscillator is disabled by the low-speed on-chip oscillator control bit (bit 4 in FSROM2), “1” cannot be written to the bit 0 in CLKM. The low-speed on-chip oscillator does not stop even in stop mode. 2: After releasing reset, the low-speed on-chip oscillator is selected as φSOURCE and divided by 8 is selected as the CPU clock. 3: When the oscillation pins not used is set by the oscillation method selection bits (bits 1 and 0 in FSROM1), “10” cannot be written to bits 5 and 5 in CLKM. To use X IN oscillation as φSOURCE, switch after XIN oscillation is stabilized. Supply a stable clock when an external clock is used. 4: Do not change the values of the clock selection bits (bits 5 and 4) in CLKM and the individual clock oscillation control bi ts (bits 2 to 0) at the same time using a singe instruction. Always use different instructions to rewrite these values. 5: Wait until the oscillation used in the destination mode is stabilized before entering. Wait mode
• Low-speed on-chip oscillator: Status before executing WIT instruction is kept
• High-speed on-chip oscillator: Status before executing WIT instruction is kept
• XIN oscillation: Status before executing the WIT instruction is kept Stop mode
• Low-speed on-chip oscillator: Stopped (Note 1)
• High-speed on-chip oscillator: Stopped
• XIN oscillation: Stopped b5,4 (Note 3)

Rev.2.00 Mar 15, 2007 Page 49 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change.

• Oscillation stop detection circuit The oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or RC oscillation ci rcuit stops by disconnection. To use this circuit, set an on-chip oscillator to be in active. The oscillation stop detection circuit is in active to set “1” to the X IN oscillation stop detection function active bit. When the oscillation stop detection circuit is enabled, the operation status of the X IN oscillator circuit is monitored using the low-speed on-chip oscillato r, and if oscillation stop is detected the oscillation stop detection status bit is set to 1. If additionally the oscillation stop detection reset enable bit is set to “1”, an internal reset is trig gered when the oscillator stops operating. The oscillation stop detection status bit is not initialized by an oscillation stop detection reset an d retains its value of 1. Since the oscillation stop detection status bit is initialized to “0” by an external reset, it is possible to determine if a reset was due to oscillation stop detection by checking the oscillation stop detection status bit. The X IN oscillation and external clock input are set as the clocks to detect the oscillation stop. Refer to the electrical characteristics for the frequencies to detect the oscillation stop.
• Notes on Oscillation Stop Detection Circuit (1) Do not execute the transition to “state 2'a” shown in Figure 66 because in this “state 2'a”, MCU is stopped without reset even when X IN oscillation is stopped. (2) X IN oscillation stop detection function active bit is not cleared by the oscillation stop detection reset. Accordingly, the oscillation stop detection circuit is in active when system is released from internal reset cause of oscillation stop detection. (3) Oscillation stop detection status bit is initialized by the following operation.
• External reset, power-on reset, low voltage detection reset, watchdog timer reset, and reset by STP instruction function
• Write “0” data to the X IN oscillation stop detection function active bit. (4) The oscillation stop detection circuit is not included in the emulator MCU “M37549RLSS”. Fig 65. Structure of oscillation stop detection register Fig 66. State transition of oscillation stop detection circuit XIN oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active Oscillation stop detection reset enable bit 0: Oscillation stop detection reset disabled 1: Oscillation stop detection reset enabled Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected Not used (“0” at reading) Oscillation stop detection register (CLKSTP: address 003816, initial value: 0016) Notes on switch of clock (1) Executing the state transition after stabilizing XIN oscillation. (2) MCU cannot be returned by on-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected in state 2'a. Accordingly, do not execute the transition to state 2'a. (3) STP instruction cannot be used when oscillation stop detection circuit is in active. (4) The same applies when the high-speed on-chip oscillator is set as φSOURCE. Make sure that the low-speed on-chip oscillator should also oscillate. When a reset occurs, the high-speed on-chip oscillator stops. Reset state 1 Oscillation stop detection reset disabled When oscillation stop is detected; CLKSTP2 is set to “1”. Internal RESET does not occur. = 02= 12 CLKSTP0 = 02 (CLKSTP2 is set to “0”.) CLKSTP 0 = 12 (Note 1) Oscillation stop is detected (internal reset) Reset state 2 External reset (RESET=“L”) ⋅ Power-on reset ⋅ Low voltage detection reset ⋅ Watchdog timer reset ⋅ Reset by STP instruction function Return from oscillation stop detection reset CLKSTP2 is set to “1”. So, return from oscillation stop reset can be confirmed. CLKSTP1= 02 CLKSTP1 = 02 (CLKSTP2 is set to “0”.) CLKM54 = 102 CLKM54 = 002 (Note 1) Prohibitive state MCU stops when oscillation stops occurs. State 3'a State 2'b State 3'b State 3'c Oscillation stop detection reset enabled When oscillation stop is detected; CLKSTP2 is set to “1”. Internal RESET occurs. Oscillation stop detection reset enabled When oscillation stop is detected; CLKSTP2 is set to “1”. Internal RESET occurs. Reset released CLKM54 = 102 CLKM54 = 002 (Note 1) CLKM54=102 CLKM54=002 (Note 1) State 3 XIN oscillation : enabled Low-speed on-chip oscillator : enabled State 3' XIN oscillation : enabled Low-speed on-chip oscillator : enabled XIN : enabled High-speed on-chip oscillator: stop Low-speed on-chip oscillator : enabled CLKSTP1 CLKSTP1 CLKSTP1 = 12 State 2' CLKSTP1= 12 XIN : enabled High-speed on-chip oscillator: stop Low-speed on-chip oscillator : enabled Reset released XIN oscillation : enabled Low-speed on-chip oscillator : enabled XIN oscillation : enabled Low-speed on-chip oscillator : enabled State 2 (Note 2) (Note 2) (Note 2) φSOURCE: XIN φSOURCE: Low-speed on-chip oscillator (Note 4) Oscillation stop detection circuit is in active. (Note 3) State 2'a (Note 2) Oscillation stop detection reset disabled When oscillation stop is detected; CLKSTP2 is set to "1". Internal RESET does not occur.

Rev.2.00 Mar 15, 2007 Page 50 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. QzROM Writing Mode In the QzROM writing mode , the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for this microcomputer. Table 10 lists the pin descript ion (QzROM writing mode) and Figure 67 shows the pin connections. Refer to Figure 68 and Figure 69 for examples of a connection with a serial programmer. Contact the manufacturer of yo ur serial programmer for serial programmer. Refer to the user's manual of you r serial programmer for details on how to use it. Table 10 Pin description (QzROM writing mode) Fig 67. Pin connection di agram (M37548G3/G2/G1FP) Pin Name I/O Function VCC, VSS Power source Input Apply 1.8 to 5.5 V to V CC, and 0 V to VSS. RESET Reset input Input Reset input pin. 1 /XIN Clock input Input Set the same termination as the single-chip mode. P20 /XOUT Clock output Output P00 − P05 P11 − P15 I/O port I/O Input “H” or “L” level signal or leave the pin open. CNVSS VPP input Input QzROM programmable power source pin. P10 ESDA I/O I/O Serial data I/O pin. P06 ESCLK input Input Serial clock input pin. P07 ESPGMB input Input Read/program pulse input pin. P13/AN3/KEY3/T2OUT P12/AN2/KEY2/CMP2 P11/AN1/KEY1/CMP1 P10/AN0/KEY0/CMP0 P07(LED7)/SRDY P06(LED6)/SCLK P05(LED5)/TxD P04(LED4)/RxD P03(LED3)/CAP0 P02(LED2) RESET P15/AN5/KEY5 P14/AN4/KEY4 P20/XOUT/XCOUT VSS VCC P21/XIN/XCIN CNVSS P00(LED0)/INT0 P01(LED1)/INT1 M37548G3/G2/G1FP RESET GND VCC VPP ESDA ESPGMB ESCLK ∗ : Set the same termination as the single-chip mode. : QzROM pin

Rev.2.00 Mar 15, 2007 Page 51 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 68. When using E8 programmer, connection example Set the same termination as the single-chip mode. Vcc P10 (ESDA) RESET Vss P21/XIN P20/XOUT 4.7 kΩ * 1: Open-collector buffer Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF Vcc CNVSS 4.7 kΩ P06 (ESCLK) P07 (ESPGMB)

Rev.2.00 Mar 15, 2007 Page 52 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 69. When using programmer of Suisei Electronics System Co., LTD, connection example Set the same termination as the single-chip mode. Vcc P10 (ESDA) RESET Vss P21/XIN P20/XOUT Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. CNVSS T_VDD T_VPP T_RXD T_SCLK T_PGM/OE/MD RESET circuit T_RESET GND 4.7 kΩ 4.7 kΩ T_TXD T_BUSY N.C. P06 (ESCLK) P07 (ESPGMB)

Rev.2.00 Mar 15, 2007 Page 53 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. NOTES ON PROGRAMMING (1) Processor Status Register The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is “1”. After reset, initialize flags whic h affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. (2) Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruc tion before executing the BBC or BBS instruction. (3) Decimal Calculations

• For calculations in decimal notation, set the decimal mode flag D to “1”, then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instru ction after executing one instruction before the ADC instruction or SBC instruction.
• In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. (4) Ports The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qua lifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA in- struction, etc. (5) A/D Conversion Do not execute the STP instruction during A/D conversion. (6) Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock φ is the same as that of the φSOURCE in double-speed mode, twice the φSOURCE cycle in high-speed mode, 4 times the φSOURCE cycle in middle-speed mode and 8 times the φSOURCE cycle in low-speed mode. (7) CPU Mode Register The processor mode bits can be written only once after releasing reset. Always set them to “002”. After written, rewriting any data to these bits is disabled because they are locked. (Emulator MCU is excluded.) Also, the stack page bit (bit 2) is not locked. In order to prevent error-writing to the processor mode bits (at program runaway), write the CPU mode register at the start of the program that runs after releasing reset. (8) State transition Do not stop the clock selected as the operation clock because of setting of bits 0 to 2. NOTES ON HARDWARE (1) Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (V CC pin) and GND pin (V SS pin). A ceramic capacitor of 0.01 µF to 0.1 µF is recommended. Connect a capacitor across the power source pin and GND pin with the shortest possible wiring.

Rev.2.00 Mar 15, 2007 Page 54 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. NOTES ON USE Countermeasures against noise It is necessary not only design the system taking measures against the noise as follows but to evaluate before actual use. 1. Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. <Reason> The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise. Fig 70. Selection of packages (2) Wiring for RESET pin Make the length of wiring whic h is connected to the RESET pin as short as possible. Especially , connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20 mm). <Reason> The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Fig 71. Wiring for the RESET pin (3) Wiring for cloc k input/output pins

• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacito r which is connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for osc illation from other VSS patterns. <Reason> If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in the microcomputer. Fig 72. Wiring for clock I/O pins (4) Wiring to CNVSS pin Connect CNV SS pin to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to V SS. In order to improve the noise reduction, to connect a 5 k Ω resistor serially to the CNVSS pin - GND line may be valid. As well as the above-mentioned, in this case, connect to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to VSS. <Reason> The CNVSS pin of the QzROM is the power source input pin for the built-in QzROM. When pr ogramming in the built-in QzROM, the impedance of the CNV SS pin is low to allow the electric current for writing flow into the QzROM. Because of this, noise can enter easily. If noise enters the CNV SS pin, abnormal instruction codes or data are read from the built-in QzROM, which may cause a program runaway. Fig 73. Wiring for the V PP pin of the QzPROM DIP SDIP SOP QFP RESETReset circuit Noise VSSVSS N.G. Reset circuit VSS RESET VSS O.K. Noise XIN XOUT VSS N.G. XIN XOUT VSS O.K. CNVSS VSS About 5 kΩ The shortest The shortest (Note) (Note) Note: This indicates pin.

Rev.2.00 Mar 15, 2007 Page 55 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. 2. Connection of bypass capacitor across V SS line and VCC line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:

• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Fig 74. Bypass capacitor across the V SS line and the VCC line 3. Wiring to analog input pins
• Connect an approximately 100 Ω to 1 k Ω r e s i s t o r t o a n analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pi n. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. <Reason> Signals which is input in an an alog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Fig 75. Analog signal line and a resistor and a capacitor
• The analog input pin is conn ected to the capacitor of a voltage comparator. Accordingl y, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the an alog signal source of high- impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. VSS VCC VSS VCC N.G. O.K. Noise Thermistor Analog input pin (Note) N.G. O.K. VSS Note : The resistor is used for dividing resistance with a thermistor. Microcomputer

Rev.2.00 Mar 15, 2007 Page 56 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. 4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a mi- crocomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows. <Reason> In the system using a microcom puter, there are signal lines for controlling motors, LEDs, and ther mal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a conn ecting pattern of an oscillator away from signal lines where pote ntial levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. <Reason> Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock wave- forms may be deformed, which causes a microcomputer failure or a program runaway. Fig 76. Wiring for a large current signal line/Writing of signal lines where potential levels change frequently (3) Oscillator protection using V SS pattern As for a two-sided printed circuit board, print a V SS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides, separate this V SS pattern from other VSS patterns. Fig 77. V SS pattern on the underside of an oscillator XIN XOUT VSS M Microcomputer Mutual inductance Large current GND XIN XOUT VSS CNTRDo not cross N.G. (1) Keeping oscillator away from large current signal lines (2) Installing oscillator away from signal lines where potential levels change frequently Oscillator wiring pattern example An example of VSS patterns on the underside of a printed circuit board Separate the VSS line for oscillation from other VSS lines XIN XOUT VSS

Rev.2.00 Mar 15, 2007 Page 57 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware>

• Connect a resistor of 100 Ω or more to an I/O port in series. <Software>
• As for an input port, read data several times by a program for checking whether input levels are equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods. Fig 78. Setup for I/O ports 6. Providing of watchdog timer function by software If a microcomputer runs away becau se of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runa way detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal op- eration, the main routine detects errors of the interrupt processing routine and the interrupt processi ng routine detects errors of the main routine. This example assumes that interr upt processing is repeated mul- tiple times in a single main routine processing. <The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N + 1 ≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT conten ts with counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to th e program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine>
• Decrements the SWDT conten ts by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initia lization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Fig 79. Watchdog timer by software N.G. O.K. Noise Noise Data bus Direction register Port latch I/O port pins N Main routine (SWDT) ← N CLI Main processing (SWDT) =N? Interrupt processing routine errors Interrupt processing routine (SWDT) ← (SWDT)−1 Interrupt processing (SWDT) ≤0? RTI Return Main routine errors

Rev.2.00 Mar 15, 2007 Page 58 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. NOTES ON USE Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicat ed as the recommended operating conditions, the microc omputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the s upply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Product shipped in blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a wri ting environment may cause some writing errors. Overvoltage Take care not to apply the volta ge above the Vcc pin voltage to other pins. Make sure that the voltage of the CNV SS pin (V PP power input pin for QzROM) does not change as shown in the bold-lined periods (Figure 80) when powering on and off. If the voltage changes as shown, the QzROM contents may be rewritten. Fig 80. Timing Diagram (bold-lin ed periods are applicable) NOTES ON QzROM Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .mask) which is made by the mask file converter MM. Be sure to set the ROM option (“MASK option” written in the mask file converter) setup when making the mask file by using the mask file converter MM. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. Renesas Technology corp. write the value of the ROM option setup data in the ROM code protect address (address FFDB 16) when writing to the QzROM. As a result, in the contents of the ROM code protect address the ordered value may differ from the actual written value. The ROM option setup data in the mask file is “00 16” for protect enabled or “FF16” for protect disabled. Therefore, the contents of the ROM code protect address (other than the user ROM area) of the QzROM product shipped after writing is “0016” or “FF16”. Note that the mask file which has nothing at the ROM option data or has the data other than “00 16” and “FF 16” can not be accepted. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* * For the QzROM writing confirmation form and the mark specification form, refer to th e “Renesas Technology Corp.” Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. VCC pin voltage CNVSS pin voltage 1.8 V 1.8 V (1) The input voltage to other MCU pins rises before the VCC pin voltage rises. (2) The input voltage to other MCU pins falls before the VCC pin voltage falls. Note: If VCC falls below the minimum value 1.8 V (shaded areas), the internal circuit becomes unstable. Take additional care to prevent overvoltage. ~~(1) (2)

Rev.2.00 Mar 15, 2007 Page 59 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. ELECTRICAL CHARACTERISTICS of 7548 Group Absolute Maximum Ratings Absolute maximum ratings VCC VI VI VI VO Pd Topr Tstg Power source voltage Input voltage P00−P07, P10−P15, P20, P21 Input voltage RESET Input voltage CNVSS Output voltage P00−P07, P10−P15, P20, P21 Power dissipation Operating temperature Storage temperature −0.3 to 6.5 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 300 −20 to 85 −40 to 125 V V V V V mW Ta = 25 °C Symbol Parameter Conditions Ratings Unit All voltages are based on VSS. When an input voltage is measured, output transistors are cut off.

Rev.2.00 Mar 15, 2007 Page 60 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Recommended Operating Conditions Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTES: 1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2. The peak output current is the peak current flowing in each port. 3. The average output current I OL (avg), IOH (avg) in an average value measured over 100 ms. 4. P2 0 and P21 indicates these pins are used as I/O ports. 5. X IN and XCIN indicates these pins are used as clock pins. Min. 0.8VCC 0.8VCC V V V V V V mA mA mA mA mA mA Typ. 0Power source voltage “H” input voltage (Note 4) P00−P07, P10−P15, P21 “H” input voltage (Note 5) RESET, XIN, XcIN “L” input voltage (Note 4) P00−P07, P10−P15, P21 “L” input voltage RESET, CNVSS “L” input voltage (Note 5) XIN, XcIN “H” total peak output current (Notes 1, 4) P00−P07, P10−P15, P20, P21 “L” total peak output current (Note 1) P00−P07 “L” total peak output current (Notes 1, 4) P10−P15, P20, P21 “H” total average output current (Notes 1, 4) P00−P07, P10−P15, P20, P21 “L” total average output current (Note 1) P00−P07 “L” total average output current (Notes 1, 4) P10−P15, P20, P21 VCC VSS VIH VIH VIL VIL VIL ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) “H” peak output current (Notes 2, 4) P00−P07, P10−P15, P20, P21 IOH(peak) “L” peak output current (Notes 2, 4) P00−P07 (drive capacity: weakness), P10−P15, P20, P21 IOL(peak) “L” peak output current (Note 2) P00−P07 (drive capacity: strength) IOL(peak) “H” average output current (Notes 3, 4) P00−P07, P10−P15, P20, P21 IOH(avg) “L” average output current (Notes 3, 4) P00−P07 (drive capacity: weakness), P10−P15, P20, P21 IOL(avg) Symbol Parameter Limits Unit Max. VCC VCC 0.2VCC 0.2VCC 0.16VCC −60 −30 mA−10 mA10 mA30 mA−5 mA5 “L” average output current (Notes 3) P00−P07 (drive capacity: strength) IOL(avg) mA15 4.5 5.5 VXIN oscillation, XCIN oscillation, external clock input 5.0 XCIN oscillation 2.4 5.5 V5.0 1.8 5.5 V5.0 2.2 5.5 V5.0 Double-, high-, middle-, low-speed mode 4.0 5.5 V5.0High-speed on-chip oscillator Low-speed on-chip oscillator Double-, high-, middle-, low-speed mode 1.8 5.5 V5.0 4.0 5.5 V5.0 2.4 5.5 V5.0 1.8 5.5 V5.0 Double-speed mode High-, middle-, low-speed mode f(XIN) ≤ 8 MHz f(XIN) ≤ 2 MHz f(XIN) ≤ 1 MHz f(XIN) ≤ 8 MHz f(XIN) ≤ 4 MHz f(XIN) ≤ 1 MHz Double-, high-, middle-, low-speed mode f(XCIN) ≤ 50 kHz Power source voltage

Rev.2.00 Mar 15, 2007 Page 61 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Recommended operating conditions (2) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTE: 1. When the oscillation frequency has a duty cycle of 50 %. Fig 81. Power source voltage and oscillation frequency Min. Typ. f(XIN) Symbol Parameter Limits Unit Max. MHz X CIN oscillation (Vcc − 2.4) × 2

0.7 MHz+2

kHz32.768 MHz XIN oscillation External clock input MHz MHz MHz Double-speed mode High-, middle-, low-speed mode Vcc = 4.5−5.5 V Vcc = 2.4−4.5 V Vcc = 2.2−2.4 V Vcc = 4.0−5.5 V Vcc = 2.4−4.0 V Vcc = 1.8−2.4 V Double-, high-, middle-, low-speed mode Vcc = 1.8−5.5 V XIN oscillation frequency (Note 1) XCIN oscillation frequency (Note 1) (Vcc − 2.2) 0.2 +1 (Vcc − 2.4) 0.4 +4 (Vcc − 1.8) 0.2 +1 Oscillation frequency: XIN(MHz) Power source voltage: Vcc(V) 8.0 4.0 2.0 1.0 0.0 0.0 Low-speed on-chip oscillator (5 V/Typ:250 kHz)//Double-, high-, middle-, low-speed mode High-speed on-chip oscillator (5 V/Typ:4 MHz) Double-, high-, middle-, low-speed mode XCIN oscillation//Double-, high-, middle-, low-speed mode XIN oscillation Double-speed mode XIN oscillation High-, middle-, low-speed mode When XIN is used, the MCU can be operated within the range shown in diagonal lines. Confirm that the oscillation is stable within the operating supply voltage range before use. Contact the oscillator manufacturer for oscillation constants.

Rev.2.00 Mar 15, 2007 Page 62 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change.

Electrical Characteristics

Electrical characteristics (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTES: 1. P2 0 and P21 indicates these pins are used as I/O ports. 2. X IN and XCIN indicates these pins are used as clock pins. 3. P0 5 is measured when the P05/TXD P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. 4. It is available only when operating key-on wake up. Symbol Parameter Limits Min. Typ. Max. Unit “H” output voltage (Notes 1, 3) P00−P07, P10−P15, P21 Vcc−1.5 VVOH “L” output voltage (Note 1) P00−P07 (drive capacity: weakness) P10−P15, P21 VOL Test conditions IOH = −5 mA, Vcc = 4.0−5.5 V IOH = −1.0 mA, Vcc = 1.8−5.5 V Vcc−1.0 V IOL = 5 mA, Vcc = 4.0−5.5 V 1.5 V IOL = 1.5 mA, Vcc = 4.0−5.5 V 0.3 V IOL = 1.0 mA, Vcc = 1.8−5.5 V 1.0 V “L” output voltage P00−P07 (drive capacity: strength) VOL IOL = 15 mA, Vcc = 4.0−5.5 V 2.0 V IOL = 1.5 mA, Vcc = 4.0−5.5 V 0.3 V IOL = 1.0 mA, Vcc = 1.8−5.5 V 1.0 V Hysteresis INT 0, INT1, CAP0, P10−P15 (Note 4) RXD, SCLK, RESET VT+ − VT- 0.5 V “H” input current (Note 1) P00−P07, P10−P15, P21 IIH VI = Vcc (Pin floating. Pull up transistors is disable) 5.0 Oscillation stop detection circuit detection frequency 62.5 250 kHz150DOSC Vcc = 5.0 V, Ta = 25 °C Low-speed on-chip oscillator oscillation frequency 125 500 kHz250RLSOSC Vcc = 5.0 V, Ta = 25 °C “H” input current RESETIIH VI = Vcc 5 µA µA “H” input current (Note 2) X INIIH VI = Vcc 4.0 µA “L” input current (Note 1) P00−P07, P10−P15, P21 IIL VI = Vss (Pin floating. Pull up transistors is disable) −5.0 µA “L” input current RESET IIL VI = Vss −0.7 mA “L” input current (Note 2) XINIIL VI = Vss −4.0 µA “L” input current P00−P07, P10−P15IIL VI = Vss (Pull up transistors is enable) −0.5−0.2 mA RAM hold voltage 1.6 5.5 VVRAM When clock stopped Pull-up resistor value RESETRPH VI = Vss 25 kΩ High-speed on-chip oscillator oscillation frequency MHz RHSOSC Vcc = 4.0−5.5 V, Ta = 0−50 °C TBD TBD4 TBD TBD “H” input current (Note 2) X CINIIH VI = Vcc 0.5 µA “L” input current (Note 2) X CINIIL VI = Vss −0.3 µA

Rev.2.00 Mar 15, 2007 Page 63 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Electrical characteristics (2) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) Symbol Parameter Test conditions Limits Min. Typ. Max. Unit Icc Power source current f(XIN)=8 MHz (ceramic resonator)

• Vcc = 5.0 V
• High-speed on-chip oscillator: stop
• Low-speed on-chip oscillator: stop
• Output transistors “off”
• Low voltage detection circuit: enable Low-speed on-chip oscillator: oscillation
• Vcc = 5.0 V
• High-speed on-chip oscillator: stop
• XIN: stop
• Output transistors “off”
• Low voltage detection circuit: enable Increment when A/D conversion is executed f(XIN) = 8 MHz, , Vcc = 5.0 V Stop mode
• Output transistors “off”
• Low-speed on-chip oscillator: stop
• Low voltage detection circuit: stop Ta = 25 °C Ta = 85 °C Double-speed mode 5.22.5 µA µA mA Low-speed mode 1.70.6 mA High-speed on-chip oscillator: oscillation
• Vcc = 5.0 V
• Low-speed on-chip oscillator: stop
• X IN: stop
• Output transistors “off”
• Low voltage detection circuit: enable 1.00.35 mA f(XIN) = 2 MHz (ceramic resonator)
• Vcc = 2.0 V
• High-speed on-chip oscillator: stop
• Low-speed on-chip oscillator: stop
• Output transistors “off”
• Low voltage detection circuit: enable Low-speed on-chip oscillator: oscillation
• Vcc = 2.0 V
• High-speed on-chip oscillator: stop
• X IN: stop
• Output transistors “off”
• Low voltage detection circuit: enable Low-speed mode 7025 µA 6023 µA 0.5 mA 1.00.1 Wait mode, functions except timer 1 disabled Wait mode, functions except timer 1 disabled f(XCIN)=32.768 kHz
• Vcc = 5.0 V
• High-speed on-chip oscillator: stop
• Low-speed on-chip oscillator: stop
• Output transistors “off”
• Low voltage detection circuit: enable f(XCIN) = 32.768 kHz
• Vcc = 2.0 V
• High-speed on-chip oscillator: stop
• Low-speed on-chip oscillator: stop
• Output transistors “off”
• Low voltage detection circuit: enable Low-speed mode 450190 µA 430150 µAWait mode, functions except timer 1 disabled Low-speed mode 6524 µA 5523 µAWait mode, functions except timer 1 disabled Low voltage detection circuit self consumption current Ta = 25 °C Vcc = 2.0 V Ta = 25 °C Vcc = 5.0 V µA µA Double-speed mode 600230 µA Low-speed mode 400120 µA 350105 µAWait mode, functions except timer 1 disabled Double-speed mode 106.0 mA Low-speed mode 6.02.6 mA 5.01.9 mAWait mode, functions except timer 1 disabled Double-speed mode 200100 µA Low-speed mode 18085 µA 17080 µAWait mode, functions except timer 1 disabled

Rev.2.00 Mar 15, 2007 Page 64 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. A/D Converter Characteristics A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) A/D Converter Recommended Operating Conditions (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTE: 1. When X CIN or the low-speed on-chip oscillator is selected as φSOURCE, the A/D converter cannot be used. Symbol Test conditions Limits Min. Typ. Max. Unit 10 bits kΩ55 Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor A/D port input current 5.0 µA tCONV RLADDER II(AD) tc(φSOURCE)122 tc(φSOURCE)61A/D conversion clock = f(φSOURCE) A/D conversion clock = f(φSOURCE)/2 LSBTa = −20−85 °C, 2.7 ≤ Vcc ≤ 5.5 V TBD Symbol Parameter Test conditions Limits Unit A/D conversion clock frequency (Note) φ(AD) MHz4.0 ≤ Vcc ≤ 5.5 V TBD 8 MHzTBD 42.7 ≤ Vcc < 4.0 V Power source voltage Ta = −20−85 °C Min. Typ. Max. 2.7 5.5 VVCC

Rev.2.00 Mar 15, 2007 Page 65 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Power-on reset circuit characteristics Power-on reset circuit characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTE: 1. V POR is the start voltage level of Vcc for the built-in power-on reset circuit to operate normally. Keep VPOR to be lower than the Vcc voltage before rising of the Vcc power source to use the built-in power-on reset circuit. Set the built-in low voltage detection circuit to be valid when the built-in power-on reset is used. Low voltage detection circuit characteristics Low voltage detection circuit characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTE: 1. V LVD is the start voltage level of Vcc for the built-in low voltage detection circuit to operate normally. If the Vcc power source becomes lower than VLVD, first set the Vcc voltage to be lower than VPOR. Next, according to the electrical characteristics of the power-on reset circuit, perform the rising of Vcc. Fig 82. Electrical characteristics of power-on r eset circuit and voltage drop detection circuit VPOR TW(VPOR) TW(VPOR-VDET) Valid start voltage of power-on reset circuit (Note) VPOR hold time Rising time of valid power source of power-on reset circuit Symbol Parameter Limits Unit Min. Typ. V s ms Max. 20TW(VPOR) > 10 s Test conditions VLVD TW(VLVD) TW(VLVD-VDET) VDET- V(VDET+- VDET-) TDET Valid start voltage of low voltage detection circuit (Note) VLVD hold time Rising time of valid power source of low voltage detection circuit Detection voltage of low voltage detection circuit Detection voltage Hysteresis (when hysteresis is valid) Detection time of low 5voltage detection circuit Symbol Parameter Limits Unit Min. 1.0 1.85 1.80 Typ. 1.95 1.95 0.10 V s s V V V µs Max. 2.05 2.10 TW(VLVD) > 10 s Ta = 0−50 °C Ta = −20−85 °C Ta = −20−85 °C Test conditions Vcc power source waveform VPOR 0 V TW(VPOR)T T(V PON-VDET) TDET TW(VLVD)T T(V LVD-VDET) NoteVDET+ VDET- Internal reset signal Power-on reset circuit characteristics Low voltage detection circuit characteristics VPOR Note: If schmitt of the voltage drop detection circuit is set to be invalid, system is released from reset at the timing of rising to power source voltage VDET-.

Rev.2.00 Mar 15, 2007 Page 66 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Timing Requirements Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTES: 1. As for CAP 0, it is the value when noise filter is not used. 2. In this time, bit 6 of the seri al I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTES: 1. As for CAP 0, it is the value when noise filter is not used. 2. In this time, bit 6 of the seri al I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width INT 0, INT1, CAP0 input “H” pulse width (Note 1) INT0, INT1, CAP0 input “L” pulse width (Note 1) Serial I/O clock input cycle time (Note 2) Serial I/O clock input “H” pulse width (Note 2) Serial I/O clock input “L” pulse width (Note 2) Serial I/O input set up time Serial I/O input hold time Symbol Parameter Limits Unit Min. 125 800 370 370 220 100 Typ. µs ns ns ns ns ns ns ns ns ns ns Max. tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tWH(INT0) tWL(INT0) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width INT 0, INT1, CAP0 input “H” pulse width (Note 1) INT0, INT1, CAP0 input “L” pulse width (Note 1) Serial I/O clock input cycle time (Note 2) Serial I/O clock input “H” pulse width (Note 2) Serial I/O clock input “L” pulse width (Note 2) Serial I/O input set up time Serial I/O input hold time Symbol Parameter Limits Unit Min. 250 100 100 230 230 2000 950 950 400 200 Typ. µs ns ns ns ns ns ns ns ns ns ns Max. tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tWH(INT0) tWL(INT0) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD)

Rev.2.00 Mar 15, 2007 Page 67 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Timing requirements (3) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTES: 1. As for CAP 0, it is the value when noise filter is not used. 2. In this time, bit 6 of the seri al I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width INT0, INT1, CAP0 input “H” pulse width (Note 1) INT0, INT1, CAP0 input “L” pulse width (Note 1) Serial I/O clock input cycle time (Note 2) Serial I/O clock input “H” pulse width (Note 2) Serial I/O clock input “L” pulse width (Note 2) Serial I/O input set up time Serial I/O input hold time Symbol Parameter Limits Unit Min. 500 200 200 460 460 4000 1900 1900 800 400 Typ. µs ns ns ns ns ns ns ns ns ns ns Max. tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tWH(INT0) tWL(INT0) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD)

Rev.2.00 Mar 15, 2007 Page 68 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Switching Characteristics Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTE: 1. Pin X OUT is excluded. Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTE: 1. Pin X OUT is excluded. Switching characteristics (3) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) NOTE: 1. Pin X OUT is excluded. Fig 83. Switching characteristics measurement circuit diagram tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tV(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Symbol Parameter Limits Unit Min. t C(SCLK)/2−30 tC(SCLK)/2−30 −30 Typ. ns ns ns ns ns ns ns ns Max. 140 tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tV(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Symbol Parameter Limits Unit Min. t C(SCLK)/2−50 tC(SCLK)/2−50 −30 Typ. ns ns ns ns ns ns ns ns Max. 350 tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tV(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Symbol Parameter Limits Unit Min. t C(SCLK)/2−70 tC(SCLK)/2−70 −30 Typ. ns ns ns ns ns ns ns ns Max. 450 Measured output pin 100 pF CMOS output

Rev.2.00 Mar 15, 2007 Page 69 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. Fig 84. Timing chart 0 . 2 VC C td(SCLK-TxD) tf 0.2VCC 0.8VCC 0 . 8 VC C tr tsu(RxD-SCLK)t h(SCLK-RxD) tv(SCLK-TxD) tC(SCLK) tWL(SCLK) tWH(SCLK) RXD (at receive) SCLK 0 . 2 VC C tWL(XIN) 0 . 8 VC C tWH(XIN) tC(XIN) XI N 0.2VCC 0.8VCC tW(RESET) R E S E T TXD (at transmit) 0 . 2 VC C tW L( I N T0) 0 . 8 VC C tW H( I N T0) INT0, INT1 CAP0

Rev.2.00 Mar 15, 2007 Page 70 of 70 REJ03B0210-0200 Notice: This is not a final specification. Some parametric limits are subject to change. PACKAGE OUTLINE y Index mark1 10 1120 F c bpe A D E HE INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. Detail F A1A2 L 0.320.220.17bp Previous CodeJEITA Package Code RENESAS Code PLSP0020JB-A 20P2F-A MASS[Typ.] 0.1gP-LSSOP20-4.4x6.5-0.65 0.20.150.13 MaxNomMin Dimension in Millimeters Symbol Reference 6.66.56.4D 4.54.44.3E 1.15A2 6.66.46.2 1.45A 0.20.10 0.70.50.3L 10°0° c 0.65e 0.10y HE 0.53 0.77

REVISION HISTORY 7548 Group Datasheet Rev. Date Description Page Summary

1.00 Dec 28, 2006 - First edition issued

1.01 Dec 28, 2006 1 Key-on wakeup is changed. 14 Fig.12 is revised. 19 Fig.16 is revised.

2.00 Mar 15, 2007 1

FEATURES: “• LED output port” → “• LED direct drive port” “• Built-in high-speed on-chip oscillator” → “High-speed on-chip oscillator” “• Built-in low-speed on-chip oscillator” → “Low-speed on-chip oscillator”

• Power dissipation; “TBD” → “30 mW”

4 Table 1: I/O port P0 0-P07; “LED direct drive ports” is added

A/D converter; “8 channel” → “× 8 channel” 6T a b l e 2 : P 0 3 “Capture function pin” → “Capture input pin” P10-P12 “Compare function pin” → “Compare output pin” P13 “Timer 2 function pin” → “Timer 2 output pin” P20, P21 “external oscillator pin” → “clock pins” 10 [CPU mode register]: Description is revised and moved from the page 12. 11 Function set ROM Area: Description is revised and moved from the page 47. <Notes>: (2) is added, (3) is revised

12 Fig 8 Note is deleted

14 Fig 10, Fig 11, Fig 12 is moved from the page 47. Fig 12 is revised 15 [Pull-up control registers]: Description revised Fig 13, Fig 14, Fig 15 is revised

16 Table 6 is revised

17, 18 Fig 17, Fig 18; Title is revised

19 Contents of Table 7 is added

21 Table 8: Key-on wakeup “P0”

→ “P1”

24 Timers, • Notes on Timers 1 and 2: Description is revised

26 Timer A (TA), • Notes on Timer A: Description is revised

27 Output compare: Contents of description added

Fig 30 “oscillator/512” → “oscillator/16”

31 Input capture: Contents of description added

32 Fig 40 “oscillator/512”

→ “oscillator/16” 37, 38 register name: “A/D” → “AD” 38 • Notes on A/D converter: (2) is added

39 Watchdog Timer is revised

Fig 51, Fig 54 is revised 40 • Notes on Watchdog Timer is revised

42 Fig 57 is revised

43 Clock Circuit is revised

44 Oscillation Control is added

47 Fig 63 is revised

48 Fig 64 is revised

REVISION HISTORY

REVISION HISTORY 7548 Group Datasheet

2.00 Mar 15, 2007 49 “oscillation stop” → “oscillation stop detection”

Fig 66 is revised, Note 4 is added

• Notes on Function Set ROM Data 2 is deleted

50 Table 10: P1 0 “ESDA input” → “ESDA I/O”, “Output” → “I/O”

53 (7) CPU Mode Register is revised

58 Overvoltage: Description revised, Fig 80 is added

59 ELECTRICAL CHARACTERISTICS is added

Rev. Date Description Page Summary

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