7547

7547 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 91

Technical content

DESCRIPTION

The 7547 Group is the QzROM version of 7542 Group. The 7547 Group has the pin-compatibilty with the 7542 Group. As new functions, the power-on reset, the low voltage detection cir- cuit, and the function set ROM are added.

FEATURES

(at 8 MHz oscillation frequency, double-speed mode for the shortest instruction)

• Memory size (low-power dissipation by an on-chip oscillator) (connected to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation)
• Power source voltage XIN oscillation frequency at ceramic oscillation, in double-speed mode X IN oscillation frequency at ceramic oscillation, in high-speed mode or middle-speed mode X IN oscillation frequency at RC oscillation in high-speed mode or middle-speed mode X Rev.1.21 Nov 15, 2006 page 1 of 89 REJ03B0156-0121

7547 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0156-0121 Rev.1.21 Nov 15, 2006

Rev.1.21 Nov 15, 2006 page 2 of 89 REJ03B0156-0121 PIN CONFIGURATION (TOP VIEW) Fig. 1 Pin configuration (Package type: PRSP0036GA-B) CNVSS XOUT XIN VSS P04(LED04)/RxD2 P30(LED10)/CAP1 Vcc VREF P05(LED05)/TxD2 P10/RXD1/CAP0 P26/AN6 P27/AN7 P11/TXD1P12/SCLK1 P13/SRDY1 P23/AN3 P22/AN2 P21/AN1 P20/AN0 P31(LED11)/CMP2 P36(LED16)/INT1 P24/AN4 P25/AN5 P06(LED06)/SCLK2 P07(LED07)/SRDY2 RESET M37547Gx-XXXFP M37547GxFP P14/CNTR0 P35(LED15) P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P37(LED17)/INT0 P00(LED00)/CAP0 P01(LED01)/CMP0 P02(LED02)/CMP1 P03(LED03)/TXOUT

Rev.1.21 Nov 15, 2006 page 3 of 89 REJ03B0156-0121 Table 1 Performance overview Parameter 0.25 µs (Minimum instruction, oscillation frequency 8 MHz: double-speed mode) 8 MHz (max.)

8 K to 16 K bytes

• 8-bit ✕ 3, 5-bit ✕ 1 18 sources, 16 vectors
• 8-bit ✕ 2, 16-bit ✕ 2 4 channel 2 channel 8-bit ✕ 2 (UART or clock synchronous) 10-bit ✕ 8 channel 16-bit ✕ 1 Built-in (external ceramic resonator or quartz-crystal oscillator, RC oscillation available) (Low consumption current by on-chip oscillator available) 4.5 to 5.5 V 4.0 to 5.5 V 2.4 to 5.5 V 2.2 to 5.5 V 4.0 to 5.5 V 2.4 to 5.5 V 2.2 to 5.5 V 4.0 to 5.5 V 2.4 to 5.5 V 2.2 to 5.5 V 1.8 to 5.5 V 29.5 mW (Typ.) -20 to 85 °C CMOS sillicon gate 36-pin plastic molded SSOP Number of basic instructions Instruction execution time Oscillation frequency Memory sizes ROM RAM I/O port P0, P1, P2, P3 Interrupts Timer Output compare Input capture Serial interface A/D converter Watchdog timer Clock generating circuit Power source Double-speed mode At 8MHz oscillation voltage At 6.5MHz oscillation (at ceramic At 2MHz oscillation resonance) At 1MHz oscillation High-speed mode At 8MHz oscillation Middle-speed mode At 4MHz oscillation At 2MHz oscillation Power source High-speed mode At 4MHz oscillation voltage Middle-speed mode At 2MHz oscillation (at RC oscillation) At 1MHz oscillation Power source voltage (at on-chip oscillation) Power dissipation Operating temperature range Device structure Package Function

Rev.1.21 Nov 15, 2006 page 4 of 89 REJ03B0156-0121 Fig. 2 Functional block diagram (Package type: PRSP0036GA-B) X IN OUT X SI/O2(8) RAM ROM CPU A X Y S PC H PC L PS V SS18 RESET V CC15 CNV SS P1(5) P2(8) P3(8) 24 22 Reset input I/O port P2 I/O port P1 I/O port P3 Clock generating circuit Clock input Clock output A/Dconverter (10) V REF INT SI/O1(8) CNTR I/O port P0 Timer X (8) Key-on wakeup Prescaler X (8) Timer B (16) P0(8) 32 30 Timer 1 (8) Prescaler 1 (8) Timer A (16) INT InputCapture OutputCompare Watchdog timer Reset Low voltagedetection circuit Reset Power-on reset circuit Reset FUNCTIONAL BLOCK DIAGRAM (Package type: PRSP0036GA-B) [7547 Group]

Rev.1.21 Nov 15, 2006 page 5 of 89 REJ03B0156-0121 Apply voltage of 1.8 to 5.5 V to Vcc, and 0 V to Vss.

• Reference voltage input pin for A/D converter.
• Chip operating mode control pin, which is always connected to Vss.
• Reset input pin for active “L”
• Input and output pins for main clock generating circuit.
• Connect a ceramic resonator or quartz crystal oscillator between the X IN and XOUT pins.
• For using RC oscillator, short between the X IN and XOUT pins, and connect the capacitor and resistor.
• If an external clock is used, connect the clock source to the X IN pin and leave the X OUT pin open.
• When the on-chip oscillator is selected as the main clock, connect X IN pin to VCC and leave X OUT open. Function expect a port functionName Power source Analog refer- ence voltage CNVss Reset input Clock input I/O port P0 I/O port P1 I/O port P2 I/O port P3 Pin Vcc, Vss V REF CNVss RESET X IN P00(LED00)/CAP0 P01(LED01)/CMP0 P02(LED02)/CMP1 P03(LED03)/TXOUT P04(LED04)/RxD2 P05(LED05)/TxD2 P06(LED06)/SCLK2 P07(LED07)/SRDY2 P10/RxD1/CAP0 P11/TxD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0–P27/AN7 P30(LED10)/CAP1 P31(LED11)/CMP2 P32(LED12)/CMP3 P33(LED13)/INT1 P34(LED14) P35(LED15) P36(LED16)/INT1 P37(LED17)/INT0
• Capture function pin
• Compare function pin
• Timer X function pin
• Serial I/O2 function pin
• Serial I/O1 function pin
• Capture function pin
• Serial I/O1 function pin
• Timer X function pin
• Input pins for A/D converter
• Capture function pin
• Compare function pin
• Interrupt input pin
• Interrupt input pin
• 8-bit I/O port.
• I/O direction register allows each pin to be individually pro- grammed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Whether a built-in pull-up resistor is to be used or not can be determined by program.
• High drive capacity for LED drive port can be selected by program.
• 5-bit I/O port
• I/O direction register allows each pin to be individually pro- grammed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• CMOS/TTL level can be switched for P1 0, P12 and P13
• 8-bit I/O port having almost the same function as P0
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit I/O port
• I/O direction register allows each pin to be individually pro- grammed as either input or output.
• CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37).
• CMOS 3-state output structure
• Whether a built-in pull-up resistor is to be used or not can be determined by program.
• High drive capacity for LED drive port can be selected by program. XOUT Clock output
• Key-input (key-on wake up interrupt input) pin

Rev.1.21 Nov 15, 2006 page 6 of 89 REJ03B0156-0121 GROUP EXPANSION Renesas plans to expand the 7547 Group as follow: Memory type Support for QzROM Memory size Package Fig. 3 Memory expansion plan 384 512 16K M37547G4 8K M37547G2 ROM size (bytes) RAM size (bytes) Note: Products under development...the development schedule and specification may be revised without notice. **: Under development Currently supported products are listed below. Table 3 List of supported products RAM size (bytes) Shipped after writing Shipped in blank Shipped after writing Shipped in blank M37547G2-XXXFP M37547G2FP M37547G4-XXXFP M37547G4FP Product ROM size (bytes) ROM size for User ( ) 384 512 RemarksPackage PRSP0036GA-B PRSP0036GA-B PRSP0036GA-B PRSP0036GA-B 8192 (Note) (8062) 16384 (Note) (16254) Note : ROM size includes the function set ROM.

Rev.1.21 Nov 15, 2006 page 7 of 89 REJ03B0156-0121 X b7 b0 S b7 b0 Y b7 b0 PCL Processor Status Register (PS) Carry Flag b7 b0 b7 b0 A b15 PCH Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Program Counter Stack Pointer Index Register Y Index Register X AccumulatorCZIDBTVN FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 <SOFTWARE> USER ’S MANUAL for details on each instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions cannot be used. 2. The MUL and DIV instructions can be used. 3. The WIT instruction can be used. 4. The STP instruction can be used. Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to “1”, the value contained in index register X becomes the address for the second OPERAND. Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack ad- dress are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcom- puter types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing reg- ister contents onto the stack and popping them from the stack are shown in Fig. 5. Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PC L. It is used to indicate the address of the next instruction to be executed. Fig. 4 740 Family CPU register structure

Rev.1.21 Nov 15, 2006 page 8 of 89 REJ03B0156-0121 Execute JSR On-going Routine M (S) (PC H) (S) (S – 1) M (S) (PC L) Execute RTS (PCL) M (S) (S) (S – 1) (S) (S + 1) (S) (S + 1) (PCH) M (S) Subroutine Restore Return Address Store Return Address on Stack M (S) (PS) Execute RTI (PS) M (S) (S) (S – 1) (S) (S + 1) Interrupt Service Routine Restore Contents of Processor Status Register M (S) (PC H) (S) (S – 1) M (S) (PC L) (S) (S – 1) (PCL) M (S) (S) (S + 1) (S) (S + 1) (PCH) M (S) Restore Return Address I Flag “0” to “1” Fetch the Jump Vector Store Return Address on Stack Store Contents of Processor Status Register on Stack Interrupt request (Note) Note : The condition to enable the interrupt Interrupt enable bit is “1” Interrupt disable flag is “0” Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 5 Register push and pop at interrupt generation and subroutine call

Rev.1.21 Nov 15, 2006 page 9 of 89 REJ03B0156-0121 Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. When an interrupt occurs, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are ex- ecuted in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was gener- ated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed be- tween accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations and direct data trans- fers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory lo- cation 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal ad- dressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location oper- ated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

Rev.1.21 Nov 15, 2006 page 10 of 89 REJ03B0156-0121 Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 0000 16 to 00FF 16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF00 16 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 6 Memory map diagram ROM capacity (bytes) address YYYY16 address ZZZZ16

8192 E000 16 E08016

16384 C000 16 C08016

Function set ROM function area 010016 000016 004016 044016 XXXX16 RAM Reserved area SFR area Not used RAM area RAM capacity (bytes) address XXXX16 512 023F16 384 01BF 16 Function set ROM consists of the followings: - Function set ROM data to set peripheral functions to be active immediately after system is released from reset, - ROM code protect to disable the reading of the built-in PROM area by serial programmer, - Renesas shipment test area where random data are written in when shipment test is performed by Renesas. ROM area Reserved ROM area (128 bytes) Interrupt vector area Reserved ROM area Zero page Special page Address FFD416 FFD516 FFD616 Renesas shipment test are Renesas shipment test area Renesas shipment test area Renesas shipment test area a FFD716 FFD816 FFD916 FFDA16 FFDB16 Function set ROM data 2 Function set ROM data 1 Function set ROM data 0 ROM code protect ROM Code Protect Address (address FFDB16) Address FFDB 16, which is the reserved ROM area of QzROM, is the ROM code protect address. “0016” is written into this address when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp.. When “0016” is set to the ROM code protect ad- dress, the protect function is enabled, so that reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial pro- grammer. As for the QzROM product shipped after writing, “00 16” (protect enabled) or “FF16” (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing. The writing of “00 16” or “FF16” can be selected as the ROM option setup (referred to as “Mask option setup ” in MM) when ordering. I Notes Because the contents of RAM are indefinite at reset, set initial val- ues before using.

Rev.1.21 Nov 15, 2006 page 11 of 89 REJ03B0156-0121 Fig. 8 Switching method of CPU mode register Fig. 7 Structure of CPU mode register Oscillation mode selection bit (Note 1, Note 4) 0 : Ceramic oscillation 1 : RC oscillation CPU mode register (Note 1) (CPUM: address 003B 16, initial value: 8016) Stack page selection bit 0 : 0 page 1 : 1 page Clock division ratio selection bits b7 b6 0 0 : f(φ) = f(X IN)/2 (High-speed mode) 0 1 : f(φ) = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f(φ) = f(XIN)/1 (Double-speed mode)(Note 5) On-chip oscillator oscillation control bit (Note 3) 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop X IN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Processor mode bits b1 b0 0 0 Single-chip mode 0 1 Not available 1 0 Not available 1 1 Not available Note 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed after releasing reset since bit 5 of CPUM is fixed. 2: The setting values of FSROM2 become valid by setting “0” to bit 0 of function set ROM data 0 (FSROM0). The setting values of FSROM2 are invalid by setting “1” to this bit. (In order that FSROM2 is invalid, write to CPUM after releasing reset.) 3: When bit 4 of FSROM2 is set to “0”, the operation of on-chip oscillator cannot be stopped. Since the on-chip oscillator is not stopped also in the stop mode, the dissipation current in the stop mode is increased. 4: The setting value of bit 5 of CPUM can be fixed after releasing reset by setting value of bit 5 of FSROM2. Also, when the setting of FSROM2 is invalid, this bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. This bit is initialized by reset, and then, rewriting it is enabled. 5: This setting can be used only at ceramic oscillation. Do not use this at RC oscillation. b7 b0 Control by Function set ROM data 2 (FSROM2: address FFDA16) (Note 2) This bit function can be set by setting bit 5 of FSROM2. (Note 4) Bit 5 of FSROM2 = 0: Bit 5 of CPUM is fixed to “0”. Bit 5 of FSROM2 = 1: Bit 5 of CPUM is “0” or “1”. This cannot be controlled by FSROM2. This cannot be controlled by FSROM2. This bit function can be set by setting bit 4 of FSROM2. (Note 3) Bit 4 of FSROM2 = 0: Bit 3 of CPUM is fixed to “0”. Bit 4 of FSROM2 = 1: Bit 3 of CPUM is “0” or “1”. This cannot be controlled by FSROM2. This cannot be controlled by FSROM2. After releasing reset Switch the oscillation mode selection bit (bit 5 of CPUM) Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Main routine Start with an on-chip oscillator An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts. Select 1/1, 1/2, 1/8 or on-chip oscillator. Wait by on-chip oscillator operation until establishment of oscillator clock When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). Note: After system is released from reset, an on-chip oscillator turns active automatically and system operation is started. Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program af- ter releasing Reset in the following method. [CPU mode register] CPUM The CPU mode register contains the stack page selection bit, etc.. This register is allocated at address 003B 16. Some function of the CPU mode register can be controlled by the function set ROM data 2.

Rev.1.21 Nov 15, 2006 page 12 of 89 REJ03B0156-0121 Fig. 9 Memory map of special function register (SFR) Notes 1: Do not access to the SFR area including nothing. 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Pull-up control register (PULL) Transmit 1 /Receive 1 buffer register (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator 1 (BRG1) Port P1P3 control register (P1P3C) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Timer count source set register (TCSS) A/D conversion register (low-order) (ADL) Prescaler 1 (PRE1) Timer 1 (T1) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Serial I/O2 control register (SIO2CON) UART2 control register (UART2CON) A/D control register (ADCON) A/D conversion register (high-order) (ADH) MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1) Timer A, B mode register (TABM) Capture/compare port register (CCPR) Timer source selection register (TMSR) Capture mode register (CAPM) Compare output mode register (CMOM) Capture/compare status register (CCSR) Compare interrupt source set register (CISR) Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2) On-chip oscillation division ratio selection register (RODR) Baud rate generator 2 (BRG2) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Timer B (low-order) (TBL) Timer B (high-order) (TBH) Transmit 2 / Receive 2 buffer register (TB2/RB2) Serial I/O2 status register (SIO2STS) Port P0P3 drive capacity control register (DCCR) Compare register re-load register (CMPR) Capture software trigger register (CSTR) Capture/compare register R/W pointer (CCRP) Compare register (high-order) (CMPH) Compare register (low-order) (CMPL) Capture register 1 (high-order) (CAP1H) Capture register 1 (low-order) (CAP1L) Capture register 0 (high-order) (CAP0H) Capture register 0 (low-order) (CAP0L) Interrupt source set register (INTSET) Interrupt source discrimination register (INTDIS) Reserved Reserved Reserved

Rev.1.21 Nov 15, 2006 page 13 of 89 REJ03B0156-0121 [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corre- sponds to one pin, and each pin can be set to be input or output. When “1” is set to the bit corresponding to a pin, this pin becomes an output port. When “0” is set to the bit, the pin becomes an in- put port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are float- ing, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. [Port P0P3 drive capacity control register] DCCR By setting the Port P0P3 drive capacity control register (address 0015 16), the drive capacity of the N-channel output transistor for the port P0 and port P3 can be selected. [Pull-up control register] PULL By setting the pull-up control register (address 0016 16), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. [Port P1P3 control register] P1P3C By setting the port P1P3 control register (address 0017 16), a CMOS input level or a TTL input level can be selected for ports 0, P12, P13, P36, and P37 by program. Fig. 12 Structure of port P1P3 control register Fig. 11 Structure of pull-up control register Port P1P3 control register (P1P3C: address 001716, initial value: 0016) b7 b0 Not used 1 : TTL level 0 : CMOS level P10,P12,P13 input level selection bit 1 : TTL level 0 : CMOS level P36/INT1 input level selection bit 1 : TTL level 0 : CMOS level P37/INT0 input level selection bit P u l l - u p c o n t r o l r e g i s t e r P U L L a d d r e s s i n i t i a l v a l u e P00 pull-up control bit P01, P02 pull-up control bit P03–P07 pull-up control bit P30 pull-up control bit P31, P32 pull-up control bit P33 pull-up control bit P34, P35 pull-up control bit P36, P37 pull-up control bit b 7 b 0 0 : P u l l - u p O f f P u l l u p O n N o t e : P i n s s e t t o o u t p u t p o r t s a r e d i s c o n n e c t e d f r o m p u l l - u p c o n t r o l . Port P0P3 drive capacity control register (DCCR: address 001516, initial value: 0016) P o r t P 00 d r i v e c a p a c i t y b i t P o r t s P 01, P d r i v e c a p a c i t y b i t P o r t s P 03–P 07 d r i v e c a p a c i t y b i t P o r t P 30 d r i v e c a p a c i t y b i t P o r t s P 31, P 32 d r i v e c a p a c i t y b i t P o r t P 33 d r i v e c a p a c i t y b i t P o r t s P 34, P 35 d r i v e c a p a c i t y b i t P o r t s P 36, P d r i v e c a p a c i t y b i t b 7 b 0 0 : L o w H i g h N o t e N u m b e r o f L E D d r i v e p o r t d r i v e c a p a c i t y i s H I G H i s p o r t Fig. 10 Structure of port P0P3 drive capacity control register

Rev.1.21 Nov 15, 2006 page 14 of 89 REJ03B0156-0121 Table 6 I/O port function table Pin P00(LED00)/CAP0 P01(LED01)/CMP0 P02(LED02)/CMP1 P03(LED03)/TXOUT P04(LED04)/RxD2 P05(LED05)/TxD2 P06(LED06)/SCLK2 P07(LED07)/SRDY2 P10/RxD1/CAP0 P11/TxD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0–P27/AN7 P30(LED10)/CAP1 P31(LED11)/CMP2 P32(LED12)/CMP3 P33(LED13)/INT1 P34(LED14) P35(LED15) P36(LED16)/INT1 P37(LED17)/INT0 I/O format

• CMOS compatible input level (Note 1)
• CMOS 3-state output Non-port function
• Capture function input
• Key input interrupt
• Compare function output
• Key input interrupt
• Timer X function output
• Key input interrupt
• Serial I/O2 function input/output
• Key input interrupt
• Serial I/O1 function input
• Capture function input
• Serial I/O1 function input/output
• Timer X function input/output
• External interrupt input
• A/D conversion input
• Capture function input
• Compare function output
• External interrupt input
• External interrupt input SFRs related each pin Capture/Compare port register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Capture/Compare port register Pull-up control register Port P0P3 drive capacity control register Timer X mode register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Pull-up control register Port P0P3 drive capacity control register Serial I/O1 control register Capture/Compare port register Port P1P3 control register Serial I/O1 control register Serial I/O1 control register Port P1P3 control register Serial I/O1 control register Port P1P3 control register Timer X mode register A/D control register Capture/Compare port register Pull-up control register Port P0P3 drive capacity control register Capture/Compare port register Pull-up control register Port P0P3 drive capacity control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Pull-up control register Port P0P3 drive capacity control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Port P1P3 control register Diagram No. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level. Name I/O port P0 I/O port P1 I/O port P2 I/O port P3

Rev.1.21 Nov 15, 2006 page 15 of 89 REJ03B0156-0121 Fig. 13 Block diagram of ports (1) (1) Port P00 Direction register Data bus Port latch Pull-up control To key input interrupt generating circuit Capture 0 input P00 key-on wakeup selection bit Drive capacity control Capture 0 input control (2) Ports P01, P02 Compare output Direction register Data bus Port latch Pull-up control To key input interrupt generating circuit Compare output control Drive capacity control (3) Port P03 Timer output Direction register Data bus Port latch Pull-up control To key input interrupt generating circuit P03/TXOUT output valid Drive capacity control (4) Port P04 Serial I/O2 input Direction register Data bus Port latch Pull-up control To key input interrupt generating circuit Serial I/O2 enable bit Drive capacity control P04 key-on wakeup selection bit Receive enable bit (5) Port P05 Serial I/O2 output Direction register Data bus Port latch Pull-up control To key input interrupt generating circuit Serial I/O2 enable bit Drive capacity control Transmit enable bit (6) Port P06 Serial I/O2 clock output Direction register Data bus Port latch Pull-up control To key input interrupt generating circuit Serial I/O2 mode selection bit Drive capacity control Serial I/O2 enable bit Serial I/O2 synchronous clock selection bit Serial I/O2 clock input P06 key-on wakeup selection bit Serial I/O2 enable bit (7) Port P07 Serial I/O2 ready output Direction register Data bus Port latch Pull-up control To key input interrupt generating circuit Serial I/O2 mode selection bit Serial I/O2 enable bit SRDY2 output enable bit Drive capacity control

Rev.1.21 Nov 15, 2006 page 16 of 89 REJ03B0156-0121 Fig. 14 Block diagram of ports (2) (8) Port P10 Direction register Data bus Port latch Serial I/O1 enable bit Receive enable bit Serial I/O1 input Capture 0 input control P10, P12, P13 input level selection bit Capture 0 input P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. (9) Port P11 Data bus Port latch Serial I/O1 output P11/TxD1 P-channel output disable bit Direction register Serial I/O1 enable bit Transmit enable bit (10) Port P12 Serial I/O1 clock output Serial I/O1 mode selection bit Serial I/O1 enable bit Serial I/O1 enable bit Serial I/O1 synchronous clock selection bit Direction register Data bus Port latch Serial I/O1 clock input 0, P12, P13 input level selection bit* (12) Port P14 Data bus Serial I/O1 ready output Port latch Direction register CNTR0 interrupt input Timer output P10, P12, P13 input level selection bit Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Data bus Port latch Direction register (11) Port P13 Data bus Port latch Direction register A/D converter input Analog input pin selection bit (13) Ports P20–P27 Pulse output mode

Rev.1.21 Nov 15, 2006 page 17 of 89 REJ03B0156-0121 Fig. 15 Block diagram of ports (3) (14) Port P30 Direction register Data bus Port latch Pull-up control Capture 1 input Drive capacity control Capture 1 input control (15) Ports P31, P32 Compare output Direction register Data bus Port latch Pull-up controlCompare output control Drive capacity control (16) Port P33 Direction register Data bus Port latch Pull-up control INT1 input control Drive capacity control INT1 input (17) Ports P34, P35 Direction register Data bus Port latch Pull-up control Drive capacity control (19) Port P37 Direction register Data bus Port latch Pull-up control Drive capacity control INT0 input P3 input level selection bit P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. *When the TTL level is selected, there is no hysteresis characteristics. (18) Port P36 Direction register Data bus Port latch Pull-up control Drive capacity control INT1 input P3 input level selection bit INT1 input control

Rev.1.21 Nov 15, 2006 page 18 of 89 REJ03B0156-0121 Termination of unused pins

• Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. Output ports: Open. Pin P00/CAP0 P01/CMP0 P02/CMP1 P03/TXOUT P04/RxD2 P05/TxD2 P06/SCLK2 P07/SRDY2 P10/RxD1/CAP0 P11/TxD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0–P27/AN7 P30/CAP1 P31/CMP2 P32/CMP3 P33/INT1 P34 P35 P36/INT1 P37/INT0 VREF Termination 1 (recommend) I/O port Connect to Vss. Termination 2 When selecting CAP function, per- form termination of input port. When selecting CMP 0 function, perform termination of output port. When selecting CMP 1 function, perform termination of output port. When selecting TX OUT function, perform termination of output port. When selecting RxD 2 function, perform termination of input port. When selecting TxD 2 function, perform termination of output port. When selecting external clock input, perform termination of output port. When selecting S RDY2 function, perform termination of output port. When selecting RxD 1 function, perform termination of input port. When selecting TxD 1 function, perform termination of output port. When selecting external clock input, perform termination of input port. When selecting S RDY1 function, perform termination of output port. When selecting CNTR input function, perform termination of input port. When selecting AN function, per- form termination of input port. When selecting CAP function, per- form termination of input port. When selecting CMP 2 function, perform termination of output port. When selecting CMP 3 function, perform termination of output port. When selecting INT function, per- form termination of input port. When selecting INT function, per- form termination of input port. When selecting INT function, per- form termination of input port. Termination 3 When selecting internal clock output, perform termination of output port. When selecting CAP function, per- form termination of input port. When selecting internal clock output, perform termination of output port. When selecting CNTR output function, perform termination of output port. Termination 4 When selecting key-on wakeup function, perform termination of input port. Table 7 Termination of unused pins Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). We recommend processing unused pins through a resistor which can secure I OH(avg) or IOL(avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc.

Rev.1.21 Nov 15, 2006 page 19 of 89 REJ03B0156-0121 Interrupts occur by 18 different sources : 6 external sources, 11 in- ternal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the in- terrupt request bit are set to “1” and the interrupt disable flag is set to “0”, an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt operation Upon acceptance of an interrupt the following operations are auto- matically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. [Interrupt source set register] INTSET When two interrupt sources are assigned to the same interrupt vector, the valid/invalid of each interrupt is set by this register. When both two interrupt sources are set to be valid, which inter- rupt request occurs is confirmed by the next interrupt source discrimination register. [Interrupt source discrimination register] INTDIS When two interrupt sources are assigned to the same interrupt vector, which interrupt source occurs is confirmed by this register. If an interrupt request of a key-on wakeup, UART1 bus collision detection, A/D conversion or timer 1 occurs, an interrupt discrimi- nation bit is set to “1” regardless of valid/invalid state by the interrupt source set register. However, when the interrupt valid bit of an interrupt source set register is “0” (invalid), the interrupt request bit of an interrupt con- trol register is not set to “1.” Moreover, since an interrupt discrimination bit is not automatically cleared to “0” by interrupt, please clear it by program. An interrupt discrimination bit can be cleared to “0” by program but not be set to “1.” [Interrupt edge selection register] INTEDGE The valid edge of external interrupt INT 0 and INT1 can be selected by the interrupt edge selection bit, respectively. For the external interrupt INT 1, the external input pin P3 3/INT1 or P36/INT1 can be selected by the INT 1 input port selection bit. By the key-on wakeup selection bit, enable/disable of a key-on wakeup of P00, P04, and P06 pins can be selected, respectively. I Notes on use (1) When setting the followings, the interrupt request bit may be set to “1”.

• When switching external interrupt active edge Related register: Interrupt edge selection register (address 003A 16) Timer X mode register (address 002B 16) Capture mode register (address 0020 16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (active edge switch bit, trigger mode bit). ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). (2) Use a LDM instruction to clear an interrupt discrimination bit. LDM #$0n, $0B Set the following values to “n” “0”: an interrupt discrimination bit to clear “1”: other interrupt discrimination bits Ex.) When a key-on wakeup interrupt discrimination bit is cleared; LDM #00001110B and $0B.

Rev.1.21 Nov 15, 2006 page 20 of 89 REJ03B0156-0121 Table 8 Interrupt vector address and priority Vector addresses (Note 1) High-order Priority Low-order Interrupt request generating conditions RemarksInterrupt source FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: Key-on wakeup interrupt and UART1 bus collision detection interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are discriminated by interrupt source discrimination register. 4: A/D conversion interrupt and Timer 1 interrupt can be enabled by setting of interrupt source set register. The occurrence of t hese interrupts are dis- criminated by interrupt source discrimination register. Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected Valid only when serial I/O2 is selected Valid only when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling, when key-on wakeup interrupt is enabled) When UART1 bus collision detection interrupt is enabled. External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Compare interrupt source is selected. When A/D conversion interrupt is enabled. STP release timer underflow (When Timer 1 interrupt is enabled) Non-maskable software interrupt At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At completion of serial I/O2 data receive At completion of serial I/O2 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT 0 input At detection of either rising or falling edge of INT 1 input At falling of conjunction of input logical level for port P0 (at input) At detection of UART1 bus collision detection At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of Capture 0 input At detection of either rising or falling edge of Capture 1 input At compare matched At timer X underflow At timer A underflow At timer B underflow At completion of A/D conversion At timer 1 underflow At BRK instruction execution Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit Serial I/O2 receive Serial I/O2 transmit INT0 INT1 Key-on wake-up/ UART1 bus collision detection (Note 3) CNTR Capture 0 Capture 1 Compare Timer X Timer A Timer B A/D conversion/ Timer 1 (Note 4) BRK instruction

Rev.1.21 Nov 15, 2006 page 21 of 89 REJ03B0156-0121 Fig. 16 Interrupt control Interrupt disable flag I Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset Timer 1 interrupt request Timer 1 interrupt valid bit A/D conversion interrupt request A/D conversion interrupt valid bit A/D conversion interrupt discrimination bit Timer 1 interrupt discrimination bit A/D conversion/ Timer 1 interrupt request bit UART1 bus collision detection interrupt request UART1 bus collision detection interrupt valid bit Key-on wakeup interrupt request Key-on wakeup interrupt valid bit Key-on wakeup interrupt discrimination bit UART1 bus collision detection interrupt discrimination bit Key-on wakeup/ UART1 bus collision detection interrupt request bit Note: For key-on wakeup, UART1 bus collision detection, A/D conversion and Timer 1 interrupt, even if interrupt valid bit (000A 16) is set “0: Invalid”, interrupt discrimination bit (000B 16) is set to “1: interrupt occurs ” when corresponding interrupt request occurs. But corresponding interrupt request bit (003C 16, 003D16) is not set to “1”.

Rev.1.21 Nov 15, 2006 page 22 of 89 REJ03B0156-0121 b7 b0 Interrupt control register 1 Serial I/O1 receive interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled (ICON1 : address 003E16, initial value : 0016) b7 b0 Interrupt control register 2 Capture 0 interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16, initial value : 0016) Interrupt request register 2 0 : No interrupt request issued 1 : Interrupt request issued (IREQ2 : address 003D16, initial value : 0016) b7 b0 Capture 0 interrupt request bit Interrupt request register 1 Serial I/O1 receive interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C16, initial value : 0016) b7 b0 Not used (returns “0” when read) (Do not write “1” to this bit) A/D conversion/Timer 1 interrupt enable bit Timer B interrupt enable bit Timer A interrupt enable bit Timer X interrupt enable bit Compare interrupt enable bit Capture 1 interrupt enable bit CNTR0 interrupt enable bit Key-on wake up/UART1 bus collision detection interrupt enable bit INT1 interrupt enable bit INT0 interrupt enable bit Serial I/O2 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) A/D conversion/Timer 1 interrupt request bit Timer B interrupt request bit Timer A interrupt request bit Timer X interrupt request bit Compare interrupt request bit Capture 1 interrupt request bit CNTR 0 interrupt request bit Key-on wake up/UART1 bus collision detection interrupt request bit INT1 interrupt request bit INT0 interrupt request bit Serial I/O2 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O1 transmit interrupt request bit Interrupt source set register (INTSET: address 000A16, initial value: 0016) Key-on wakeup interrupt valid bit b7 b0 Interrupt source discrimination register (INTDIS: address 000B16, initial value: 0016) Key-on wakeup interrupt discrimination bit b7 b0 Interrupt edge selection register (INTEDGE : address 003A16, initial value: 0016) b7 b0 Not used (returns “0” when read) Timer 1 interrupt valid bit A/D conversion interrupt valid bit UART1 bus collision detection interrupt valid bit 1: Interrupt valid 0: Interrupt invalid 1: Interrupt occurs 0: Interrupt does not occur Not used (returns “0” when read) Timer 1 interrupt discrimination bit A/D conversion interrupt discrimination bit UART1 bus collision detection interrupt discrimination bit INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 input port selection bit 0 : P36 1 : P33 Not used (returns “0” when read) P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled P04 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled P06 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled Fig. 17 Structure of Interrupt-related registers

Rev.1.21 Nov 15, 2006 page 23 of 89 REJ03B0156-0121 Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P0 0 to P03 as input ports. Fig. 18 Connection example when using key input interrupt and port P0 block diagram Port PXx “L” level output PULL register bit 3 = “0” Port P07 latch Port P07 Direction register = “1” *** P07 output Key input interrupt request Port P0 Input read circuit * P-channel transistor for pull-up CMOS out put buffer PULL register bit 3 = “0” Port P0 latch Port P06 Direction register = “1” * P06 output PULL register bit 3 = “0” Port P05 latch Port P05 Direction register = “1” * P05 output PULL register bit 3 = “0” Port P04 latch Port P04 Direction register = “1” * P04 output PULL register bit 2 = “1” Port P03 latch Port P03 Direction register = “0” * P03 input PULL register bit 2 = “1” Port P02 latch Port P02 Direction register = “0” * P02 input PULL register bit 1 = “1” Port P01 latch Port P01 Direction register = “0” * P01 input PULL register bit 0 = “1” Port P00 latch Port P00 Direction register = “0” * P00 input Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Port P00 key-on wakeup selection bit Port P06 key-on wakeup selection bit Port P04 key-on wakeup selection bit

Rev.1.21 Nov 15, 2006 page 24 of 89 REJ03B0156-0121 Timers The 7547 Group has 4 timers: timer 1, timer X, timer A and timer The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches “0”, an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”.

• Frequency divider for timer According to the clock division selection bits (b7 and b6) of CPU mode register (003B 16), the count source of frequency divider is set as follows; b7b6 = “00”(high-speed), “01”(middle-speed), “11”(double-speed): X IN b7b6 = “10”(On-chip oscillator): On-chip oscillator G Timer 1 Timer 1 is an 8-bit timer and counts the prescaler output. When Timer 1 underflows, the timer 1 interrupt request bit is set to “1”. Prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. The value of prescaler 1 latch is set to Prescaler 1 when Prescaler 1 underflows. The value of timer 1 latch is set to Timer 1 when Timer 1 underflows. When writing to Prescaler 1 (PRE1) is executed, the value is writ- ten to both the prescaler 1 latch and Prescaler 1. When writing to Timer 1 (T1) is executed, the value is written to both the timer 1 latch and Timer 1. When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex- ecuted, each count value is read out. Timer 1 always operates in the timer mode. Prescaler 1 counts the signal which is the oscillation frequency di- vided by 16. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach “00 16”, an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count contin- ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the under- flow signal of Prescaler 1 is input. When the contents of Timer 1 reach “00 16”, an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The di- vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is 1/((n+1) ✕ (m+1)) provided that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software. G Timer X Timer X is an 8-bit timer and counts the prescaler X output. When Timer X underflows, the timer X interrupt request bit is set to “1”. Prescaler X is an 8-bit prescaler and counts the signal selected by the timer X count source selection bit. Prescaler X and Timer X have the prescaler X latch and the timer X latch to retain the reload value, respectively. The value of prescaler X latch is set to Prescaler X when Prescaler X underflows.The value of timer X latch is set to Timer X when Timer X underflows. When writing to Prescaler X (PREX) is executed, the value is writ- ten to both the prescaler X latch and Prescaler X. When writing to Timer X (TX) is executed, the value is written to both the timer X latch and Timer X. When reading from Prescaler X (PREX) and Timer X (TX) is ex- ecuted, each count value is read out. Timer X can be selected in one of 4 operating modes by setting the timer X operating mode bits of the timer X mode register. (1) Timer mode Prescaler X counts the count source selected by the timer X count source selection bits. Each time the count clock is input, the con- tents of Prescaler X is decremented by 1. When the contents of Prescaler X reach “00 16”, an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) pro- vided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the under- flow signal of Prescaler X is input. When the contents of Timer X reach “00 16”, an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The di- vision ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is 1/((n+1) ✕ (m+1)) provided that the value of Prescaler X is n and the value of Timer X is m. (2) Pulse output mode In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the CNTR 0 pin. The output level of CNTR 0 pin can be selected by the CNTR 0 ac- tive edge switch bit. When the CNTR 0 active edge switch bit is “0”, the output of CNTR 0 pin is started at “H” level. When this bit is “1”, the output is started at “L” level. Also, the inverted waveform of pulse output from CNTR 0 pin can be output from TX OUT pin by setting “1” to the P0 3/TXOUT output valid bit. When using a timer in this mode, set the port P1 4 and P0 3 direc- tion registers to output mode. (3) Event counter mode The timer A counts signals input from the P1 4/CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR 0 pin input signal can be selected from rising or falling by the CNTR 0 active edge switch bit .

Rev.1.21 Nov 15, 2006 page 25 of 89 REJ03B0156-0121 (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the sig- nal input to P1 4/CNTR0 pin is measured. The operation of Timer X can be controlled by the level of the sig- nal input from the CNTR 0 pin. When the CNTR0 active edge switch bit is “0”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR 0 pin is “H”. The count is stopped while the pin is “L”. Also, when the CNTR 0 active edge switch bit is “1”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR 0 pin is “L”. The count is stopped while the pin is “H”. Timer X can stop counting by setting “1” to the timer X count stop bit in any mode. Also, when Timer X underflows, the timer X interrupt request bit is set to “1”. Note on Timer X is described below; I Note on Timer X (1) CNTR 0 interrupt active edge selection-1 CNTR0 interrupt active edge depends on the CNTR 0 active edge switch bit. When this bit is “0”, the CNTR 0 interrupt request bit is set to “1” at the falling edge of CNTR 0 pin input signal. When this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal. (2) CNTR0 interrupt active edge selection-2 According to the setting value of CNTR 0 active edge switch bit, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the active edge switch bit. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). Fig. 19 Structure of timer X mode register Fig. 20 Timer count source set register T i m e r X m o d e r e g i s t e r T X M a d d r e s s i n i t i a l v a l u e C N T R0 a c t i v e e d g e s w i t c h b i t I n t e r r u p t a t f a l l i n g e d g e C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e I n t e r r u p t a t r i s i n g e d g e C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e T i m e r X o p e r a t i n g m o d e b i t s b b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d ) T i m e r X c o u n t s t o p b i t C o u n t s t a r t C o u n t s t o p b 7 b 0 P 03/ T XO U T o u t p u t v a l i d b i t O u t p u t i n v a l i d I O p o r t O u t p u t v a l i d I n v e r t e d C N T o u t p u t b7 b0 Timer X count source selection bits b1 b0 0 0 : f(X IN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: On-chip oscillator can be used when the on-chip oscillator is enabled by bit 3 of CPUM. Timer count source set register (TCSS : address 002A 16, initial value: 0016) Timer B count source selection bits b7 b6 b5 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : Timer A underflow 1 1 1 : Not available Timer A count source selection bits b4 b3 b2 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : On-chip oscillator output (Note 2) 1 1 1 : Not available

Rev.1.21 Nov 15, 2006 page 26 of 89 REJ03B0156-0121 Fig. 21 Block diagram of timer 1 and timer X Q Q P14/CNTR0 R T Timer X interrupt request bit Toggle flip-flop Timer X count stop bit Pulse width measurement mode Event counter mode CNTR interrupt request bit Pulse output mode Port P1 latchPort P14 direction register CNTR0 active edge switch bit Timer mode Pulse output mode CNTR0 active edge switch bit Timer X count source selection bits P03/TXOUT Prescaler X latch (8) Prescaler X (8) Timer X latch (8) Timer X (8) Data bus “0” “1” “0” “1” Writing to timer X latch Pulse output mode P03/TXOUT output valid Port P03 latch Port P03 direction register Prescaler 1 latch (8) Prescaler 1 (8) Timer 1 latch (8) Timer 1 (8)1/16 Data bus Timer 1 interrupt request Frequency divider XIN On-chip oscillator “00” “01” “11” “0” “10” Clock division ratio selection bits CPU mode register

Rev.1.21 Nov 15, 2006 page 27 of 89 REJ03B0156-0121 G Timer A,B Timer A and Timer B are 16-bit timers and counts the signal which is the oscillation frequency selected by setting of the timer count source set register (TCSS). Timer A and Timer B have the same function except of the count source clock selection. The count source clock of Timer A is selected from among 1/2,1/ IN) clock and on-chip oscillator clock. The count source clock of Timer B is selected from among 1/2, 1/ IN) clock and Timer A underflow. Timer A (B) consists of the low-order of Timer A: TAL (Timer B: TBL) and the high-order of Timer A: TAH (Timer B: TBH). Timer A (B) is decremented by 1 when each time of the count clock is in- put. When the contents of Timer A (B) reach “0000 16”, an underflow occurs at the next count clock, and the timer latch is re- loaded into timer. When Timer A (B) underflows, the Timer A (B) interrupt request bit is set to “1”. Timer A (B) has the Timer A (B) latch to retain the load value. The value of timer A (B) latch is set to Timer A (B) at the timing of Timer A (B) underflow. The division ratio of Timer A (B) is 1/(n+1) pro- vided that the value of Timer A (B) is n. When writing to both the low-order of Timer A (B) and the high or- der of Timer A (B) is executed, writing to “latch only ” or “latch and timer” can be selected by the setting value of the timer A (B) write control bit. When reading from Timer A (B) register is executed, the count value of Timer A (B) is read out. Be sure to write to/read out the low-order of Timer A (B) and the high-order of Timer A (B) in the following order;

• Read Read the high-order of Timer A (B) first, and the low-order of Timer A (B) next and be sure to read both high-order and low-order.
• Write Write to the low-order of Timer A (B) first, and the high-order of Timer A (B) next and be sure to write both low-order and high or- der. Timer A and Timer B can be used for the timing timer of Input cap- ture and Output compare function. I Notes on Timer A, B (1) Setting of timer value When “1: Write to only latch ” is set to the timer A (B) write control bit, written data to timer register is set to only latch even if timer is stopped. Accordingly, in order to set the initial value for timer when it is stopped, set “0: Write to latch and timer simultaneously ” to timer A (B) write control bit. (2) Read/write of timer A Stop timer A to read/write its data when the system is in the follow- ing state;
• CPU operation clock source: X IN oscillation
• Timer A count source: On-chip oscillator output (3) Read/write of timer B Stop timer B to read/write its data when the system is in the fol- lowing state;
• CPU operation clock source: X IN oscillation
• Timer B count source: Timer A underflow
• Timer A count source: On-chip oscillator output

Rev.1.21 Nov 15, 2006 page 28 of 89 REJ03B0156-0121 Fig. 24 Block diagram of timer A and timer B Timer A (low-order) latch (8) Timer A (low-order) (8) Timer A (high-order) latch (8) Timer A (high-order) (8) Data bus Timer A interrupt request Compare Capture Timer B (low-order) latch (8) Timer B (low-order) (8) Timer B (high-order) latch (8) Timer B (high-order) (8) Data bus Timer B interrupt request Compare Capture Timer A count stop bit Timer A count source selection bits On-chip oscillator Timer A write control bit Timer B write control bit Timer B count stop bit Timer B count source selection bits Frequency dividerOn-chip oscillator XIN “00” “01” “11” Clock division ratio selection bits “10” Frequency divider CPU mode register Fig. 22 Structure of timer A, B mode register Fig. 23 Timer count source set register T i m e r A , B m o d e r e g i s t e r T A B M a d d r e s s i n i t i a l v a l u e b 7 b 0 T i m e r A w r i t e c o n t r o l b i t W r i t e t o l a t c h a n d t i m e r s i m u l t a n e o u s l y W r i t e t o o n l y l a t c h T i m e r A c o u n t s t o p b i t C o u n t s t a r t C o u n t s t o p T i m e r B w r i t e c o n t r o l b i t W r i t e t o l a t c h a n d t i m e r s i m u l t a n e o u s l y W r i t e t o o n l y l a t c h T i m e r B c o u n t s t o p b i t C o u n t s t a r t C o u n t s t o p N o t u s e d r e t u r n w h e n r e a d C o m p a r e m o d u l a t i o n m o d e b i t D i s a b l e d E n a b l e d C o m p a r e m o d u l a t i o n m o d e b i t D i s a b l e d E n a b l e d b7 b0 Timer X count source selection bits b1 b0 0 0 : f(X IN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: On-chip oscillator can be used when the on-chip oscillator is enabled by bit 3 of CPUM. Timer count source set register (TCSS : address 002A 16, initial value: 0016) Timer B count source selection bits b7 b6 b5 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : Timer A underflow 1 1 1 : Not available Timer A count source selection bits b4 b3 b2 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : On-chip oscillator output (Note 2) 1 1 1 : Not available

Rev.1.21 Nov 15, 2006 page 29 of 89 REJ03B0156-0121 7547 group has 4-output compare channels. Each channel (0 to 3) has the same function and can be used to output waveform by us- ing count value of either Timer A or Timer B. The source timer for each channel is selected by setting value of the compare x (x = 0, 1, 2, 3) timer source bit. Timer A and Timer B can be selected for the source timer to each channel, respectively. To use each compare channel, set “1” to the compare x output port bit and set the port direction register corresponding to com- pare channel to output mode. The compare value for each channel is set to the compare regis- ter (low-order) and compare register (high-order). Writing to the register for each channel is controlled by setting value of compare register write pointer. Writing to each register is in the following order; 1.Set the value of corresponded output compare channel to the compare register write pointer. 2.Write a value to the compare register (low-order) and compare register (high-order). 3.Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31) re-load bit. When “1” is set to the compare latch y re-load bit, the value set to the compare register is loaded to compare latch when the next timer underflow. When count value of timer and setting value of compare latch is matched, compare output trigger occurs. When “1: Enabled ” is set to the compare trigger x enable bit, the output waveform from port is inverted by compare trigger. When “0: Disabled” is set to the compare trigger x enable bit, the out- put waveform is not inverted, so port output can be fixed to “H” or “L”. When “0: Positive ” is set to the compare x output level latch, the compare output waveform is turned to “H level ” at compare latch x0’s match and turned to “L level” at compare latch x1 ’s match. When “1 :Negative ” is set to the compare x output level latch, the compare output waveform is turned to “L level ” at compare latch x0’s match and turned to “H level” at compare latch x1 ’s match. The compare output level of each channel can be confirmed by reading the compare x output status bit. Compare output interrupt is available when match of each com- pare channel and timer count value. The interrupt request from each channel can be disabled or enabled by setting value of com- pare latch y interrupt source bit. Compare 0,1 (2,3) modulation mode In compare modulation mode, modulation waveform can be gener- ated by using compare channel 0 and 1, or compare channel 2 and 3. To use this mode,

• Set “1: Enabled” to the compare 0,1 (2, 3) modulation mode bit.
• Set Timer A underflow for Timer B count source.
• Set Timer A for the timer source of compare channel 0 (2).
• Set Timer B for the timer source of compare channel 1 (3). In this mode, AND waveform of compare 0 (1) and compare 2 (3) is generated from Port P0 1 and P3 1, respectively. Accordingly, in order to use this mode, set “1” to the compare 0 output port bit or compare 2 output port bit. Fig. 25 Structure of capture/compare register R/W pointer Fig. 26 Structure of compare register re-load register b 7 b 0 C o m p a r e r e g i s t e r R / W p o i n t e r b b b 000 C o m p a r e l a t c h 001 C o m p a r e l a t c h 010 C o m p a r e l a t c h 011 C o m p a r e l a t c h 100 C o m p a r e l a t c h 101 C o m p a r e l a t c h 110 C o m p a r e l a t c h 111 C o m p a r e l a t c h N o t u s e d r e t u r n s w h e n r e a d C a p t u r e r e g i s t e r R W p o i n t e r C a p t u r e l a t c h C a p t u r e l a t c h C a p t u r e r e g i s t e r R W p o i n t e r C a p t u r e l a t c h C a p t u r e l a t c h N o t u s e d r e t u r n s w h e n r e a d C a p t u r e / c o m p a r e r e g i s t e r R / W p o i n t e r C C R P a d d r e s s i n i t i a l v a l u e b 7 b 0 C o m p a r e l a t c h 0 0 , 0 1 r e - l o a d b i t R e l o a d d i s a b l e d R e l o a d a t n e x t u n d e r f l o w C o m p a r e l a t c h r e l o a d b i t R e l o a d d i s a b l e d R e l o a d a t n e x t u n d e r f l o w C o m p a r e l a t c h r e l o a d b i t R e l o a d d i s a b l e d R e l o a d a t n e x t u n d e r f l o w C o m p a r e l a t c h r e l o a d b i t R e l o a d d i s a b l e d R e l o a d a t n e x t u n d e r f l o w N o t u s e d r e t u r n s w h e n r e a d C o m p a r e r e g i s t e r r e - l o a d r e g i s t e r C M P R a d d r e s s i n i t i a l v a l u e I Notes on Output Compare
• When the selected source timer of each compare channel is stopped, written data to compare register is loaded to the com- pare latch simultaneously.
• Do not write the same data to both of compare latch x0 and x1.
• When setting value of the compare latch is larger than timer set- ting value, compare match signal is not generated. Accordingly, the output waveform is fixed to “L” or “H” level. However, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. Accordingly, compare match interrupt occurs.
• When the compare x trigger enable bit is cleared to “0” (dis- abled), the match trigger to the waveform output circuit is disabled, and the output waveform can be fixed to “L” or “H” level. However, in this case, the compare match signal is generated. Accordingly, compare match interrupt occurs.

Rev.1.21 Nov 15, 2006 page 30 of 89 REJ03B0156-0121 Fig. 28 Structure of timer source selection register Fig. 29 Structure of compare output mode register Fig. 30 Structure of capture/compare status register Fig. 31 Structure of compare interrupt source register b7 b0 C o m p a r e 0 t i m e r s o u r c e b i t C o m p a r e t i m e r s o u r c e b i t C o m p a r e t i m e r s o u r c e b i t C o m p a r e t i m e r s o u r c e b i t C a p t u r e t i m e r s o u r c e b i t C a p t u r e t i m e r s o u r c e b i t N o t u s e d r e t u r n s w h e n r e a d T i m e r A T i m e r B T i m e r s o u r c e s e l e c t i o n r e g i s t e r T M S R a d d r e s s i n i t i a l v a l u e b 7 b 0 C o m p a r e 0 o u t p u t l e v e l l a t c h P o s i t i v e N e g a t i v e C o m p a r e o u t p u t l e v e l l a t c h P o s i t i v e N e g a t i v e C o m p a r e o u t p u t l e v e l l a t c h P o s i t i v e N e g a t i v e C o m p a r e o u t p u t l e v e l l a t c h P o s i t i v e N e g a t i v e C o m p a r e t r i g g e r e n a b l e b i t D i s a b l e d E n a b l e d C o m p a r e t r i g g e r e n a b l e b i t D i s a b l e d E n a b l e d C o m p a r e t r i g g e r e n a b l e b i t D i s a b l e d E n a b l e d C o m p a r e t r i g g e r e n a b l e b i t D i s a b l e d E n a b l e d C o m p a r e o u t p u t m o d e r e g i s t e r C M O M a d d r e s s i n i t i a l v a l u e b 7 b 0 C o m p a r e 0 o u t p u t s t a t u s b i t L l e v e l o u t p u t H l e v e l o u t p u t C o m p a r e o u t p u t s t a t u s b i t L l e v e l o u t p u t H l e v e l o u t p u t C o m p a r e o u t p u t s t a t u s b i t L l e v e l o u t p u t H l e v e l o u t p u t C o m p a r e o u t p u t s t a t u s b i t L l e v e l o u t p u t H l e v e l o u t p u t C a p t u r e s t a t u s b i t l a t c h c a p t u r e d l a t c h c a p t u r e d C a p t u r e s t a t u s b i t l a t c h c a p t u r e d l a t c h c a p t u r e d N o t u s e d r e t u r n s w h e n r e a d C a p t u r e / C o m p a r e s t a t u s r e g i s t e r C C S R a d d r e s s i n i t i a l v a l u e b7 b0 C o m p a r e l a t c h 0 0 i n t e r r u p t s o u r c e b i t C o m p a r e l a t c h i n t e r r u p t s o u r c e b i t C o m p a r e l a t c h i n t e r r u p t s o u r c e b i t C o m p a r e l a t c h i n t e r r u p t s o u r c e b i t C o m p a r e l a t c h i n t e r r u p t s o u r c e b i t C o m p a r e l a t c h i n t e r r u p t s o u r c e b i t C o m p a r e l a t c h i n t e r r u p t s o u r c e b i t C o m p a r e l a t c h i n t e r r u p t s o u r c e b i t D i s a b l e d E n a b l e d C o m p a r e i n t e r r u p t s o u r c e r e g i s t e r C I S R a d d r e s s i n i t i a l v a l u e Fig. 27 Structure of capture/compare port register b 7 b 0 C a p t u r e 0 i n p u t p o r t b i t s b b C a p t u r e f r o m P C a p t u r e f r o m P R i n g N o t a v a i l a b l e C o m p a r e o u t p u t p o r t b i t P i s I O p o r t P i s C o m p a r e C o m p a r e o u t p u t p o r t b i t P i s I O p o r t P i s C o m p a r e C a p t u r e i n p u t p o r t b i t C a p t u r e f r o m P R i n g C o m p a r e o u t p u t p o r t b i t P i s I O p o r t P i s C o m p a r e C o m p a r e o u t p u t p o r t b i t P i s I O p o r t P i s C o m p a r e N o t u s e d r e t u r n s w h e n r e a d C a p t u r e / C o m p a r e p o r t r e g i s t e r C C P R a d d r e s s i n i t i a l v a l u e

Rev.1.21 Nov 15, 2006 page 31 of 89 REJ03B0156-0121 Fig. 32 Block diagram of output compare Fig. 33 Block diagram of compare channel 0 Timer A latch Timer A counter Timer B counter Timer B latch Compare latch 00 Compare latch 01 Wave latch channel 0 Compare 0 timer source bit Compare channel 0 Compare channel 1 Compare channel 2 Compare channel 3 P01/CMP0 P02/CMP1 P31/CMP2 P32/CMP3 Compare buffer 00 (16) Compare latch 00 (16) Compare buffer 01 (16) Compare latch 01 (16) Data bus Compare interrupt Compare register write pointer (0012 16, bits 0 to 2) Compare latch 00, 01 re-load bit (0014 16, bit 0) Timer A counter (16) Compare 0 timer source bit (001F 16, bit 0) Compare 0 trigger enable bit (0021 16, bit 4) Output latch Compare 0 output level latch (0021 16, bit 0) Compare 0 output status bit (0022 16, bit 0) Compare 0 output port bit (001E 16, bit 2) P01/CMP0 Timer B counter (16) I/O port Compare latch 00 interrupt source bit (0023 16, bit 0) Compare latch 01 interrupt source bit (0023 16, bit 1) Compare register

Rev.1.21 Nov 15, 2006 page 32 of 89 REJ03B0156-0121 Fig. 34 Block diagram at modulation mode Compare buffer 00 (16) Compare latch 00 (16) Compare buffer 01 (16) Compare latch 01 (16) Data bus Compare register Compare register write pointer (0012 16, bits 0 to 2) Compare latch 00, 01 re-load bit (0014 16, bit 0) Timer A counter (16) Compare 0 (1) timer source bits (001F 16, bit 0 (bit 1) Compare 0 trigger enable bit (0021 16, bit 4) Output latch Compare 0 output level latch (0021 16, bit 0) Compare 0 output status bit (0022 16, bit 0) Compare 0 output port bit (001E 16, bit 2) P01/CMP0 Timer B counter (16) Compare 1 trigger enable bit (0021 16, bit 5) Output latch Compare 1 output level latch (0021 16, bit 1) Compare 1 output status bit (0022 16, bit 1) Underflow Compare latch 10 (16) Compare buffer 10 (16) Compare latch 11 (16) Compare buffer 11 (16) Data bus Compare register Compare latch 10, 11 re-load bit (0014 16, bit 1) Compare register write pointer (0012 16, bits 0 to 2) I/O port

Rev.1.21 Nov 15, 2006 page 33 of 89 REJ03B0156-0121 Fig. 35 Output compare mode (general waveform) Fig. 36 Output compare mode (compare register write timing) 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B0000 000B 0005 0 1 0 Timer underflow Timer count value Compare latch 00 Compare latch 01 Compare 00 match Compare 01 match Compare output Compare interrupt Compare status bit Timer count clock Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register. Re-load the count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B0000 000B 0005 0 1 10 000E 000C Timer underflow Timer count value Compare latch 00 Compare latch 01 Compare latch 00 write Compare latch 01 write Compare latch 00, 01 re-load bit Compare latch 00, 01 re-load signal Compare 00 match Compare 01 match Compare output Compare interrupt Compare status bit Timer count clock Re-load the count value

Rev.1.21 Nov 15, 2006 page 34 of 89 REJ03B0156-0121 Fig. 37 Output compare mode (compare 0, 1 modulation mode) 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0007 0006 0005 0004 00030000 0006 0002 0 1 101 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0007 0006 0005 0004 00030000 0004 0001 0 1 1010 Timer A underflow Timer A count value Compare latch 00 Compare latch 01 Compare 00 match Compare 01 match Compare 0 output Compare 0 output status bit Timer A count clock Carrier wave generated by Compare 0 Compare 0 output Timer B count value Compare latch 10 Compare latch 11 Compare 10 match Compare 11 match Compare 1 output Compare interrupt Compare 1 output status bit Timer A underflow Modulation of output waveform generated by Compare 1 Modulation output Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register. Port outptu wavefowm

Rev.1.21 Nov 15, 2006 page 35 of 89 REJ03B0156-0121 Fig. 38 Output compare mode (compare 0, 1 modulation mode: effect of output level latch) Modulation output Compare 1 output Compare 0 output 1. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Positive”. Modulation output Compare 1 output Compare 0 output 2. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Positive”. Modulation output Compare 1 output Compare 0 output 3. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Negative”. Modulation output Compare 1 output Compare 0 output 4. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Negative”.

Rev.1.21 Nov 15, 2006 page 36 of 89 REJ03B0156-0121 Input capture 7547 group has 2-input capture channels. Each channel (0 and 1) has the same function and can be used to capture count value of either Timer A or Timer B. The source timer for each channel is selected by setting value of the capture x (x = 0, 1) timer source bit. Timer A and Timer B can be selected for the source timer to each channel, respectively. To use each capture channel, set the capture x input port bits and set the port direction register corresponding to capture channel to input mode. The input capture circuit retains the count value of selected timer when external trigger is input. The timer count value is retained to the capture latch x0 when rising edge is input and is retained to the capture latch x1 when falling edge is input. The count value of timer can be retained by software by capture y (y = 00, 01, 10, 11) software trigger bit too. When “1” is set to this bit, count value of timer is retained to the corresponded capture latch. When reading from the capture y software trigger bit is executed, “0” is read out. The latest status of capture latch can be confirmed by reading of the capture x status bit. This bit indicates the capture latch which latest data is in. The valid trigger edge for capture interrupt is set by the capture x interrupt edge selection bits. (Regardless of the setting value of capture x interrupt edge selection bits, timer count values for both edges are retained to the capture latch.) Each capture input has the noise filter circuit that judges continu- ous 4-time same level with sampling clock to be valid. The sampling clock of noise filter is set by the capture x noise filter clock selection bits. Reading from the register for each channel is controlled by setting value of the capture register read pointer. Reading from each reg- ister is in the following order; 1.Set the value of the corresponded input capture channel to the capture register read pointer. 2.Read from the capture register (low-order) and capture register (high-order). I Notes on Input Capture

• If the capture trigger is input while the capture register (low-order and high-order) is in read, captured value is changed between high-order reading and low-order reading. Accordingly, some countermeasure by program is recommended, for example comparing the values that twice of read.
• When CPU operation clock source is X IN oscillation and the on- chip-oscillator is selected for Timer A count source, Timer A cannot be used for the capture source timer. Timer B cannot be used for the capture source timer when the system is in the following state;
• CPU operation clock source: X IN oscillation
• Timer B count source: Timer A underflow
• Timer A count source: On-chip oscillator output
• When writing “1” to capture latch x0 (x1) software trigger bit of capture latch x0 and x1 at the same time, or external trigger and software trigger occur simultaneously, the set value of capture x status bit is undefined.
• When setting the interrupt active edge selection bit and noise fil- ter clock selection bit of external interrupt CAP 0, CAP 1, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge selection bit or noise filter clock selection bit. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled).
• When the capture interrupt is used as the interrupt for return from stop mode, set the capture x noise filter clock selection bits to “00 (Filter stop) ”.

Rev.1.21 Nov 15, 2006 page 37 of 89 REJ03B0156-0121 Fig. 39 Structure of capture software trigger register b 7 b 0 C a p t u r e r e g i s t e r 0 ( L o w - o r d e r ) C A P L a d d r e s s b 7 b 0 C a p t u r e r e g i s t e r 0 ( H i g h - o r d e r ) C A P H a d d r e s s b 7 b 0 C a p t u r e r e g i s t e r 1 ( L o w - o r d e r ) C A P L a d d r e s s b 7 b 0 C a p t u r e r e g i s t e r 1 ( H i g h - o r d e r ) C A P H a d d r e s s b7 b0 C a p t u r e 0 i n t e r r u p t e d g e s e l e c t i o n b i t s b b R i s i n g a n d f a l l i n g e d g e R i s i n g e d g e F a l l i n g e d g e N o t a v a i l a b l e C a p t u r e i n t e r r u p t e d g e s e l e c t i o n b i t s b b R i s i n g a n d f a l l i n g e d g e R i s i n g e d g e F a l l i n g e d g e N o t a v a i l a b l e C a p t u r e n o i s e f i l t e r c l o c k s e l e c t i o n b i t s b b F i l t e r s t o p f XI f XI f XI C a p t u r e n o i s e f i l t e r c l o c k s e l e c t i o n b i t s b b F i l t e r s t o p f XI f XI f XI C a p t u r e m o d e r e g i s t e r C A P M a d d r e s s i n i t i a l v a l u e b 7 b 0 C a p t u r e l a t c h 0 0 s o f t w a r e t r i g g e r b i t C a p t u r e l a t c h s o f t w a r e t r i g g e r b i t C a p t u r e l a t c h s o f t w a r e t r i g g e r b i t C a p t u r e l a t c h s o f t w a r e t r i g g e r b i t E a c h so f t w a r e t r i g g e r o c c u r s b y s e t t i n g t o c o r r e s p o n d i n g b i t r e t u r n s w h e n r e a d N o t u s e d r e t u r n s w h e n r e a d Capture software trigger register (CSTR : address 001316, initial value: 0016) Fig. 40 Structure of capture software trigger register/capture mode register

Rev.1.21 Nov 15, 2006 page 38 of 89 REJ03B0156-0121 Fig. 41 Block diagram of input capture Fig. 42 Block diagram of capture channel 0 P10/CAP0 P00/CAP0 Timer A latch Timer A counter Timer B counter Timer B latch Capture latch 00 Capture latch 01 Trigger input channel 0 Capture 0 timer source bit Capture channel 0 Capture channel 1 Ring /512 Ring /512 P30/CAP1 Capture pointer (001216, bits 4, 5) Capture latch 00 (16) C a p t u re l a t c h 0 1 ( 1 6 ) Data bus Capture interrupt Capture register 0 read pointer (0012 16, bit 4) Timer A counter (16) Capture 0 timer source bit (001F 16, bit 4) Capture trigger Capture 0 status bit (0022 16, bit 4) Digital filter R i n g / 5 1 2 C a p t u r e l a t c h 0 0 s o f t w a r e t r i g g e r b i t b i t Capture 0 input port bits (001E 16, bits 0, 1) T i m e r B c o u n t e r ( 1 6 ) C a p t u r e 0 i n t e r r u p t e d g e s e l e c t i o n b i t s b i t s P 10/ C A P0 C a p t u r e r e g i s t e r C a p t u r e l a t c h 0 ( 1 6 ) Capture 0 noise filter clock selection bits (0020 16, bits 4, 5) P 00/ C A P0 Rising F a l l i n g

Rev.1.21 Nov 15, 2006 page 39 of 89 REJ03B0156-0121 Fig. 43 Capture interrupt edge selection = “rising edge” Fig. 44 Capture interrupt edge selection = “rising and falling edge” 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B0000 XXXX 000A 000C XXXX 0005 0001 000F 1 0 1 01 0 Timer underflow Capture input wave Timer count value Capture latch 00 Capture latch 01 Capture interrupt Capture x (x=0, 1) status bit Re-load the timer count value Overwrite 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B0000 1 0 1 01 0 XXXX 000A 000C XXXX 0005 0001 000F Timer underflow Capture input wave Timer count value Capture latch 00 Capture latch 01 Capture interrupt Capture x (x=0, 1) status bit Re-load the timer count value Overwrite

Rev.1.21 Nov 15, 2006 page 40 of 89 REJ03B0156-0121 Fig. 45 Block diagram of clock synchronous serial I/O1 Fig. 46 Operation of clock synchronous serial I/O1 function Serial Interface The 7547 Group has Serial I/O1 and Serial I/O2. Except that Serial I/O1 has the bus collision detection function and the T XD2 output structure for Serial I/O2 is CMOS only, they have the same function. G Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O1 Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6) to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. F / F P 12/ SC L K S e r i a l I / O 1 s t a t u s r e g i s t e r S e r i a l I / O 1 c o n t r o l r e g i s t e r P 13/ SR D Y P 10/ RXD1/ C A P0 P 11/ TXD1 XIN R e c e i v e b u f f e r r e g i s t e r 1 A d d r e s s 0 0 1 81 Receive shift register 1 R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) Clock control circuitS h i f t c l o c k Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 A d d r e s s 0 0 1 C BRG count source selection bit C l o c k c o n t r o l c i r c u i tFalling-edge detector T r a n s m i t b u f f e r r e g i s t e r 1 Data bus A d d r e s s 0 0 1 81 Shift clock Transmit shift completion flag (TSC) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) Transmit interrupt request (TI) T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t A d d r e s s 0 0 1 91 Data bus A d d r e s s 0 0 1 A1 T r a n s m i t s h i f t r e g i s t e r 1 D0 D1 D2 D3 D4 D5 D6 D0 D1 D2 D3 D4 D5 D6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD1 Write pulse to receive/transmit buffer register 1 (address 001816) Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD 1 pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1

Rev.1.21 Nov 15, 2006 page 41 of 89 REJ03B0156-0121 Fig. 47 Block diagram of UART serial I/O1 (2) Asynchronous Serial I/O1 (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 48 Operation of UART serial I/O1 function XI N OE PE FE 1 / 1 6 Data bus R e c e i v e b u f f e r r e g i s t e r 1 A d d r e s s 0 0 1 81 R e c e i v e s h i f t r e g i s t e r 1 R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) Baud rate generator 1 F r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) Address 001C16 ST/SP/PA generator Transmit buffer register 1 Data bus T r a n s m i t s h i f t r e g i s t e r 1 Address 001816 T r a n s m i t s h i f t c o m p l e t i o n f l a g ( T S C ) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) T r a n s m i t i n t e r r u p t r e q u e s t ( T I ) Address 001916 S T d e t e c t o r SP detector U A R T 1 c o n t r o l r e g i s t e r A d d r e s s 0 0 1 B1 Character length selection bit A d d r e s s 0 0 1 A1 B R G c o u n t s o u r c e s e l e c t i o n b i t Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit C h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s Serial I/O1 control register P 12/ SC L K Serial I/O1 status register P 10/ RXD1/ C A P0 P11/TXD1 TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD0 D1 SP D0 D1ST SP TBE=1 TSC=1 STD0 D1 SP D0 D1ST SP Transmit or receive clock Transmit buffer 1 write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD1 Serial input RXD1 Receive buffer 1 read signal

Rev.1.21 Nov 15, 2006 page 42 of 89 REJ03B0156-0121 [Transmit buffer register 1/receive buffer register 1 (TB1/ RB1)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 status register (SIO1STS)] 0019 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O1 control regis- ter has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 control register (SIO1CON)] 001A The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 control register (UART1CON)] 001B16 The UART1 control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P1 1/TxD1 pin. [Baud rate generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. I Notes on Serial I/O1

• Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled. The functions of P1 2 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0” : P1 2 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) “0” : P13 pin can be used as a normal I/O pin. “1” : P13 pin turns into a S RDY1 output pin. (2) Serial I/O1 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0”: P1 2 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin.

Rev.1.21 Nov 15, 2006 page 43 of 89 REJ03B0156-0121 Fig. 49 Structure of serial I/O1-related registers T r a n s m i t b u f f e r e m p t y f l a g T B E B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d r e t u r n s w h e n r e a d b 7b 7 S e r i a l I O s t a t u s r e g i s t e r S e r i a l I O c o n t r o l r e g i s t e r b 0 b 0 B R G c o u n t s o u r c e s e l e c t i o n b i t C S S f XI f XI S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t S C S B R G o u t p u t d i v i d e d b y w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d B R G o u t p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d E x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d e x t e r n a l c l o c k i n p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d SR D Y o u t p u t e n a b l e b i t S R D Y P p i n o p e r a t e s a s o r d i n a r y I O p i n P p i n o p e r a t e s a s SR D Y o u t p u t p i n T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C I n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d I n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d T r a n s m i t e n a b l e b i t T E T r a n s m i t d i s a b l e d T r a n s m i t e n a b l e d R e c e i v e e n a b l e b i t R E R e c e i v e d i s a b l e d R e c e i v e e n a b l e d S e r i a l I O m o d e s e l e c t i o n b i t S I O M C l o c k a s y n c h r o n o u s U A R T s e r i a l I O C l o c k s y n c h r o n o u s s e r i a l I O S e r i a l I O e n a b l e b i t S I O E S e r i a l I O d i s a b l e d p i n s P t o P o p e r a t e a s o r d i n a r y I O p i n s S e r i a l I O e n a b l e d p i n s P t o P 13o p e r a t e a s s e r i a l I O p i n s b 7 U A R T 1 c o n t r o l r e g i s t e r C h a r a c t e r l e n g t h s e l e c t i o n b i t ( C H A S ) b i t s b i t s P a r i t y e n a b l e b i t P A R E P a r i t y c h e c k i n g d i s a b l e d P a r i t y c h e c k i n g e n a b l e d P a r i t y s e l e c t i o n b i t P A R S E v e n p a r i t y O d d p a r i t y S t o p b i t l e n g t h s e l e c t i o n b i t S T P S s t o p b i t s t o p b i t s P 11/ TXD1 P c h a n n e l o u t p u t d i s a b l e b i t P O F F C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e N o t u s e d r e t u r n w h e n r e a d b 0 S I O S T S a d d r e s s i n i t i a l v a l u e S I O C O N a d d r e s s i n i t i a l v a l u e ( U A R T 1 C O N : a d d r e s s 0 0 1 B1 6, i n i t i a l v a l u e : E 01

Rev.1.21 Nov 15, 2006 page 44 of 89 REJ03B0156-0121 Bus collision detection (SIO1) SIO1 can detect a bus collision by setting UART1 bus collision de- tection interrupt enable bit. When transmission is started in the clock synchronous or asyn- chronous (UART) serial I/O mode, the transmit pin TxD 1 is compared with the receive pin RxD 1 in synchronization with rising edge of transmit shift clock. If they do not coincide with each other, a bus collision detection interrupt request occurs. When a transmit data collision is detected between LSB and MSB of transmit data in the clock synchronous serial I/O mode or be- tween the start bit and stop bit of transmit data in UART mode, a bus collision detection can be performed by both the internal clock and the external clock. A block diagram is shown in Fig. 51. A timing diagram is shown in Fig. 52. Note: Bus collision detection can be used when SIO1 is operating at full-duplex communication. When SIO1 is operating at half-duplex communication, set bus collision detection inter- rupt to be disabled. Fig. 51 Block diagram of bus collision detection interrupt circuit Fig. 52 Timing diagram of bus collision detection interrupt DTxD1 RxD1 Shift clock UART1 bus collision detection interrupt valid bit (Address 000A16, bit 1) UART1 bus collision detection interrupt discrimination bit (Address 000B 16, bit 1) Key-on wakeup/ UART1 bus collision detection interrupt request bit (Address 003C 16, bit 6) Key-on wakeup interrupt request Q 0 : No interrupt request issued Interrupt source set register (INTSET: address 000A16, initial value: 0016) Key-on wakeup interrupt valid bit b7 b0 0: Interrupt invalid Interrupt source discrimination register (INTDIS: address 000B16, initial value: 0016) Key-on wakeup interrupt discrimination bit b7 b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value : 0016) Serial I/O1 receive interrupt request bit b7 b0 Serial I/O1 receive interrupt enable bit 0 : Interrupts disabled Interrupt control register 1 (ICON1 : address 003E16, initial value : 0016) b7 b0 1 : Interrupts enabled CNTR0 interrupt enable bit Key-on wake up/UART1 bus collision INT1 interrupt enable bit INT0 interrupt enable bit Serial I/O2 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit detection interrupt enable bit 1 : Interrupt request issued CNTR 0 interrupt request bit detection interrupt request bit Key-on wake up/UART1 bus collision INT 1 interrupt request bit INT0 interrupt request bit Serial I/O2 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O1 transmit interrupt request bit 1: Interrupt occurs 0: Interrupt does not occur Not used (returns “0” when read) Timer 1 interrupt discrimination bit A/D conversion interrupt discrimination bit discrimination bit UART1 bus collision detection interrupt 1: Interrupt valid Not used (returns “0” when read) Timer 1 interrupt valid bit A/D conversion interrupt valid bit UART1 bus collision detection interrupt valid bit Fig. 50 Bus collision detection circuit related registers Bus collision detection interrupt generation Data collision Transmit shift clock Transmit pin TxD1 Receive pin RxD1

Rev.1.21 Nov 15, 2006 page 45 of 89 REJ03B0156-0121 Fig. 53 Block diagram of clock synchronous serial I/O2 Fig. 54 Operation of clock synchronous serial I/O2 function G Serial I/O2 Serial I/O2 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O2 Mode Clock synchronous serial I/O2 mode can be selected by setting the serial I/O2 mode selection bit of the serial I/O2 control register (bit 6) to “1”. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. D0 D1 D2 D3 D4 D5 D6 D0 D1 D2 D3 D4 D5 D6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD2 Write pulse to receive/transmit buffer register 2 (address 002E16) Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD 2 pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY2 F / F P 06/ SC L K S e r i a l I / O 2 s t a t u s r e g i s t e r S e r i a l I / O 2 c o n t r o l r e g i s t e r P 07/ SR D Y P 04/ RXD2 P 05/ TXD2 XI N R e c e i v e b u f f e r r e g i s t e r 2 A d d r e s s 0 0 2 E1 R e c e i v e s h i f t r e g i s t e r 2 R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) C l o c k c o n t r o l c i r c u i tS h i f t c l o c k S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t F r e q u e n c y d i v i s i o n r a t i o n B a u d r a t e g e n e r a t o r 2 A d d r e s s 0 0 3 2 B R G c o u n t s o u r c e s e l e c t i o n b i t C l o c k c o n t r o l c i r c u i tF a l l i n g - e d g e d e t e c t o r T r a n s m i t b u f f e r r e g i s t e r 2 D a t a b u s A d d r e s s 0 0 2 E1 S h i f t c l o c k T r a n s m i t s h i f t c o m p l e t i o n f l a g ( T S C ) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) T r a n s m i t i n t e r r u p t r e q u e s t ( T I ) T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t A d d r e s s 0 0 2 F D a t a b u s A d d r e s s 0 0 3 01 T r a n s m i t s h i f t r e g i s t e r 2

Rev.1.21 Nov 15, 2006 page 46 of 89 REJ03B0156-0121 Fig. 55 Block diagram of UART serial I/O2 (2) Asynchronous Serial I/O2 (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O2 mode selection bit of the serial I/O2 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 56 Operation of UART serial I/O2 function XIN OE PE FE Data bus Receive buffer register 2 Address 002E16 Receive shift register 2 Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator 2 Frequency division ratio 1/(n+1) Address 003216 ST/SP/PA generator Transmit buffer register 2 Data bus Transmit shift register 2 Address 002E16 Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 002F16 ST detector SP detector UART2 control register Address 003116 Character length selection bit Address 003016 BRG count source selection bit Transmit interrupt source selection bit Serial I/O2 synchronous clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O2 control register P06/SCLK2 Serial I/O2 status register P04/RXD2 P05/TXD2 TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD0 D1 SP D0 D1ST SP TBE=1 TSC=1 STD0 D1 SP D0 D1ST SP Transmit or receive clock Transmit buffer 2 write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD2 Serial input RXD2 Receive buffer 2 read signal

Rev.1.21 Nov 15, 2006 page 47 of 89 REJ03B0156-0121 [Transmit buffer register 2/receive buffer register 2 (TB2/ RB2)] 002E16 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O2 status register (SIO2STS)] 002F The read-only serial I/O2 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O2 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O2 enable bit SIOE (bit 7 of the serial I/O2 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O2 status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O2 control regis- ter has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O2 control register (SIO2CON)] 0030 The serial I/O2 control register consists of eight control bits for the serial I/O2 function. [UART2 control register (UART2CON)] 003116 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. [Baud rate generator 2 (BRG2)] 0032 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. I Notes on Serial I/O2

• Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O2 is enabled. The functions of P0 6 and P07 are switched with the setting values of a serial I/O2 mode selection bit and a serial I/O2 synchronous clock selection bit as follows. (1) Serial I/O2 mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O2 synchronous clock selection bit “0” : P0 6 pin turns into an output pin of a synchronous clock. “1” : P06 pin turns into an input pin of a synchronous clock. Setup of a SRDY2 output enable bit (SRDY) “0” : P07 pin can be used as a normal I/O pin. “1” : P07 pin turns into a S RDY2 output pin. (2) Serial I/O2 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O2 synchronous clock selection bit “0”: P0 6 pin can be used as a normal I/O pin. “1”: P06 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P07 pin. It can be used as a normal I/O pin.

Rev.1.21 Nov 15, 2006 page 48 of 89 REJ03B0156-0121 T r a n s m i t b u f f e r e m p t y f l a g T B E B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d r e t u r n s w h e n r e a d b 7b 7 S e r i a l I O s t a t u s r e g i s t e r S e r i a l I O c o n t r o l r e g i s t e r b 0 b 0 B R G c o u n t s o u r c e s e l e c t i o n b i t C S S f XI f XI S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t S C S B R G o u t p u t d i v i d e d b y w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d B R G o u t p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d E x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d e x t e r n a l c l o c k i n p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d SR D Y o u t p u t e n a b l e b i t S R D Y P 07 p i n o p e r a t e s a s o r d i n a r y I O p i n P 07 p i n o p e r a t e s a s SR D Y o u t p u t p i n T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C I n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d I n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d T r a n s m i t e n a b l e b i t T E T r a n s m i t d i s a b l e d T r a n s m i t e n a b l e d R e c e i v e e n a b l e b i t R E R e c e i v e d i s a b l e d R e c e i v e e n a b l e d S e r i a l I O m o d e s e l e c t i o n b i t S I O M C l o c k a s y n c h r o n o u s U A R T s e r i a l I O C l o c k s y n c h r o n o u s s e r i a l I O S e r i a l I O e n a b l e b i t S I O E S e r i a l I O d i s a b l e d p i n s P t o P o p e r a t e a s o r d i n a r y I O p i n s S e r i a l I O e n a b l e d p i n s P t o P o p e r a t e a s s e r i a l I O p i n s b7 U A R T c o n t r o l r e g i s t e r Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits Not used (return “0” when read) (Do not write “1” to this bit.) Not used (return “1” when read) S I O S T S a d d r e s s i n i t i a l v a l u e S I O C O N a d d r e s s i n i t i a l v a l u e (UART2CON : address 003116, initial value: E016) Fig. 57 Structure of serial I/O2-related registers

Rev.1.21 Nov 15, 2006 page 49 of 89 REJ03B0156-0121 The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/ D conversion. [A/D control register] ADCON The A/D control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 3 is the A/D conversion clock selection bit. When “0” is set to this bit, the A/D conversion clock is f(X IN)/2 and the A/D conversion time is 122 cycles of f(X IN). When “1” is set to this bit, the A/D conversion clock is f(XIN) and the A/D conversion time is 61 cycles of f(X IN). Bit 4 is the A/D conversion completion bit. The value of this bit re- mains at “0” during A/D conversion, and changes to “1” at completion of A/D conversion. A/D conversion is started by setting this bit to “0”. [Comparison voltage generator] The comparison voltage generator divides the voltage between AV SS and VREF by 1024, and outputs the divided voltages. [Channel selector] The channel selector selects one of ports P2 7/AN7 to P2 0/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input volt- age with the comparison voltage and stores its result into the A/D conversion register. When A/D conversion is completed, the con- trol circuit sets the A/D conversion completion bit and the A/D interrupt request bit to “1”. Because the comparator is constructed linked to a capacitor, set f(X IN) in order that the A/D conversion clock is 250 kHz or over during A/D conversion. I Notes on A/D converter As for AD translation accuracy, on the following operating condi- tions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sen- sitive to noise when V REF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where V REF voltage and Vcc voltage are set up to the same value.. (2) When V REF voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at V REF=3.0 V or more is recom- mended. Fig. 58 Structure of A/D control register Fig. 59 Structure of A/D conversion register Read 8-bit (Read only address 003516) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2(Address 003516) Read 10-bit (read in order address 003616, 003516) b7 b0 b9 b8(Address 003616) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0(Address 003516) Note: High-order 6-bit of address 003616 returns “0” when read. N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) A / D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d b 7 b 0 A n a l o g i n p u t p i n s e l e c t i o n b i t s P 20/ A P 21/ A P 22/ A P 23/ A P 24/ A P 25/ A P 26/ A P 27/ A N o t e s 1 : A / D c o n v e r s i o n c l o c k = f ( XI N) c a n b e u s e d o n l y w h e n c e r a m i c o s c i l l a t i o n o r o n c h i p o s c i l l a t o r i s u s e d S e l e c t f XI w h e n R C o s c i l l a t i o n i s u s e d A / D c o n t r o l r e g i s t e r A D C O N a d d r e s s i n i t i a l v a l u e A / D c o n v e r s i o n c l o c k s e l e c t i o n b i t (N o t e 1) f XI f XI

Rev.1.21 Nov 15, 2006 page 50 of 89 REJ03B0156-0121 Fig. 60 Block diagram of A/D converter A/D control register (Address 003416) Channel selector A/D control circuit Resistor ladder VREF Comparator A/D interrupt request b7 b0 Data bus P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 A/D conversion register (low-order) (Address 003616) (Address 003516) A/D conversion register (high-order) VSS f(XIN) f(XIN)/2

Rev.1.21 Nov 15, 2006 page 51 of 89 REJ03B0156-0121 The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16-bit counter. G Standard operation of watchdog timer (1) Start of watchdog timer The watchdog timer starts operating by setting value of the func- tion set ROM data 2 (FSROM2: address 0FFA 16) or writing to the watchdog timer control register (WDTCON: address 0039 16). Set “0” to the watchdog timer start selection bit (bit 1 of FSROM2) when operation starts by setting value of FSROM2. In this case, the watchdog timer starts operating after releasing reset. Write an arbitrary value to WDTCON when FSROM2 is set to be invalid and operation starts by program. Operation by program can start even when “1” (stop state after releasing reset) is set to the watchdog timer start selection bit. (2) Operation of watchdog timer Watchdog timer L is set to “FF 16”and watchdog timer H is set to “FF16” by reset or writing an arbitrary value to WDTCON. When the watchdog timer starts operating, the selected clock is counted and internal reset occurs by the watchdog timer H under- flow. Accordingly, write to WDTCON before underflow by program. When WDTCON is read, the values of the STP instruction function selection bit, watchdog timer H count source selection bit and the high-order 6 bits of the watchdog timer H are read. (3) Count source clock of watchdog timer The count source clock of the watchdog timer can be selected by the watchdog timer source clock selection bit (bit 0 of FSROM2). If “0” is set to the watchdog timer source clock selection bit, the count source clock of the watchdog timer always is the on-chip os- cillator output/16. It changes by setting the clock division ratio selection bits (bit 7 and bit 6 of the CPU mode register) when “1” is set to the watch- dog timer source clock selection bit or FSROM2 is set to be invalid. When a double-speed mode, a high-speed mode, and a middle- speed mode are selected by the clock division ratio selection bits, the count source clock of the watchdog timer becomes f(X IN)/16. When the supply from on-chip oscillator is selected, it becomes the on-chip oscillator output/16. (4) Watchdog timer H count source selection bit The count source of watchdog timer H can be selected by FSROM2 or program. When “0” is set to watchdog timer H count source selection bit (bit 2 of FSROM2), the watchdog timer L underflow signal is selected as the count source of watchdog timer H and the detection time is 131.072 ms at f(X IN) = 8 MHz. When “1” is set to this bit, the clock selected as the count source of watchdog timer L is input to watchdog timer H. In this case, the detection time is 512 µs at f(X IN) =8 MHz. When FSROM2 is set to be invalid, the count source of watchdog timer can be set by watchdog timer H count source selection bit (bit 7 of WDTCON). When “0” is set to this bit, the watchdog timer L underflow signal is selected as the count source of watchdog timer H. When “1” is set to this bit, the clock selected as the count source of watchdog timer L is input to watchdog timer H. This bit is cleared to “0” after reset. (5) STP instruction function selection bit The function of the STP instruction can be selected by FSROM2 or program. When “0” is set to the STP instruction function selection bit (bit 3 of FSROM2), system enters into the stop mode at the STP instruc- tion execution. When “1” is set to this bit, internal reset occurs at the STP instruc- tion execution. When the function of the STP instruction is set by FSROM2, it cannot be changed by program. When setting value of FSROM2 is invalid, the function of the STP instruction can be set by the STP instruction function selection bit (bit 6 of WDTCON). When “0” is set to this bit, system enters into the stop mode at the STP instruction execution. When “1” is set to this bit, internal reset occurs at the STP instruc- tion execution. Once this bit is set to “1”, it cannot be changed to “0” by program. This bit is cleared to “0” after reset. I Notes on watchdog timer 1. The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer un- derflow. 2. The watchdog timer stops during the stop mode. However, the watchdog timer is running during the oscillation stabilizing time after the STP instruction is released. In order to avoid the un- derflow of the watchdog timer, the watchdog timer count source selection bit (bit 7 of watchdog timer control register (address 16)) before executing the STP instruction. 3. The STP instruction function selection bit (bit 6 of watchdog timer control register (address 39 16)) can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit.

Rev.1.21 Nov 15, 2006 page 52 of 89 REJ03B0156-0121 Fig. 61 Block diagram of watchdog timer Fig. 62 Structure of watchdog timer control register Watchdog timer H (read only for high-order 6-bit) Watchdog timer H count source selection bit (Note 1, Note 4) 0 : Watchdog timer L underflow 1 : On-chip oscillator/16 or f(X IN)/16 b7 b0 Watchdog timer control register (Note 1) (WDTCON: address 003916, initial value: 3F16) STP instruction function selection bit (Note 1, Note 3) 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution Notes 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed after releasing reset since bits 6 and 7 of WDTCON are fixed. 2: The setting values of FSROM2 become valid by setting “0” to bit 0 of function set ROM data 0 (FSROM0). The setting values of FSROM2 are invalid by setting “1” to this bit. This cannot be controlled by FSROM2. This bit function can be set by setting bit 3 of FSROM2. Bit 3 of FSROM2 = 0: Bit 6 of WDTCON is fixed to “0”. Bit 3 of FSROM2 = 1: Bit 6 of WDTCON is fixed to “1”. Control by Function set ROM data 2 (FSROM2: address FFDA16) (Note 2) The initial value of this bit is changed by setting bit 2 of FSROM2. Bit 2 of FSROM2 = 0: Initial value of bit 7 of WDTCON is changed to “0”. Bit 2 of FSROM2 = 1: Initial value of bit 7 of WDTCON is changed to “1”. The following setting can be available by setting bit 0 of FSROM2. (This setting cannot be set by WDTCON) Bit 0 of FSROM2 = 0: The source clock of watchdog timer is always Bit 0 of FSROM2 = 1: The source clock of watchdog timer is the on-chip oscillator output/16 of f(X IN)/16. 3:The setting value of this bit can be fixed after releasing reset by FSROM2, and then, the setting value cannot be changed by program. Also, when the setting by program is performed, this bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. 4: When FSROM2 is used to select the watchdo g timer H count source, the initial value of this bit is changed after releasing reset. the on-chip oscillator output/16. “0” “1”1/16 Reset pin input WDTCON: Watchdog timer control register FSROM2: Function set ROM data 2 XIN clock On-chip oscillator CPUM: CPU mode register Data bus Reset circuit Watchdog timer H (8) Write "FF16" to WDTCON Internal reset Watchdog timer L (8) STP Instruction Write “FF16” to WDTCON Watchdog timer H count source selection bit (bit 2 of FSROM2) or bit 7 of WDTCON Source clock selection (auto-switch depending on setting of CPUM) STP instruction function selection bit (bit 3 of FSROM2) Bit 6 of WDTCON On-chip oscillator output can be fixed by bit 0 of FSROM2 Count start (Watchdotm timer start selection bit (bit 1 of FSROM2)) or writing arbitrary value to WDTCON

Rev.1.21 Nov 15, 2006 page 53 of 89 REJ03B0156-0121 Fig. 63 Operation waveform diagram of power-on reset circuit Fig. 64 Operation waveform diagram of low voltage detection circuit VCC (Note)1 ms or less Power-on Reset released Internal reset signal Reset state Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Po circuit output wer-on reset VCC Reset voltage (Typ:1.90V) Internal reset signal Microcomputer starts operation by the built-in on-chip oscillator. Internal reset signal SYNC Address Data Reset address from the vector table On-chip oscillator clock RING Internal CPU clock φ RESET 9 to 16 cycles of internal CPU clock φ Fig. 65 Timing diagram at reset Power-on Reset Circuit Reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. In order to use the power-on reset circuit effectively, the time for the supply voltage to rise from 0 V to 1.8 V must be set to 1 ms or less. When the built-in power-on reset circuit is used, pull-up the RESET pin to VCC. Low voltage Detection Circuit The built-in low voltage detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the power source voltage drops below a set value (Typ.1.90 V). The low voltage detection circuit is valid by setting “1” to bit 1 of the function set ROM data 0. Also, when “1” is set to bit 3 of the function set ROM data 0, the low voltage detection circuit can be valid even in the stop mode. The low voltage detection circuit is stopped in the stop mode by setting “0” to this bit, so that the power dissipation is reduced.

Rev.1.21 Nov 15, 2006 page 54 of 89 REJ03B0156-0121 Fig. 66 Internal status of microcomputer at reset Prescaler 1 (PRE1) Timer 1 (T1) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS) Serial I/O2 control register (SIO2STS) A/D control register (ADCON) MISRG Watchdog timer control register (WDTCON) (Note 3) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) (Note 3) Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1) (18) (19) (20) (21) (22) (23) (29) (30) (31) (32) (33) (34) FF16 0116 0016 0016 FF16 FF16 0016 002816 002916 002A16 002B16 002C16 002D16 002F16 003016 003416 003716 003916 003A16 003B16 003C16 003E16 0011 1111 0016 0016 0016 1000 0000 Contents of address FFFC16 Notes 1: X : Undefined 2: The content of other registers is undefined when the microcomputer is reset. The initial values must be surely set before you use it. 3: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial values of these registers at reset are changed. Contents of address FFFD16 XXXX X1XX Port P0 direction register (P0D) Port P1 direction register (P1D) Port P2 direction register (P2D) Port P3 direction register (P3D) Pull-up control register (PULL) (1) (2) (3) (4) (13) Register contents 0016 0016 0016 0016000116 000316 000516 000716 001616 Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) (16) (17) Serial I/O1 status register (SIO1STS)(15) 001A16 001B16 0016 1110 0000 001916 1000 0000 XXX 0 0000 Address Port P1P3 control register (P1P3C) (14) 001716 0016 Timer A, B mode register (TABM) Capture/Compare port register (CCPR) Timer source selection register (TMSR) 0016 0016 0016 001D16 001E16 001F16 0016 0016 0016 002016 002116 002216 0016002316 (35) (36) (37) (38) (39) (41) (42) (43) (44) (45) Serial I/O2 register (SIO2CON) 0031 Interrupt request register 2 (IREQ2) 003D16 0016 Interrupt control register 2 (ICON2) 003F16 0016 (46) (47) (48) (49) UART2 control register (UART2CON) On-chip oscillation division ratio selection register (RODR) 0016003816 (40) 0000 00 10 0001 00 00 1110 00 00 1000 00 00 Capture mode register (CAPM) Compare output mode register (CMOM) (25) (26) (27) (28) FF16002416 FF16 FF16 002516 002616

002716 FF16

Timer A (low-order) (TAL) Timer A (high-order) (TAH) Timer B (low-order) (TBL) Timer B (high-order) (TBH) (24) Capture/Compare status register (CCSR) Compare interrupt source register (CISR) (8) (9) (10) (11) (12) Interrupt source discrimination register (INTDIS) Compare register (low-order) (CMPL) (6) (7) Interrupt source set register (INTSET)(5) 000B16 001016 0016 000A16 Compare register (high-order) (CMPH) Capture/Compare register R/W pointer (CCRP) Capture software trigger register (CSTR) 0016 0016 0016 001116 001216 001316 0016 0016 001416 001516 Compare register re-load register (CMPR) Port P0P3 drive capacity control register (DCCR) 0016 0016 Processor status register Program counter (PS) (PCH) (PCL) FF16 FF16 (50) Watchdog timer H (51) Watchdog timer L

Rev.1.21 Nov 15, 2006 page 55 of 89 REJ03B0156-0121 Fig. 68 External circuit of ceramic resonator Fig. 69 External circuit of RC oscillation Fig. 70 External clock input circuit Fig. 67 Processing of XIN and XOUT pins at on-chip oscillator operation Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator be- tween X IN and XOUT, and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between X IN and X OUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depending on conditions.) (1) On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect X IN pin to V CC through a resistor and leave X OUT pin open. The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins X IN and XOUT at the shortest distance. A feedback resistor is built in be- tween pins XIN and XOUT. (3) RC oscillation When the RC oscillation is used for the main clock, connect the X IN pin and X OUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a micro- computer. So, set the constants within the range of the frequency limits. (4) External clock When the external signal clock is used for the main clock, connect the X IN pin to the clock source and leave X OUT pin open. Select “0” (ceramic oscillation) to oscillation mode selection bit of CPU mode register (003B 16). Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer ’s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feed- back resistor between X IN and X OUT following the instruction. Note: Connect the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is af- fected by a capacitor, a resistor and a micro- computer. So, set the constants within the range of the frequency limits. Note: The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies and obtain the sufficient margin. Note: XI N XO U T E x t e r n a l o s c i l l a t i o n c i r c u i t VC C VS S Open M 3 7 5 4 7 XI N XO U T C R M 3 7 5 4 7 XI N COUTCI N XOUT M 3 7 5 4 7 Rd XI N XO U T M 3 7 5 4 7 O p e n R

Rev.1.21 Nov 15, 2006 page 56 of 89 REJ03B0156-0121 (1) Oscillation control

• Stop mode When the STP instruction is executed, the internal clock φ stops at an “H” level and the X IN oscillator stops. At this time, timer 1 is set to “0116” and prescaler 1 is set to “FF16” when the oscillation sta- bilization time set bit after release of the STP instruction is “0”. On the other hand, timer 1 and prescaler 1 are not set when the above bit is “1”. Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(X IN)/16 is forcibly connected to the input of prescaler 1. When an external interrupt is accepted, oscillation is restarted but the internal clock φ remains at “H” until timer 1 underflows. As soon as timer 1 underflows, the internal clock φ is supplied. This is because when a ceramic oscil- lator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an “L” level to the RESET pin while oscillation becomes stable, or set the wait time by on-chip oscillator operation after system is released from reset until the oscillation is stabled.
• Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock re- starts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immedi- ately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed. Fig. 71 Structure of CPU mode register Oscillation mode selection bit (Note 1, Note 4) 0 : Ceramic oscillation 1 : RC oscillation CPU mode register (Note 1) (CPUM: address 003B 16, initial value: 8016) Stack page selection bit 0 : 0 page 1 : 1 page Clock division ratio selection bits b7 b6 0 0 : f(φ) = f(X IN)/2 (High-speed mode) 0 1 : f(φ) = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f(φ) = f(XIN)/1 (Double-speed mode)(Note 5) On-chip oscillator oscillation control bit (Note 3) 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop X IN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Processor mode bits b1 b0 0 0 Single-chip mode 0 1 Not available 1 0 Not available 1 1 Not available Note 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed after releasing reset since bit 5 of CPUM is fixed. 2: The setting values of FSROM2 become valid by setting “0” to bit 0 of function set ROM data 0 (FSROM0). The setting values of FSROM2 are invalid by setting “1” to this bit. (In order that FSROM2 is invalid, write to CPUM after releasing reset.) 3: When bit 4 of FSROM2 is set to “0”, the operation of on-chip oscillator cannot be stopped. Since the on-chip oscillator is not stopped also in the stop mode, the dissipation current in the stop mode is increased. 4: The setting value of bit 5 of CPUM can be fixed after releasing reset by setting value of bit 5 of FSROM2. Also, when the setting of FSROM2 is invalid, this bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. This bit is initialized by reset, and then, rewriting it is enabled. 5: This setting can be used only at ceramic oscillation. Do not use this at RC oscillation. b7 b0 Control by Function set ROM data 2 (FSROM2: address FFDA16) (Note 2) This bit function can be set by setting bit 5 of FSROM2. (Note 4) Bit 5 of FSROM2 = 0: Bit 5 of CPUM is fixed to “0”. Bit 5 of FSROM2 = 1: Bit 5 of CPUM is “0” or “1”. This cannot be controlled by FSROM2. This cannot be controlled by FSROM2. This bit function can be set by setting bit 4 of FSROM2. (Note 3) Bit 4 of FSROM2 = 0: Bit 3 of CPUM is fixed to “0”. Bit 4 of FSROM2 = 1: Bit 3 of CPUM is “0” or “1”. This cannot be controlled by FSROM2. This cannot be controlled by FSROM2. I Notes on Clock Generating Circuit For use with the oscillation stabilization set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used.
• Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip os- cillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register.
• Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected.
• CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. After rewriting it is disable to write any data to the bit. (The emulator MCU “M37542RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.

Rev.1.21 Nov 15, 2006 page 57 of 89 REJ03B0156-0121 G On-chip oscillation division ratio At on-chip oscillator mode, division ratio of on-chip oscillator for CPU clock is selected by setting value of on-chip oscillation divi- sion ratio selection register. The division ratio of on-chip oscillation for CPU clock is selected from among 1/1, 1/2, 1/8, 1/128. The op- eration clock for the peripheral function block is not changed by setting value of this register. I Notes on On-chip Oscillation Division Ratio

• When system is released from reset, R OSC/8 (on-chip oscillator middle-speed mode) is selected for CPU clock.
• When state transition from the ceramic or RC oscillation to on- chip oscillator, R OSC/8 (on-chip oscillator middle-speed mode) is selected for CPU clock.
• When the MCU operates by on-chip oscillator for the main clock without external oscillation circuit, connect X IN pin to V CC through a resistor and leave X OUT pin open. Set “10010x002” (x = 0 or 1) to CPUM. Fig. 72 Structure of on-chip oscillation division ratio selection register On-chip oscillation division ratio selection register (RODR: address 003716, initial value: 0216) On-chip oscillator division ratio b1 b0 0 0: On-chip oscillator double-speed mode (R OSC/1) 0 1: On-chip oscillator high-speed mode (R OSC/2) 1 0: On-chip oscillator middle-speed mode (R OSC/8) 1 1: On-chip oscillator low-speed mode (R OSC/128) Not used (returns “0” when read) b7 b0
• Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 75 can be performed by setting the clock division ratio selection bits (bits 7 and 6), X IN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 75.
• Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O, Serial I/O2, A/D converter, Watchdog timer) The count sources of these functions are af fected by the clock divi- sion selection bit of the CPU mode register. The f(X IN) clock is supplied to the watchdog timer when selecting f(XIN) as the CPU clock. The on-chip oscillator output is supplied to these functions when se- lecting the on-chip oscillator output as the CPU clock. However, the watchdog timer is also affected by the function set ROM.

Rev.1.21 Nov 15, 2006 page 58 of 89 REJ03B0156-0121 Fig. 73 Block diagram of internal clock generating circuit (for ceramic resonator) Fig. 74 Block diagram of internal clock generating circuit (for RC oscillation) S R Q S R Q R SQ (Note) 1/4 1/2 WIT instruction STP instruction Timing φ (Internal clock) STP instruction Interrupt request Reset Interrupt disable flag l High-speed mode Middle-speed mode Prescaler 1 Timer 1 Clock division ratio selection bits Double-speed mode On-chip oscillator mode On-chip oscillator XOUTXIN Clock division ratio selection bits Middle-, high-, double-speed mode On-chip oscillator mode 1/41/2 On-chip oscillator division ratio selection bitsROSC/128 ROSC/8 ROSC/2 ROSC/1 RESET Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Note: S R Q S R Q R SQ 1/4 1/2 WIT instruction STP instruction Timing φ (Internal clock) STP instruction Interrupt request Reset Interrupt disable flag l High-speed mode Middle-speed mode Prescaler 1 Timer 1 Clock division ratio selection bits Double-speed modeRING XOUT XIN Delay Clock division ratio selection bits Middle-, high-, double-speed mode On-chip oscillator mode RESET On-chip oscillator mode On-chip oscillator division ratio selection bitsOn-chip oscillator 1/161/41/2 ROSC/128 ROSC/8 ROSC/2 ROSC/1

Rev.1.21 Nov 15, 2006 page 59 of 89 REJ03B0156-0121 Fig. 75 State transition STP mode f(XIN) oscillation: stop On-chip oscillator: stop WAIT mode 1 WAIT mode 2 WAIT mode 3 WAIT mode 3 ’ Operation clock source: On-chip oscillator (Note 2)Operation clock source: f(XIN) (Note 1) Notes on switch of clock (1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio. f(XIN)/2 (high-speed mode) f(XIN)/8 (middle-speed mode) f(XIN) (double-speed mode, only at a ceramic oscillation) (2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio. ROSC/1 (On-chip oscillator double-speed mode) ROSC/2 (On-chip oscillator high-speed mode) ROSC/8 (On-chip oscillator middle-speed mode) ROSC/128 (On-chip oscillator low-speed mode) (3) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’, ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock. (4) Executing the state transition state 3 to 2 or state 3’ to 2’ after stabilizing XIN oscillation. (5) When the state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. 1. CPUM 76 = 102 (state 2 → state 3) 2. NOP instruction Transition from Double-speed mode: NOP ✕ 3 Transition from High-speed mode: NOP ✕ 1 Transition from Middle-speed mode: NOP ✕ 0 3. CPU4 = 12 (state 3 → state 4) (6) When the state 3 → state 2 → state 1 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. 1. CPUM 76 = 002 or 012 or 112 (state 3 → state 2) 2. NOP instruction Transition from On-chip oscillator double-speed mode: NOP ✕ 4 Transition from On-chip oscillator high-speed mode: NOP ✕ 2 Transition from On-chip oscillator middle-speed mode: NOP ✕ 0 Transition from On-chip oscillator low-speed mode: NOP ✕ 0 3. CPUM3 = 12 (state 2 → state 1) WAIT mode 4 State 4 RESET state f(XIN) oscillation: enabled On-chip oscillator: enabled State 3 State 3’ WAIT mode 2 ’ State 2’ State 2State 1 Interrupt STP instruction Interrupt WIT instruction Interrupt CPUM3=02 CPUM3=12 CPUM76=102 (Note 3) CPUM76=002 012 112 (Note 4) CPUM76=102 (Note 3) CPUM76=002 012 112 MISRG1=12 MISRG1=02 MISRG1=12 (Note 4) MISRG1=02 Reset released (Note 3) CPUM 4=02 CPUM4=12 Interrupt WIT instruction WIT instruction InterruptWIT instruction Interrupt WIT instruction Interrupt WIT instruction STP instruction STP instruction STP instruction Interrupt Interrupt Interrupt f(XIN) oscillation: enabled On-chip oscillator: stop f(XIN) oscillation: enabled On-chip oscillator: enabled f(XIN) oscillation: enabled On-chip oscillator: enabled f(XIN) oscillation: enabled On-chip oscillator: enabled f(XIN) oscillation: enabled On-chip oscillator: enabled Oscillation stop detection circuit valid f(XIN) oscillation: stop On-chip oscillator: enabled

Rev.1.21 Nov 15, 2006 page 60 of 89 REJ03B0156-0121 Fig. 76 Structure of MISRG G Oscillation stop detection circuit The oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or RC oscillation circuit stops by dis- connection. To use this circuit, set an on-chip oscillator to be in active. The oscillation stop detection circuit is in active to set “1” to the ceramic or RC oscillation stop detection function active bit. When the oscillation stop detection circuit is in active, ceramic or RC os- cillation is watched by the on-chip oscillator. When stop of ceramic or RC oscillation is detected, the oscillation stop detection status bit is set to “1”. While “1” is set to the oscillation stop reset bit, in- ternal reset occurs when oscillation stop is detected. The external reset and the oscillation stop reset can be discrimi- nated by reading the oscillation stop detection status bit. The oscillation stop detection status bit retains “1”, not initialized, when the oscillation stop reset occurs. The oscillation stop detec- tion status bit is initialized to “0” when the external reset occurs. Accordingly, reset by oscillation stop can be confirmed by using this flag. I Notes on Oscillation Stop Detection Circuit

• Do not execute the transition to “state 2 ’a” shown in Figure 77 because in this “state 2 ’a”, MCU is stopped without reset even when X IN oscillation is stopped.
• Ceramic or RC oscillation stop detection function active bit is not cleared by the oscillation stop internal reset. Accordingly, the oscillation stop detection circuit is in active when system is re- leased from internal reset cause of oscillation stop detection.
• Oscillation stop detection status bit is initialized by the following operation. (1) External reset (2) Write “0” data to the ceramic or RC oscillation stop detection function active bit.
• The oscillation stop detection circuit is not included in the emu- lator MCU “M37542RSS”. MISRG(address 003816, initial value: 0016) b7 b0 Oscillation stabilization time set bit after release of the STP instruction 0: Set “01 16” in timer1, and “FF16” in prescaler 1 automatically 1: Not set automatically Reserved bits (Do not write “1” to these bits) Not used (return “0” when read) Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected Oscillation stop reset bit 0: Oscillation stop reset disabled 1: Oscillation stop reset enabled Ceramic or RC oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active

Rev.1.21 Nov 15, 2006 page 61 of 89 REJ03B0156-0121 Fig. 77 State transition 2 Operation clock source: On-chip oscillator (Note 2)Operation clock source: f(XIN) (Note 1) Notes on switch of clock (1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio. f(XIN)/2 (High-speed mode) f(XIN)/8 (Middle-speed mode) f(XIN) (Double-speed mode, only at a ceramic oscillation) (2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio. ROSC/1 (On-chip oscillator double-speed mode) ROSC/2 (On-chip oscillator high-speed mode) ROSC/8 (On-chip oscillator middle-speed mode) ROSC/128 (On-chip oscillator low-speed mode) (3) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation. (4) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’, ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock. (5) MCU cannot be returned by On-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected. Accordingly, do not execute the transition to state 2'a. (6) STP instruction cannot be used when oscillation stop detection circuit is in active. RESET state 2 f(XIN) oscillation: enabled On-chip oscillator: enabled RESET state 1 f(XIN) oscillation: enabled On-chip oscillator: enabled Oscillation stop detection circuit is in active. (Note 6) Applied “L” to RESET pin (external reset) MISRG3 is cleared to “0”. MISRG2=12 MISRG2=02 MISRG2=12 MISRG2=02 MISRG1=12 MISRG1=02 (MISRG3 is cleared to “0”.) MISRG1=12 (Note 3) MISRG1=02 (MISRG3 is cleared to “0”.) State 3State 2 f(XIN) oscillation: enabled On-chip oscillator: enabled f(XIN) oscillation: enabled On-chip oscillator: enabled State 3’State 2’ f(XIN) oscillation: enabled On-chip oscillator: enabled State 2’a (Note 5) Oscillation stop reset disabled When oscillation stop is detected; MISRG 3 is set to “1”. Internal RESET does not occur. Prohibitive state MUC will be locked when Ceramic or RC oscillation is stopped. State 3’a Oscillation stop reset disabled When oscillation stop is detected; MISRG 3 is set to “1”. Internal RESET does not occur. Oscillation stop reset enabled When oscillation stop is detected; MISRG 3 is set to “1”. Internal RESET occurs. Oscillation stop reset enabled When oscillation stop is detected; MISRG 3 is set to “1”. Internal RESET occurs. State 3’c Release from internal reset MISRG 3 is set to “1”. Oscillation status can be confirmed by reading MISRG f(XIN) oscillation: enabled On-chip oscillator: enabled State 3’bState 2’b CPUM76=102 (Note 4) CPUM76=002 012 112 (Note 3) CPUM76=102 CPUM76=002 012 112 CPUM76=102 (Note 4) CPUM76=002 012 112 Reset released (Note 4) Reset released (Note 4) Oscillation stop is detected (internal reset)

Rev.1.21 Nov 15, 2006 page 62 of 89 REJ03B0156-0121 Fig. 78 Assignment of Function set ROM area Fig. 79 Structure of Function set ROM data 0 Function set ROM invalid bit (Note 1) 0: Setting of bit 5 to bit 0 of function set ROM data 2 valid 1: Setting of bit 5 to bit 0 of function set ROM data 2 invalid Set “0” to these bits. Set “0” to this bit certainly. Low voltage detection circuit valid bit 0: Low voltage detection circuit invalid 1: Low voltage detection circuit valid Low voltage detection circuit valid bit in the stop mode (Note 2) 0: Low voltage detection circuit invalid in the stop mode 1: Low voltage detection circuit valid in the stop mode Set “1” to this bit. Function set ROM data 0 (FSROM0: address FFD816) 1000 0 Note 1: When “1” is set to this bit, the setting values of bit 5 to bit 0 of function set ROM data 2 become invalid, and these functions can be set by program. (this bit does not affect on other bits than bit 5 to bit 0 of function set ROM data 2.) 2: When the Low voltage detection circuit is set to be valid in the stop mode, the dissipation current in the stop mode is increased. Renesas shipment test area Renesas shipment test area Renesas shipment test area Renesas shipment test area Function set ROM data 0 Function set ROM data 2 Function set ROM data 1 ROM code protect Interrupt vector area Addres FFD4 FFD5 16 FFD6 16 FFD7 16 FFD8 16 FFD9 16 FFDA 16 FFDB 16 Note: The random data are written into the Renesas shipment test areas (address FFD4 16 to address FFD716). Do not rewrite the data of these areas. When checksum is included in user program, avoid assigning it to these areas. Fig. 81 Structure of Function set ROM data 2 Function set ROM data 1 FSROM1 (FFD916) b7 b0 Set “0” to these bits certainly. 0000 0 000 Watchdog timer start selection bit (Note 1) 0 : Watchdog timer starts automatically after reset 1 : Watchdog timer is inactive after reset On-chip oscillator control bit (Note 1) 0 : Stop of on-chip oscillator disabled 1 : Stop of on-chip oscillator enabled Watchdog timer source clock selection bit (Note 1) 0 : On-chip oscillator/16 1 : On-chip oscillator/16 or f(X IN)/16 Watchdog timer H count source selection bit (Note 1) 0 :Watchdog timer L underflow 1 : Count source of watchdog timer L (The clock selected by the watchdog timer source clock selection bit (bit 0)) STP instruction function selection bit (Note 1) 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation Function set ROM data 2 (FSROM2: address FFDA 16) Note 1: These functions can be active when “0” is set to function set ROM valid bit (bit 0 of function set ROM data 0). Set “0” to these bits certainly. Fig. 80 Structure of Function set ROM data 1 G Function set ROM Figure 78 shows the Assignment of Function set ROM area. The random data are written to the Renesas shipment test areas (addresses FFD4 16 to address FFD7 16). Do not rewrite the data of these areas. When the checksum is included in the user program, avoid as- signing it to these areas. The function set ROM data 0 to 2 (addresses FFD8 16 to FFDA16) are used to set the peripheral function. Data set to these areas become valid after releasing reset. The ROM code protect to disable the reading of the built-in QzROM area is assigned to address FFDB 16. [Function set ROM data] FSROM0, FSROM1, FSROM2 Function set ROM data 0 to 2 (addresses FFD8 16 to FFDA16) are used to set modes of peripheral functions. By setting values to these areas, the operation mode of each pe- ripheral function are set after releasing reset. Refer to the descriptions of peripheral functions for the details of operation of peripheral functions. - CPU mode register - Watchdog timer - Low voltage detection circuit When “1” is set to bit 0 of function set ROM data 0 (address FFD8 16), the written values to bit 5 to bit 0 of function set ROM data 2 (address FFDA 16) can become invalid. When the values of bit 5 to bit 0 of function set ROM data 2 (ad- dress FFDA 16) are invalid, the operation mode of the peripheral functions can be set by setting the related registers. [ROM code protect] By setting “0016” to ROM code protect (address FFDB 16), reading of the built-in QzROM by the serial programmer is disabled.

Rev.1.21 Nov 15, 2006 page 63 of 89 REJ03B0156-0121 The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is “1”. After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. Decimal Calculations

• For calculations in decimal notation, set the decimal mode flag D to “1”, then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD in- struction after executing one instruction before the ADC instruction or SBC instruction.
• In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. Ports
• The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory opera- tion instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA in- struction, etc. A/D Conversion Do not execute the STP instruction during A/D conversion. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles men- tioned in the machine-language instruction table. The frequency of the internal clock φ is the same as that of the X IN in double-speed mode, twice the X IN cycle in high-speed mode and 8 times the X IN cycle in middle-speed mode. CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is ex- cluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. State transition Do not stop the clock selected as the operation clock because of setting of CM3, 4. NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 µF to 0.1 µF is recommended.

Rev.1.21 Nov 15, 2006 page 64 of 89 REJ03B0156-0121 NOTES ON USE Countermeasures against noise 1. Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. <Reason> The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP , makes the total wir- ing length short to reduce influence of noise. (3) Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for oscillation from other V SS pat- terns. <Reason> If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in the microcomputer. (2) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20mm). <Reason> The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initial- ized. This may cause a program runaway. Fig. 84 Wiring for clock I/O pins Fig. 82 Selection of packages DIP SDIP SOP QFP Fig. 83 Wiring for the RESET pin RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. (4) Wiring to VPP pin Connect VPP pin to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to V SS. In order to improve the noise reduction, to connect a 5 k Ω resistor serially to the V PP pin - GND line may be valid. As well as the above-mentioned, in this case, connect to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to V SS. <Reason> The V PP pin of the QzROM is the power source input pin for the built-in QzROM. When programming in the built-in QzROM, the impedance of the V PP pin is low to allow the electric current for writing flow into the QzROM. Because of this, noise can enter eas- ily. If noise enters the V PP pin, abnormal instruction codes or data are read from the built-in QzROM, which may cause a program runaway. Fig. 85 Wiring for the V PP pin of the QzPROM About 5kΩ VSS The shortest The shortest CNVSS/VPP (Note) (Note) Note: This indicates pin.

Rev.1.21 Nov 15, 2006 page 65 of 89 REJ03B0156-0121 Fig. 86 Bypass capacitor across the VSS line and the VCC line 2. Connection of bypass capacitor across V SS line and VCC line Connect an approximately 0.1 µF bypass capacitor across the V SS line and the V CC line as follows:

• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the V CC pin. VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K. 3. Wiring to analog input pins
• Connect an approximately 100 Ω to 1 k Ω resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin. Besides, connect the capacitor to the Vss pin as close as possible. Also, connect the capacitor across the analog input pin and the Vss pin at equal length. <Reason> Signals which is input in an analog input pin (such as an A/D con- verter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring func- tions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Fig. 87 Analog signal line and a resistor and a capacitor Analog input pin VSS Noise Thermistor Microcomputer N.G. O.K. (Note) Note : The resistor is used for dividing resistance with a thermistor.
• The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be ob- tained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D con- version result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an ana- log input pin.

Rev.1.21 Nov 15, 2006 page 66 of 89 REJ03B0156-0121 4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a mi- crocomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows. <Reason> In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Installing oscillator away from signal lines where potential lev- els change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. <Reason> Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock wave- forms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines ➁ Installing oscillator away from signal lines where potential lev- els change frequently Fig. 88 Wiring for a large current signal line/Writing of signal lines where potential levels change frequently XI N XO U T VS S M Microcomputer Mutual inductance Large current GND XIN XO U T VS S C N T RDo not cross N.G. (3) Oscillator protection using Vss pattern As for a two-sided printed circuit board, print a Vss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring. Besides, separate this Vss pattern from other Vss patterns. Fig. 89 Vss pattern on the underside of an oscillator /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines XIN XOUT VSS An example of V SS patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the V SS line for oscillation from other VSS lines

Rev.1.21 Nov 15, 2006 page 67 of 89 REJ03B0156-0121

1. Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware>

• Connect a resistor of 100 Ω or more to an I/O port in series. <Software>
• As for an input port, read data several times by a program for checking whether input levels are equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods. Fig. 90 Setup for I/O ports 6. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal op- eration, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated mul- tiple times in a single main routine processing. Fig. 91 Watchdog timer by software <The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt process- ing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and de- termines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt process- ing.
• Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization routine for recovery process- ing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Main routine (SWDT)← N CLI Main processing (SWDT) Interrupt processing routine errors N Interrupt processing routine (SWDT) ← (SWDT)— 1 Interrupt processing (SWDT) Main routine errors ≤0 RTI Return =N? ≤0? Direction register Port latch Data bus I/O port pins Noise Noise N.G. O.K.

Rev.1.21 Nov 15, 2006 page 68 of 89 REJ03B0156-0121 ELECTRICAL CHARACTERISTICS of 7547 Group Absolute Maximum Ratings Absolute maximum ratings –0.3 to 6.5 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 300 –20 to 85 –40 to 125 Power source voltage Input voltage 0–P07, P10–P14, P20–P27, P30–P37, VREF Input voltage RESET, X IN Input voltage CNV SS Output voltage P00–P07, P10–P14, P20–P27, P30–P37, XOUT Power dissipation Operating temperature Storage temperature V V V V V mW V CC VI VI VI VO Pd Topr Tstg ConditionsSymbol Ratings UnitParameter All voltages are based on VSS. When an input voltage is mea- sured, output transistors are cut off. Ta = 25°C

Rev.1.21 Nov 15, 2006 page 69 of 89 REJ03B0156-0121 Recommended Operating Conditions Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter UnitLimits Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V CC VCC VCC VCC 0.2VCC 0.8 0.2VCC 0.16VCC –80 –40 4.5 4.0 2.4 2.2 4.0 2.4 2.2 4.0 2.4 2.2 1.8 1.8 0.8V CC 2.0 0.8VCC Power source voltage (Double-speed mode) (ceramic) (High-, Middle-speed mode) Power source voltage (High-, Middle-speed mode) (RC) Power source voltage (at on-chip oscillator) Power source voltage Analog reference voltage “H” input voltage 0–P07, P10–P14, P20–P27, P30–P37 “H” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) “H” input voltage RESET, XIN “L” input voltage P00–P07, P10–P14, P20–P27, P30–P37 “L” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) “L” input voltage RESET, CNVSS “L” input voltage XIN “H” total peak output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” total peak output current (Note 2) P10–P14, P20–P27 “L” total peak output current (Note 2) P00–P07, P30–P37 “H” total average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” total average output current (Note 2) P10–P14, P20–P27 “L” total average output current (Note 2) P00–P07, P30–P37 f(XIN) = 8 MHz f(XIN) = 6.5 MHz f(XIN) = 2 MHz f(XIN) = 1 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 1 MHz 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 V CC VSS VREF VIH VIH VIH VIL VIL VIL VIL ∑ IOH(peak) ∑ IOL(peak) ∑ IOL(peak) ∑ IOH(avg) ∑ IOL(avg) ∑ IOL(avg) V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA

Rev.1.21 Nov 15, 2006 page 70 of 89 REJ03B0156-0121 Recommended operating conditions (2) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) “H” peak output current (Note 1) P0 0–P07, P10–P14, P20–P27, P30–P37 “L” peak output current (Note 1) P0 0–P07, P30–P37 (Drive capacity = “L”) P10–P14, P20–P27 “L” peak output current (Note 1) P00–P07, P30–P37 (Drive capacity = “H”) “H” average output current (Note 2) P0 0–P07, P10–P14, P20–P27, P30–P37 “L” average output current (Note 2) P0 0–P07, P30–P37 (Drive capacity = “L”) P10–P14, P20–P27 “L” average output current (Note 2) P00–P07, P30–P37 (Drive capacity = “H”) Oscillation frequency (Note 3) at ceramic oscillation or external clock input CC = 4.5 V to 5.5 V) Double-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input CC = 4.0 V to 5.5 V) Double-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input CC = 2.4 V to 5.5 V) Double-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input CC = 2.2 V to 5.5 V) Double-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input CC = 4.0 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input (VCC = 2.4 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input CC = 2.2 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at RC oscillation CC = 4.0 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at RC oscillation CC = 2.4 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at RC oscillation CC = 2.2 V to 5.5 V) High-, Middle-speed mode Symbol Parameter Limits Max.Typ.Min. –10 6.5 Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit

Rev.1.21 Nov 15, 2006 page 71 of 89 REJ03B0156-0121

Electrical Characteristics

Electrical characteristics (1) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits UnitTest conditions V V V V V V V V V V V µA µA µA µA µA µA mA V kHz kHz Notes 1:P11 is measured when the P1 1/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B 16) is “0”. P05 is measured when the P0 5/TXD2 P-channel output disable bit of the UART2 control register (bit 4 of address 0031 16) is “0”. 2:RXD1, SCLK1, INT0, and INT1 (P36 selected) have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3:It is available only when operating key-on wake up. VCC–1.5 VCC–1.0 1.6 1000 62.5 “H” output voltage P00–P07, P10–P14, P20–P27, P30–P37 (Note 1) “L” output voltage P00–P07, P30–P37 (Drive capacity = “L”) P10–P14, P20–P27 “L” output voltage P00–P07, P30–P37 (Drive capacity = “H”) Hysteresis CNTR0, INT0, INT1, CAP0, CAP1 (Note 2) P00–P07 (Note 3) Hysteresis RXD0, SCLK0, RXD1, SCLK1 Hysteresis RESET “H” input current 0–P07, P10–P14, P20–P27, P30–P37 “H” input current RESET “H” input current XIN “L” input current P00–P07, P10–P14, P20–P27, P30–P37 “L” input current RESET “L” input current XIN “L” input current P00–P07, P30–P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 –5.0 –5.0 –0.5 5.5 3000 187.5 V OH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM ROSC DOSC 0.4 0.5 0.5 4.0 –4.0 –0.2 2000 125 IOH = –5 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 1.8 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 1.8 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 1.8 to 5.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS VI = VSS VI = VSS (Pull up transistors “on”) When clock stopped V CC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C

Rev.1.21 Nov 15, 2006 page 72 of 89 REJ03B0156-0121 Electrical characteristics (2) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits UnitTest conditions Note: Increment when A/D conversion is executed includes the reference power source input current (IV REF). f(XIN) = 8 MHz Output transistors “off” f(XIN) = 2 MHz, VCC = 2.2 V Output transistors “off” On-chip oscillator operation mode, Output transistors “off” f(X IN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(X IN) = 2 MHz, VCC = 2.2 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(X IN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors “off” Low voltage detection circuit self consumption current Double-speed mode High-speed mode Middle-speed mode High-speed mode Frequency/1 Frequency/2 Frequency/8 Frequency/128 Ta = 25 °C Ta = 85 °C Ta = 25 °C V CC = 5 V mA mA mA mA mA mA mA mA mA mA mA mA µA µA µA Power source current *LVD is valid (except at STP) 9.5 7.0 5.5 1.25 3.3 2.3 1.1 0.7 3.5 0.7 1.0 I CC 5.9 3.9 2.4 0.45 1.55 0.95 0.4 0.25 2.0 0.25 0.25 0.5 0.1

Rev.1.21 Nov 15, 2006 page 73 of 89 REJ03B0156-0121 A/D Converter Characteristics A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Resolution Absolute accuracy Conversion time Ladder resistor Reference power source input current A/D port input current Min. Typ. Max.Symbol Parameter Limits UnitTest conditions Bits LSB tc(XIN) kΩ µA µA ± 3 122 200 120 5.0 tCONV RLADDER IVREF II(AD) 150 Note: AD conversion accuracy may be low under the following conditions; (1) When the V REF voltage is set to be lower than the V CC voltage, an analog circuit in this microcomputer is affected by noise. The accuracy is lower than the case the V REF voltage is the same as V CC voltage. (2) When the V REF voltage is 3.0 V or less at the low temperature, the AD conversion accuracy may be very lower than at room temperature. When system is used at low temperature, that V REF is 3.0 V or more is recommended. Ta = 25 °C VCC = VREF = 2.7 to 5.5 V AD conversion clock = f(X IN)/2 AD conversion clock = f(X IN) VREF = 5.0 V VREF = 3.0 V

Rev.1.21 Nov 15, 2006 page 74 of 89 REJ03B0156-0121 Power-on reset circuit characteristics Power-on reset circuit characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Valid start voltage of power-on reset circuit (Note) VPOR hold time Rising time of valid power source of power-on reset circuit Min. Typ. Max.Symbol Parameter Limits UnitTest conditions mV s ms V POR TW(VPOR) TW(VPOR-VDET) Note: VPOR is the start voltage level of Vcc for the built-in power-on reset circuit to operate normally. Keep VPOR to be lower than the Vcc voltage before rising of the Vcc power source to use the built-in power-on reset circuit. Set the built-in low voltage detection circuit to be valid when the built-in power-on reset is used. TW(VPOR) > 10 s Low voltage detection circuit characteristics Low voltage detection circuit characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Valid start voltage of low voltage detection circuit (Note) VLVD hold time Rising time of valid power source of low voltage detection circuit Detection voltage of low voltage detection circuit Detection voltage Hysteresis (when hysteresis is valid) Detection time of low 5voltage detection circuit Min. 1.0 1.85 1.8 Typ. 1.95 1.95 0.1 Max.Symbol Parameter Limits UnitTest conditions V s s V V V µs 2.05 2.1 V LVD TW(VLVD) TW(VLVD-VDET) VDET- V(VDET+–VDET-) TDET Note: VLVD is the start voltage level of Vcc for the built-in low voltage detection circuit to operate normally. If the Vcc power source becomes lower than V LVD, first set the Vcc voltage to be lower than V POR. Next, according to the electrical characteristics of the power-on reset circuit, perform the rising of Vcc. TW(VLVD) > 10 s Ta = 0 to 50 °C Ta = –20 to 85 °C Ta = –20 to 85 °C Fig. 92 Electrical characteristics of power-on reset circuit and voltage drop detection circuit Vcc power source waveform VPOR TW(VPOR)T ( V PON-VDET) TDET TW(VLVD)T ( V LVD-VDET) NoteVDET+ VDET- Internal reset signal Power-on reset circuit characteristics Low voltage detection circuit characteristics Note: If the schmitt of the voltage drop detection circuit is set to be invalid, system is released from reset at the timing of rising to power source voltage VDET-. VPOR

Rev.1.21 Nov 15, 2006 page 75 of 89 REJ03B0156-0121 Table 22 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1) CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2) Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2) Serial I/O1, serial I/O2 input set up time Serial I/O1, serial I/O2 input hold time tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) 125 200 800 370 370 220 100 µs ns ns ns ns ns ns ns ns ns ns ns Table 23 Timing requirements (2) VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1) CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2) Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2) Serial I/O1, serial I/O2 input set up time Serial I/O1, serial I/O2 input hold time tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) 250 100 100 500 230 230 2000 950 950 400 200 µs ns ns ns ns ns ns ns ns ns ns ns Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A 16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 0030 16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A 16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 0030 16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.

Rev.1.21 Nov 15, 2006 page 76 of 89 REJ03B0156-0121 Table 24 Timing requirements (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1) CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2) Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2) Serial I/O1, serial I/O2 input set up time Serial I/O1, serial I/O2 input hold time tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) 500 200 200 1000 460 460 4000 1900 1900 800 400 µs ns ns ns ns ns ns ns ns ns ns ns Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A 16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 0030 16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.

Rev.1.21 Nov 15, 2006 page 77 of 89 REJ03B0156-0121 Table 25 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) tC(SCLK1)/2–30 tC(SCLK1)/2–30 –30 Min. Typ. Max. Symbol Parameter Limits Unit tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Serial I/O1, serial I/O2 clock output “H” pulse width Serial I/O1, serial I/O2 clock output “L” pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Table 26 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit 350 Note 1: Pin XOUT is excluded. tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Serial I/O1, serial I/O2 clock output “H” pulse width Serial I/O1, serial I/O2 clock output “L” pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) t C(SCLK1)/2–50 tC(SCLK1)/2–50 –30 ns ns ns ns ns ns ns ns 140 ns ns ns ns ns ns ns ns Table 27 Switching characteristics (3) VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit 450 Note 1: Pin XOUT is excluded. Switching characteristics measurement circuit diagram / / / Measured output pin CMOS output 100 pF tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Serial I/O1, serial I/O2 clock output “H” pulse width Serial I/O1, serial I/O2 clock output “L” pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) t C(SCLK1)/2–70 tC(SCLK1)/2–70 –30 ns ns ns ns ns ns ns ns

Rev.1.21 Nov 15, 2006 page 78 of 89 REJ03B0156-0121 Fig. 93 Timing chart 0.2VCC td(SCLK1-TxD1) tf 0.2 VCC 0.8VCC 0.8VCC tr tsu(RxD1-SCLK1)t h(SCLK1-RxD1) tv(SCLK1-TxD1) tC(SCLK1) tWL(SCLK1) tWH(SCLK1) RXD1 (at receive) SCLK1 0.2VCC tWL(XIN) 0.8VCC tWH(XIN) tC(XIN) XIN 0.2VCC 0.8 VCC tW(RESET) RESET 0.2VCC tWL(CNTR0) 0.8VCC tWH(CNTR0) tC(CNTR0) TXD1 (at transmit) CNTR0 0.2VCC tWL(INT0) 0.8VCC tWH(INT0) INT0, INT1 CAP0, CAP1

Rev.1.21 Nov 15, 2006 page 79 of 89 REJ03B0156-0121 y 0.10 e 0.8 c 0° 8° L 0.3 0.5 0.7 0 0.1 0.2 A 2.35 11.63 11.93 12.23 A2 2.05 E 8.2 8.4 8.6 D 14.8 15.0 15.2 Reference Symbol Dimension in Millimeters Min Nom Max 0.3 0.35 0.45 0.18 0.2 0.25 P-SSOP36-8.4x15-0.80 0.5g MASS[Typ.] 36P2R-DPRSP0036GA-B RENESAS CodeJEITA Package Code Previous Code 0.65 0.95 DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark 1 18 1936 F E HE D e bp A c Detail F L

Rev.1.21 Nov 15, 2006 page 80 of 89 REJ03B0156-0121 APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a re- set. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. <Reason> After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. Reset Initializing of flags Main program Fig. 3 Stack memory contents after PHP instruction execution 2. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, ex- ecute another instruction before executing the SEC , CLC , or CLD instruction. PLP instruction execution Fig. 1 Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), ex- ecute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its origi- nal status. Fig. 2 Sequence of PLP instruction execution (S) (S)+1 Stored PS 3. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4. Multiplication and Division Instructions (1) The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. (2) The execution of these instructions does not change the con- tents of the processor status register. 5. Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (SFR). The read-modify-write instruction operates in the following se- quence: read one-byte of data from memory, modify the data, write the data back to original memory. The following instructions are classified as the read-modify-write instructions in the 740 Family. (1) Bit management instructions: CLB, SEB (2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF (3) Add and subtract instructions: DEC, INC (4) Logical operation instructions (1 ’s complement): COM Add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = “1” operate in the way as the read- modify-write instruction. Do not execute the read invalid SFR. <Reason> When the read-modify-write instruction is executed to read invalid SFR, the instruction may cause the following consequence: the in- struction reads unspecified data from the area due to the read invalid condition. Then the instruction modifies this unspecified data and writes the data to the area. The result will be random data written to the area or some unexpected event. Set D flag to “1” ADC or SBC instruction NOP instruction SEC , CLC , or CLD instruction Fig. 4 Status flag at decimal calculations (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To de- termine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calcula- tion.

Rev.1.21 Nov 15, 2006 page 81 of 89 REJ03B0156-0121 NOTES ON PERIPHERAL FUNCTIONS Notes on I/O Ports 1. Port P0P3 drive capacity control register The number of LED drive port (drive capacity is HIGH) is 8. 2. Pull-up control register When using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected. <Reason> Pull-up control is effective only when each direction register is set to the input mode. 3. Notes in stand-by state In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”. Pull-up (connect the port to Vcc) or pull-down (connect the port to Vss) these ports through a resistor. When determining a resistance value, note the following points:

• External circuit
• Variation of output levels during the ordinary operation When using a built-in pull-up resistor, note on varied current val- ues:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external. <Reason> The output transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a mi- crocomputer is unstable in the state that input levels of an input port and an I/O port are “undefined ”. This may cause power source current. 1 stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction 4. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit manag- ing instruction* 2, the value of the unspecified bit may be changed. <Reason> The bit managing instructions are read-modify-write form instruc- tions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port : The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port : The bit value of the port latch is read in the CPU, and is written to this bit after bit managing. Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit man- aging instruction in case where the pin state differs from its port latch contents. 2 bit managing instructions : SEB , and CLB instructions

Rev.1.21 Nov 15, 2006 page 82 of 89 REJ03B0156-0121 5. Direction register The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory opera- tion instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS . It is also impossible to use bit operation instructions such as CLB and SEB and read-modify-write instructions of direction registers for calculations such as ROR . For setting direction registers, use the LDM instruction, STA in- struction, etc. Termination of Unused Pins 1. Terminate unused pins Perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. (1) I/O ports Set the I/O ports for the input mode and connect each pin to V CC or VSS through each resistor of 1 k Ω to 10 kΩ . The port which can select a built-in pull-up resistor can also use the built-in pull-up re- sistor. When using the I/O ports as the output mode, open them at “L” or “H”.

• When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the poten- tial at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the sys- tem, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. 2. Termination remarks (1) I/O ports setting as input mode [1] Do not open in the input mode. <Reason>
• The power source current may increase depending on the first- stage circuit.
• An effect due to noise may be easily produced as compared with proper termination (1) shown on the above “1. Terminate unused pins”. [2] Do not connect to V CC or VSS directly. <Reason> If the direction register setup changes for the output mode be- cause of a program runaway or noise, a short circuit may occur. [3] Do not connect multiple ports in a lump to V CC or VSS through a resistor. <Reason> If the direction register setup changes for the output mode be- cause of a program runaway or noise, a short circuit may occur between ports. Notes on Interrupts 1. Change of relevant register settings When not requiring for the interrupt occurrence synchronous with the following case, take the sequence shown in Figure 5.
• When switching external interrupt active edge
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Fig. 5 Sequence of changing relevant register <Reason> When setting the followings, the interrupt request bit of the corre- sponding interrupt may be set to “1”.
• When switching external interrupt active edge INT 0 interrupt edge selection bit (bit 0 of Interrupt edge selection register (address 3A 16)) INT1 interrupt edge selection bit (bit 1 of Interrupt edge selection register) CNTR 0 active edge switch bit (bit 2 of timer X mode register (address 2B 16)) Capture 0 interrupt edge selection bit (bits 1 and 0 of capture mode register (address 20 16)) Capture 1 interrupt edge selection bit (bits 3 and 2 of capture mode register) 2. Check of interrupt request bit When executing the BBC or BBS instruction to determine an in- terrupt request bit immediately after this bit is set to “0”, take the following sequence. <Reason> If the BBC or BBS instruction is executed immediately after an in- terrupt request bit is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. Set the corresponding interrupt enable bit to “0” (disabled) . Set the interrupt edge selection bit, active edge switch bit, or the interrupt source selection bit. NOP (One or more instructions) Set the corresponding interrupt request bit to “0” (no interrupt request issued). Set the corresponding interrupt enable bit to “1” (enabled). Set the interrupt request bit to “0” (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction Fig. 6 Sequence of check of interrupt request bit

Rev.1.21 Nov 15, 2006 page 83 of 89 REJ03B0156-0121

1. Interrupt discrimination bit Use an LDM instruction to clear to “0” an interrupt discrimination bit. LDM #%0000XXXX, $0B Set the following values to “X” “0”: an interrupt discrimination bit to clear “1”: other interrupt discrimination bits Ex.) When a key-on wakeup interrupt discrimination bit is cleared; LDM #%00001110 and $0B. 4. Interrupt discrimination bit and interrupt request bit For key-on wakeup, UART1 bus collision detection, A/D conver- sion and Timer 1 interrupt, even if each interrupt valid bit (interrupt source set register (address 0A 16)) is set “0: Invalid ”, each inter- rupt discrimination bit (interrupt source discrimination register (address 0B 16)) is set to “1: interrupt occurs ” when corresponding interrupt request occurs. But corresponding interrupt request bit (interrupt request registers 1, 2 (addresses 3C 16, 3D16) is not affected. Notes on Timers 1. When n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). 2. When a count source of timer X, timer A or timer B is switched, stop a count of the timer. Notes on Timer X 1. CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR 0 active edge switch bit (bit 2 of timer X mode register (address 2B 16)). When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at the falling edge of CNTR 0 pin input signal. When this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal. 2. Timer X count source selection The f(XIN) (frequency not divided) can be selected by the timer X count source selection bits (bits 1 and 0 of timer count source set register (address 2A 16)) only when the ceramic oscillation or the on-chip oscillator is selected. Do not select it for the timer X count source at the RC oscillation. 3. Pulse output mode Set the direction register of port P1 4, which is also used as CNTR 0 pin, to output. When the TXOUT pin is used, set the direction register of port P0 3, which is also used as TX OUT pin, to output. 4. Pulse width measurement mode Set the direction register of port P1 4, which is also used as CNTR 0 pin, to input. Notes on Timer A, B 1. Setting of timer value When “1: Write to only latch ” is set to the timer A (B) write control bit (bit 0 (bit 2) of timer X mode register (address 1D 16)), written data to timer register is set to only latch even if timer is stopped or operating. Accordingly, in order to set the initial value for timer when it is stopped, set “0: Write to latch and timer simultaneously ” to timer A (B) write control bit. 2. Read/write of timer A Stop timer A to read/write its data in the following state; X IN oscillation selected by clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B 16)), and the on-chip os- cillator output is selected as the timer A count source. 3. Read/write of timer B Stop timer B to read/write its data in the following state; X IN oscillation selected by clock division ratio selection bits, the timer A underflow is selected as the timer B count source, and the on-chip oscillator output is selected as the timer A count source.

Rev.1.21 Nov 15, 2006 page 84 of 89 REJ03B0156-0121 Notes on Output Compare 1. When the selected source timer of each compare channel is stopped, written data to compare register is loaded to the com- pare latch simultaneously. 2. Do not write the same data to both of compare latch x0 (x=0, 1, 2, 3) and x1. 3. When setting value of the compare register is larger than timer setting value, compare match signal is not generated. Accord- ingly, the output waveform is fixed to “L” or “H” level. However, when setting value of another compare register is smaller than timer setting value, this compare match signal is generated. Accordingly, if the corresponding compare latch y (y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to “1” (valid), compare match interrupt request occurs. 4. When the compare x trigger enable bit is cleared to “0” (dis- abled), the match trigger to the waveform output circuit is disabled. Accordingly, the output waveform can be fixed to “L” or “H” level. However, in this case, the compare match signal is generated. Accordingly, if the corresponding compare latch y (y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to “1” (valid),compare match interrupt request occurs. Notes on Input Capture 1. If the capture trigger is input while the capture register (low-or- der and high-order) is in read, captured value is changed between high-order reading and low-order reading. Accordingly, some countermeasure by program is recommended, for ex- ample comparing the values that twice of read. 2. Timer A cannot be used for the capture source timer in the fol- lowing state;

• X IN oscillation selected by clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B 16))
• Timer A count source: On-chip oscillator output. Timer B cannot be used for the capture source timer in the fol- lowing state;
• X IN oscillation selected by clock division ratio selection bits
• Timer B count source: Timer A underflow
• Timer A count source: On-chip oscillator output. 3. As shown below, when the capture input is performed to both capture latch 00 and 01 at the same time, the value of capture 0 status bit (bit 4 of capture/compare status register (address 16)) is undefined (same as capture 1).
• When “1” is written to capture latch 00 software trigger bit (bit 0 of capture software trigger register (address 13 16)) and capture latch 01 software trigger bit (bit 1 of capture software trigger reg- ister) at the same time
• When external trigger of capture latch 00 and software trigger of capture latch 01 occur at the same time
• When external trigger of capture latch 01 and software trigger of capture latch 00 occur at the same time 4. When the capture interrupt is used as the interrupt for return from stop mode, set the capture 0 noise filter clock selection bits (bits 5 and 4 of capture mode register (address 20 16)) to “00 (Filter stop) ” (same as capture 1).

Rev.1.21 Nov 15, 2006 page 85 of 89 REJ03B0156-0121

1. Notes common to clock synchronous serial I/O and UART (1) Set the serial I/Oi (i=1, 2) control register again after the trans- mission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” Fig. 7 Sequence of setting serial I/Oi control register again Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/Oi control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Notes on Serial I/Oi (i=1, 2) 1. Clock synchronous serial I/O (1) When the transmit operation is stopped, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled), the internal transmission is running (in this case, since pins TxD i, RxD i, S CLKi , and S RDYi function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/Oi enable bit is set to “1” at this time, the data during internally shifting is output to the TxD i pin and an operation failure occurs. (2) When the receive operation is stopped, clear the receive en- able bit to “0” (receive disabled), or clear the serial I/Oi enable bit to “0” (serial I/Oi disabled). (3) When the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) simultaneously. (any one of data transmis- sion and reception cannot be stopped.) <Reason> In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error oc- curs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also oper- ates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit cannot be initialized even if the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled) (same as (1)). (4) When signals are output from the S RDYi pin on the reception side by using an external clock, set all of the receive enable bit, the S RDYi output enable bit, and the transmit enable bit to “1”. (5) When the SRDYi signal input is used, set the using pin to the in- put mode before data is written to the transmit/receive buffer register. 2. UART When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled). <Reason> Same as (1) shown on the above “1. Clock synchronous serial I/O “. When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled). When the transmit/receive operation is stopped, clear the transmit enable bit to “0” (transmit disabled) and receive enable bit to “0” (receive disabled). (2) The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (3) When data transmission is executed at the state that an exter- nal clock input is selected as the synchronous clock, set “1” to the transmit enable bit while the S CLKi is “H” state. Also, write to the transmit buffer register while the S CLKi is “H” state. (4) When the transmit interrupt is used, set as the following se- quence. ➀ Serial I/Oi transmit interrupt enable bit is set to “0” (disabled). ➁ Serial I/Oi transmit enable bit is set to “1”. ➂ Serial I/Oi transmit interrupt request bit is set to “0” after 1 or more instructions have been executed. ➃ Serial I/Oi transmit interrupt enable bit is set to “1” (enabled). <Reason> When the transmit enable bit is set to “1”, the transmit buffer empty flag and transmit shift completion flag are set to “1”. Accordingly, even if the timing when any of the above flags is set to “1” is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. (5) Write to the baud rate generator (BRGi) while the transmit/re- ceive operation is stopped. Can be set with the LDM instruction at the same time

Rev.1.21 Nov 15, 2006 page 86 of 89 REJ03B0156-0121 Notes on Serial I/O1 1. I/O pin function when serial I/O1 is enabled. The pin functions of P1 2/SCLK1 and P13/SRDY1 are switched to as follows according to the setting values of a serial I/O1 mode selec- tion bit (bit 6 of serial I/O1 control register (address 1A 16)) and a serial I/O1 synchronous clock selection bit (bit 1 of serial I/O1 con- trol register). (1) Serial I/O1 mode selection bit → “1” : Clock synchronous type serial I/O is selected.

• Setup of a serial I/O1 synchronous clock selection bit “0” : P1 2 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock.
• Setup of a SRDY1 output enable bit (SRDY) “0” : P13 pin can be used as a normal I/O pin. “1” : P13 pin turns into a S RDY1 output pin. (2) Serial I/O1 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected.
• Setup of a serial I/O1 synchronous clock selection bit “0”: P1 2 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock.
• When clock asynchronous (UART) type serial I/O is selected, it functions P13 pin. It can be used as a normal I/O pin. Note on Bus Collision Detection When serial I/O1 is operating at half-duplex communication, set bus collision detection interrupt to be disabled. Notes on Serial I/O2 1. I/O pin function when serial I/O2 is enabled The pin functions of P0 6/SCLK2 and P07/SRDY2 are switched to as follows according to the setting values of a serial I/O2 mode selec- tion bit (bit 6 of serial I/O2 control register (address 30 16)) and a serial I/O2 synchronous clock selection bit (bit 2 of serial I/O2 con- trol register). (1) Serial I/O2 mode selection bit → “1” : Clock synchronous type serial I/O is selected.
• Setup of a serial I/O2 synchronous clock selection bit “0” : P0 6 pin turns into an output pin of a synchronous clock. “1” : P06 pin turns into an input pin of a synchronous clock.
• Setup of a SRDY2 output enable bit (SRDY) “0” : P07 pin can be used as a normal I/O pin. “1” : P07 pin turns into a S RDY2 output pin. (2) Serial I/O2 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected.
• Setup of a serial I/O2 synchronous clock selection bit “0”: P0 6 pin can be used as a normal I/O pin. “1”: P06 pin turns into an input pin of an external clock.
• When clock asynchronous (UART) type serial I/O is selected, it functions P07 pin. It can be used as a normal I/O pin.

Rev.1.21 Nov 15, 2006 page 87 of 89 REJ03B0156-0121

1. A/D conversion accuracy As for AD translation accuracy, on the following operating condi- tions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sen- sitive to noise when V REF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where V REF voltage and Vcc voltage are set up to the same value.. (2) When V REF voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at V REF=3.0 V or more is recom- mended. Notes on Watchdog Timer 1. The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer un- derflow. 2. The watchdog timer stops during the stop mode. However, the watchdog timer is running during the oscillation stabilizing time after the STP instruction is released. In order to avoid the un- derflow of the watchdog timer, the watchdog timer count source selection bit (bit 7 of watchdog timer control register (address 16)) before executing the STP instruction. 3. The STP instruction function selection bit (bit 6 of watchdog timer control register (address 39 16)) can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. Notes on RESET pin 1. Connecting capacitor In case where the RESET signal rise time is long, connect a ce- ramic capacitor or others across the RESET pin and the Vss pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following :

• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side. <Reason> If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer fail- ure. Notes on A/D conversion 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the user side. <Reason> An analog input pin includes the capacitor for analog voltage com- parison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion/comparison precision to be worse. 2. Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. This may cause the A/D conversion precision to be worse. Accordingly, set f(X IN) in order that the A/D conversion clock is 250 kHz or over during A/D conversion. 3. A/D conversion clock selection Select f(XIN)/2 as an A/D conversion clock by setting the A/D con- version clock selection bit (bit 3 of A/D control register (address 16)) when RC oscillation is used. The f(XIN) can be also used as an A/D conversion clock only when ceramic oscillation or on-chip oscillator is used. 4. Read A/D conversion register
• 8-bit read Read only the A/D conversion low-order register (address 35 16).
• 10-bit read Read the A/D conversion high-ordrer register (address 36 16) first, and then, read the A/D conversion low-order register (address 16). In this case, the high-order 6 bits of address 36 16 returns “0” when read.

Rev.1.21 Nov 15, 2006 page 88 of 89 REJ03B0156-0121 Notes on Clock Generating Circuit 1. Switch of ceramic and RC oscillations After releasing reset, the oscillation mode selection bit (bit 5 of CPU mode register (address 3B 16)) is “0” (ceramic oscillation se- lected). When the RC oscillation is used, after releasing reset, set this bit to “1”. 2. Double-speed mode The double-speed mode can be used only when a ceramic oscilla- tion is selected. Do not use it when an RC oscillation is selected. 3. CPU mode register Oscillation mode selection bit (bit 5), processor mode bits (bits 1 and 0) of CPU mode register (address 3B 16) are used to select os- cillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by erroneously writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting, it is disabled to write any data to the bit. (The emulator MCU “M37542RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB, etc.) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. 4. Clock division ratio, X IN oscillation control, on-chip oscillator control The state transition shown in Fig. 74 can be performed by setting the clock division ratio selection bits (bits 7 and 6), X IN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 74. 5. On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect X IN pin to VCC through a 1 kΩ to 10 kΩ resistor and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that this margin of frequencies when designing applica- tion products. 6. Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins X IN and XOUT at the shortest distance. Externally connect a damping resis- tor Rd depending on the oscillation frequency. A feedback resistor is built-in. Use the resonator manufacturer ’s recommended value because constants such as capacitance depend on the resonator. 7. RC oscillation When the RC oscillation is used for the main clock, connect the X IN pin and X OUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a micro- computer. So, set the constants within the range of the frequency limits. Notes on Oscillation Control 1. Oscillation stop detection circuit (1) When the stop mode is used, set the oscillation stop detection function to “invalid”. (2) When the ceramic or RC oscillation is stopped by the X IN oscil- lation control bit (bit 4 of CPU mode register (address 3B 16)), set the oscillation stop detection function to “invalid”. 2. Stop mode (1) When the stop mode is used, set the oscillation stop detection function to “invalid”. (2) When the stop mode is used, set “0” (STP instruction enabled) to the STP instruction function selection bit of the watchdog timer control register (bit 6 of watchdog timer control register (address 39 16)). (3) The oscillation stabilizing time after release of STP instruction can be selected from “set automatically ”/“not set automati- cally” by the oscillation stabilizing time set bit after release of the STP instruction (bit 0 of MISRG (address 38 16)). When “0” is set to this bit, “0116” is set to timer 1 and “FF16” is set to prescaler 1 automatically at the execution of the STP instruc- tion. When “1” is set to this bit, set the wait time to timer 1 and prescaler 1 according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. (4) Do not execute the STP instruction during the A/D conversion. 8. External clock When the external signal clock is used for the main clock, connect the X IN pin to the clock source and leave X OUT pin open. Select “0” (ceramic oscillation) to oscillation mode selection bit. 9. Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O, Serial I/O2, A/D converter, Watchdog timer) The count sources of these functions are affected by the clock di- vision selection bit of the CPU mode register. The f(X IN) clock is supplied to the watchdog timer when selecting f(XIN) as the CPU clock. The on-chip oscillator output is supplied to these functions when selecting the on-chip oscillator output as the CPU clock. However, the watchdog timer is also affected by the function set ROM.

Rev.1.21 Nov 15, 2006 page 89 of 89 REJ03B0156-0121 Notes on On-chip Oscillation Division Ratio

• When the clock division ratio is switched from f(X IN) to on-chip oscillator by the clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B 16)), the on-chip oscillator divi- sion ratio (bits 1 and 0 of on-chip oscillation division ratio selection register (address 37 16)) is “102” (on-chip oscillator middle-speed mode (R OSC/8)). Notes on Oscillation Stop Detection Circuit 1. After the reset by the oscillation stop detection, the value of fol- lowing bits are retained, not initialized.
• Ceramic or RC oscillation stop detection function active bit Bit 1 of MISRG (address 3B 16)
• Oscillation stop detection status bit Bit 3 of MISRG 2. Oscillation stop detection status bit is initialized ( “0”) by the fol- lowing operation.
• External reset
• Write “0” data to the ceramic or RC oscillation stop detection function active bit. 3. The oscillation stop detection circuit is not included in the emu- lator MCU “M37542RSS”. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Product shipped in blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 µF to 0.1 µF is recommended. NOTES ON QzROM Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .mask) which is made by the mask file converter MM. Be sure to set the ROM option ("MASK option" written in the mask file converter) setup when making the mask file by using the mask file converter MM. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. Renesas Technology corp. write the value of the ROM option setup data in the ROM code protect address (address FFDB 16) when writing to the QzROM. As a result, in the contents of the ROM code protect address the ordered value may differ from the actual written value. The ROM option setup data in the mask file is “00 16” for protect enabled or “FF16” for protect disabled. Therefore, the contents of the ROM code protect address (other than the user ROM area) of the QzROM product shipped after writing is “00 16” or “FF16”. Note that the mask file which has nothing at the ROM option data or has the data other than “0016” and “FF16” can not be accepted. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* * For the QzROM writing confirmation form and the mark specifi- cation form, refer to the “Renesas Technology Corp. ” Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer.

1.00 Oct 14, 2005

1.10 Jun 05, 2006

1.20 Aug 30, 2006

1.21 Nov 15, 2006

REVISION HISTORY

Rev. Date Description Page Summary A - 1

7547 Group Datasheet

“Preliminary” eliminated. Power dissipation added. Fig.1: part number added. Power source voltage (at on-chip oscillator) and power dissipation added. Memory expansion plan: “Under development” eliminated. Notes on use (2): $0Bn → $0B Notes on Input Capture; 2nd note: some description added. Block diagram of capture channel 0: address of capture pointer revised. Low Voltage Detection Circuit: bit number of the function set ROM data 0 revised. State transition: (4) revised. Wiring for the V PP pin of the QzPROM revised. Electrical characteristics (1) V RAM Min. value is added. Electrical characteristics (2) - Parameter The condition is added. - Limits Typ. and Max. values are changed. A/D Converter characteristics - Absolute accuracy Max. value is revised. Power-on reset circuit characteristics and Low voltage detection circuit added. Timing requirements is added. Switching characteristics is added. Timing chart added. 4.BRK instruction eliminated. Table 3: ROM size revised and note added. Notes on watchdog timer: note 3 revised. Notes on clock generating circuit: note added. 5. Setup for I/O ports: Note eliminated. Electrical characteristics (2) - Low voltage detection circuit self consumption current added. Low voltage detection circuit characteristics. - Unit of V LVD mV → V (1) Analog input pin: description revised. All f(X IN): VCC condition added. 2,4,6,79 75, 76 51, 87 56, 88

Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 RENESAS SALES OFFICES © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.0