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Rev. A, October 2003©2003 Fairchild Semiconductor Corporation Abstract An empirical self-heating SPICE MOSFET model which accurately portrays the verti- cal DMOS power MOSFET electrical and thermal responses is presented. This mac- romodel implementation is the culmination of years of evolution in MOSFET modeling. This new version brings together the thermal and the electrical models of a VDMOS MOSFET. The existing electrical model [2,3] is highly accurate and is recog- nized in the industry. Simulation response of the new self-heating MOSFET model track the dynamic thermal response and is independent of SPICE’s global tempera- ture definition. Existing models may be upgraded to self-heating models with relative ease. 1. Introduction Many power MOSFET models available today are based on an ideal lateral MOSFET device. They offer poor correlation between simulated and actual circuit performance in several areas. They have low and high current inaccuracies that could mislead power circuit designers. This situation is further complicated by the dynamic perfor- mance of the models. The ideal low power SPICE level-1 NMOS MOSFET model does not account for the nonlinear capacitive characteristics C iss, Coss, Crss of a power MOSFET. Higher level SPICE MOSFET models may be used to implement the non-linear capacitance with mixed results. The inherent inaccuracies of modeling a power VDMOS with the SPICE MOSFET model dictated the need for an alternative approach; a macro-model. A macro-model such as the one defined by Wheatley and Hepp [1] can address the short comings of the ideal low power SPICE MOSFET model. Highly accurate results are possible by surrounding the ideal level-1 MOSFET model with resistive, capaci- tive, inductive and other SPICE circuit elements. Two examples will illustrate the approach: 1) It was demonstrated in [3] that a third parallel MOSFET is required to accurately model the exponential relationship of drain current and gate-tosource voltage in the Application Note 7533 A Revised MOSFET Model With Dynamic Temperature Compensation Alain Laprade, Scott Pearson, Stan Benczkowski, Gary Dolny, Frank Wheatley October 2003
Rev. A, October 2003©2003 Fairchild Semiconductor Corporation sub-threshold region. 2) The implementation of the network (figure 1) using switches S1 and S2 provided a method to precisely model the non-linear capacitance. The result is an accurate rep- resentation of the dynamic transition between blocking and conduction. The need for this higher level modeling accuracy becomes apparent in high frequency applications where gate charge losses as a proportion of overall losses become sig- nificant. The same situation exists for the space charge limiting effect at high drain current. The MOSFET model reference on which this work is based has been explained in [1, 2, 3]. The reader is encouraged to refer to these references for a full understanding of the MOSFET model parameters herein referenced as the standard SPICE MOSFET model. Recent works [8, 9] have demonstrated methods of circumventing the SPICE global temperature definition, providing a means of using the device’s own junction tempera- ture as a self-heating feedback mechanism. The model developed in [8] has limitations involving proprietary algorithms, rendering the method of limited interest. Model implementation is convoluted, involving a MOS- FET analog behavioral model (ABM) implementation whose operating characteristics are dependent on a SPICE level-3 NMOS MOSFET. As a result, both the switching circuit and the load must be duplicated for the model to function. The implementation in [9] does not model the drain-source avalanche property of a MOSFET. Neither [8] nor [9] attempt to model the temperature characteristics of the intrinsic body diode. Introduced self-heating modeling concepts are non-proprietary and may be adapted to other MOSFET models. 2. Standard SPICE MOSFET Model The macro-model in Figure 1 is that used in numerous Fairchild MOSFET device models. It is the evolution of many years of work and improvements from numerous contributors [1-7]. A significant advantage of this model is that extensive knowledge of device physics or process details are not required for implementing parametric data within the model. The following data curves are the basis used to generate the macro- model model over temperature: - transfer characteristic - saturation characteristic
leled operation cannot be accurately modeled with a globally assigned temperature. Figure 1. Standard MOSFET macro-model dependent on global temperature definition
- Self-Heating SPICE MOSFET Model
- Self-Heating Model Implementation
junction temperature. PSPICE resistor ABMs do not permit voltage node references. mented without a resistor ABM. RDRAIN , RSOURCE , and RSLC1 . Figure 4. Implementing a voltage dependent ABM resistor model added to improve convergence. of the intrinsic body diode forward conduction drop.
heatsink at a temperature of 25oC. Figure 5. UIS simulation circuit the visual resolution of the data at the higher current range.
Figure 10. FDB038AN08A0 saturation voltage Conditions: VGS = 10V simulations if PSPICE’s setup option ABSTOL setting is less than 1µA. with virus scan software enabled. PSPICE Schematics version 9.1 was used. dynamic interaction of the junction temperature feedback.
- Future Model Developments
ature dependent current source across the body diode.
Rev. A, October 2003©2003 Fairchild Semiconductor Corporation 8. Conclusion The self heating PSPICE power MOSFET macromodel provides the next evolutionary step in circuit simulation accuracy. The inclusion of a thermal model coupled to the temperature sensitive MOSFET electrical parameters results in a selfheating PSPICE MOSFET macro-model which allows increased accuracy during time domain simula- tions. The effect of temperature change due to power dissipation during time domain simulations can now be modeled. The modeling modification concepts introduced are non-proprietary and may be adapted to MOSFET SPICE models from any manufac- turer. References [1] W.J. Hepp, C. F. Wheatley, “A New PSPICE Subcircuit For The Power MOSFET Featuring Global Temperature Options”, IEEE Transactions on Power Electronics Specialist Conference Records, 1991 pp. 533-544. [2] “A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options”, Fairchild Semiconductor, Application Note AN-7510, October 1999. [3] S. Benczkowski, R. Mancini, “Improved MOSFET Model”, PCIM, September 1998, pp. 64-69. sentation for Power MOSFETs Using Empirical Methods,” RCA Review”, Vol 46, Sept 1985. ware For Power MOSFET Modeling,” Fairchild Semiconductor, Application Note AN7506, February 1994. 5Volt Gate Drive Power MOSFET,” Power Electronics Specialist Conference Record, June 1984, p. 238. Gate-Voltage Propagation Effects In Power MOSFETs”, Proc. HFPC, May 1986, p. 146. [8] F. Di Giovanni, G. Bazzano, A. Grimaldi, ”A New PSPICE Power MOSFET Subcir- cuit with Associated Thermal Model“, PCIM 2002 Europe, pp. 271-276. [9] M. März, P . Nance, “Thermal Modeling of Power-electronic Systems”, Infineon Technologies, Application Note, mmpn_eng.pdf.
Rev. A, October 2003©2003 Fairchild Semiconductor Corporation Appendix I Standard MOSFET SPICE Model .SUBCKT FDP038AN06A0 2 1 3 *Nom Temp=25 deg C *7 February 2003 Ca 12 8 1.5e-9 Cb 15 14 1.5e-9 Cin 6 8 6.1e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 69.3 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 4.81e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.63e-9 RLgate 1 9 48.1 RLdrain 2 5 10 RLsource 3 7 46.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.0e-4 Rgate 9 20 1.36 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2.8e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/ +(1e-6*300),10))} + TRS2=2e-7 CJO=4.35e-9 M=5.4e-1 TT=1e-9 XTI=3.9) .MODEL DbreakMOD D (RS=7.0e-2 TRS1=5e-4 TRS2=1.0e-7) .MODEL DplcapMOD D (CJO=1.7e-9 IS=1e-30 N=10 M=0.47) .MODEL MmedMOD NMOS (VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1
Rev. A, October 2003©2003 Fairchild Semiconductor Corporation + L=1u W=1u RG=1.36 T_abs=25) .MODEL MstroMOD NMOS (VTO=4.00 KP=275 IS=1e-30 N=10 + TOX=1 L=1u W=1u T_abs=25) .MODEL MweakMOD NMOS (VTO=2.72 KP=0.03 IS=1e-30 N=10 + TOX=1 L=1u W=1u RG=13.6 RS=.1 T_abs=25) .MODEL RbreakMOD RES (TC1=9e-4 TC2=1e-7) .MODEL RdrainMOD RES (TC1=5.5e-2 TC2=3.2e-4) .MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5) .MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-6.7e-3 TC2=-1.5e-5) .MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 + VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 + VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 + VOFF=.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=.5 + VOFF=-1) .ENDS *Thermal Model Subcircuit .SUBCKT FDP038AN06A0_Thermal TH TL CTHERM1 TH 6 6.45e-3 CTHERM2 6 5 3e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 TL 1e-1 RTHERM1 TH 6 3.24e-3 RTHERM2 6 5 8.08e-3 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 1e-1 RTHERM5 3 2 1.1e-1 RTHERM6 2 TL 1.4e-1 .ends
Rev. A, October 2003©2003 Fairchild Semiconductor Corporation Appendix II Self-Heating MOSFET SPICE Model .SUBCKT FDP038AN06A0_5NODE 2 1 3 Tj Tcase ** Spice model for FDP038AN06A0 *7 February 2003 Ca 12 8 1.5e-9 Cb 15 14 1.5e-9 Cin 6 8 6.1e-9 EDbody 31 30 VALUE={IF(V(Tj,0)<175,-1.5E-3*V(Tj,0)+.03,-.2325)} Dbody 30 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RDBODY 30 7 1E15 G_Rdbody 7 31 VALUE={V(7,31)/(1.65e-3*(1+2.7E-3*(V(Tj,0)-25)+ +2E-7*PWR((V(Tj,0)-25),2)))} G_Rdbreak 32 7 VALUE={v(32,7)/(7.0e-2*(1+5e-4*(V(Tj,0)-25)+ +1e-7*PWR((V(Tj,0)-25),2)))} Ebreak 11 32 VALUE={69.3*(1+9.5E-4*(V(Tj,0)-25)+1e-7* +PWR((V(Tj,0)-25),2))} Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 VALUE={-6.7E-3*(V(Tj,0)-25)-1.5E-5*PWR((V(Tj,0)- +25),2)} Evtemp 20 6 VALUE={-2.5e-3*(V(Tj,0)-25)+1e-6*PWR((V(Tj,0)-25),2)} Lgate 1 9 4.81e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.63e-9 RLgate 1 9 48.1 RLdrain 2 5 10 RLsource 3 7 46.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD G_Rdrain 50 16 VALUE={V(50,16)/(1E-4*(1+5.5E-2*(v(Tj,0)-25)+ Rgate 9 20 1.36 G_RSLC1 5 51 VALUE={v(5,51)/(1e-6*(1+1E-3*(v(Tj,0)-25)+ +1E-5*pwr((v(Tj,0)-25),2)))} RSLC2 5 50 1e3 G_Rsource 8 7 VALUE={V(8,7)/(2.8E-3*(1+5e-3*(V(Tj,0)-25)+ +1e-6*pwr((V(Tj,0)-25),2)))} S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/ +(1e-6*300),10))} G_PDISS 0 TH+ VALUE={I(ESLC)*V(5,7) + I(EVTEMP)*V(9,7) +
Rev. A, October 2003©2003 Fairchild Semiconductor Corporation + I(EBREAK)*V(5,7) + I(EDBODY)*V(7,5)}CTHERM1 Tj 106 6.45E-3 CTHERM2 106 105 3e-2 CTHERM3 105 104 1.4e-2 CTHERM4 104 103 1.65e-2 CTHERM5 103 102 4.85e-2 CTHERM6 102 Tcase 1e-1 RTHERM1 Tj 106 3.24e-3 RTHERM2 106 105 8.08e-3 RTHERM3 105 104 2.28e-2 RTHERM4 104 103 1e-1 RTHERM5 103 102 1.1e-1 RTHERM6 102 Tcase 1.4e-1 .MODEL DbodyMOD D (T_ABS=25 IS=2.4E-11 N=1.04 CJO=4.35e-9 + M=0.54 TT=1.0e-9 XTI=3.9) .MODEL DbreakMOD D () .MODEL DplcapMOD D (CJO=1.7e-9 IS=1e-30 N=10 M=0.47) .MODEL MmedMOD NMOS (T_ABS=25 VTO=3.3 KP=9 IS=1e-30 + N=10 TOX=1 L=1u W=1u RG=1.36) .MODEL MstroMOD NMOS (T_ABS=25 VTO=4.0 KP=275 IS=1e-30 + N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (T_ABS=25 VTO=2.72 KP=0.03 + IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13.6 RS=.1) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 + VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 + VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 + VOFF=.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=.5 + VOFF=-1) .ENDS
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