7528AC

UPD7527A NEC | Alldatasheet

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4-Bit, Single-Chip NEC Electronics Inc. CMOS Microcomputers With FIP® Driver a Description © Vectored interrupts: one external, two internal The uPO7527A, .PD7528A, and uPO7SCG2BE are Abit, pet timer! bara single-chip CMOS microcomputers with the »PD7500 Standby function (HALT, STOP) architecture and FIP direct-drive capability. y tun zg C Data retention mode The uwPD7527A contains a 2048x8-bit ROManda128x ( Zero-cross detector on POg/INTO input (mask 4-bit RAM. The uPD7528A contains a 4096 x 8-bit ROM optional) and 160 x 4-bit RAM. CO. System clock (:PD7527A/7528A/75CG28E): on-chip The uPD7527A/28A contains two 4-bit general purpose, PO Oseillalor 4 ° d fechnology registers located outside RAM. The subroutine stack is = [ow power consumption implemented in RAM for greater depth and flexibility. ° The ¢PD7527A/28A typicall tes 67 instructi G Single power supply ne we ioe 'ypically executes 67 instructions —yPD7527A/7528A: 2.7 to 6.0V 3 with a 5ys instruction cycle time. —NeD75CG28E: 5.0V The uPD7527A/28A has one external and two internal edge-triggered hardware-vectored interrupts. It also Ordering Information contains an 8-bit timer/event counter and an 8-bit serial 9 jqSSSSCSSSCSCSSSC~CT SOM Frequency interface to help reduce software requirements. Number Package Type ‘of Operation Thirty-one high-voltage lines are organized into the bit HPO7S27AC/26AC~_42-pin plastic DIP B10 KH output port 2, the 4-bit output ports 3, 8, and 9, and the 4- wPO7527ACU /28ACU-“ 42-pin plastic shrink DIP 610 kHz bit 1/0 ports 4, 5, 10, and 11. PD750628E 42-pin ceramic piggyback DIP 500 kHz The low power consumption CMOS process allows the use of a power supply between 2.7 and 6.0. Current Pin Configurations consumption is less than 3.0 mA maximum, and can be further reduced inthe halt and stop power-down modes. —_,PD)7527A/28A, 42-Pin Plastic DIP or Shrink DIP ‘The yPD75CG28E Is a piggyback EPROM version of the uPD7527A/28A, Pin-compatible and — function- reser 7 =P Ys compatible with the final, masked versions of the sed oO eee uPD7527A/28A, the yPD75CG28E is used for prototyp- vonet] « SoH povso ing and for aiding in program development. Youn GS 38D poyst mad « whew Features od 7 36 D1 P3 rae 38 Pi Pay © 67 instructions psd @ at Bars C2 instruction cycle: msc & mhew — Internal clock: 3.3 48/600 kHz, 5 V ict: Me Sel — External clock: 3.3 48/600 kHz, 5V lane ge eg pe _ Upwardly compatible with the wPD7500 series peed te Shr product family P10, 15, 28 Pips, (1 4,096 x 8-bit ROM (uPD7528A /75CG28E) #105 Cf 16 apr 2,048 x B-bit ROM (4PD7527A) Prat] 17 zs pres C1 160 x 4-bit RAM (xPD7528A/75CG28E) | a= be asf Pe 428 x 4-bit RAM (uPD7527A) pra se she 0 361/O lines Yoo C2: nba © 3thigh-voltage output lines that can directly drive a ssoonua vacuum fluorescent display (FIP)

1 Can select either a pull-down resistor or open-drain

output per 31 high-voltage outputs (mask optional) FIP is the registered trademark for NEC's fluorescent indicator panel vacuum fiyorescent display) 027s (NECEL $00) 3-53

yuPD7527A/28A!75CG28E NEC Pin Configurations (cont) uPD75CG28E EPROM . F KI ie ‘Symbol Function uPD75CG28E, 42-Pin Ceramic Piggybac! j Yoo Connection to pin 21 of wPOTSCG2BE neser {7 TEP vss BNC Nocommection cud? PDTSCG28E 41 [1 PopinTo: 3-10, 21, Ao-Ato EPROM address output cada sofa POSER 24,25 vee d : p00 1 280 Yoo ° p eo 113, 15-19 ipl Data read input from the EPROM esd 6 So ThO uc a7 He % Vss Connection to EPROM GND pin mq? eg isda BP m 2» is Chip enable output a: as a TE ipenabioouped Pio 9 up s xis 36 P35 2 Vss Supplies EPROM OE signal rae NOE agen pre 2 Ay Program counter MSB output pau OTBOVS 3 Hes, Sr ee rayprout iz OE MON 3 Het % Yoo Supplies Veg to the EPROM Ps a rire 1 19 moe ioe Sa) oa a SEL ‘Mode select input pw qi b 20 CULUh—E a rrav— mH did, = Ph Fy Voo ‘Supplies high-level signal to MSEL Pim Os 3 176 2 Pe, cls ne ene aE Le Note: Pie” vesQis sO BP Pes (1) Output drivers on ports 2-5 and 8-11 are mask-optional. Accordingly, id: a asp either an open-drain output or a pulldown resistor can be solected La: ee ee a Vioao'Ss suitable for an output criver with a pulldown resistor. — (3) Ports 8-11 have high-current drive capability and can drive an LED th Pin Identification oroet Pin Functions, .PD7527A/28A and uPD7527A/28A and uPD75CG28E uPD75CG28E No. ‘Symbol Function RESET i RESET Reset input ; 2.3 ou, C12 Clock pins System reset (input).

4 VRE High-voltage predriver supply CL1, CL2

5 vi High-volt ition resistor st oan oa sue Connection to the RC oscillator. CL1 is the external =) P5gPS3 High-voliage 170 port 5 clock input. 10,12 P23, P2 High-voltage output port 2, and output VpRE P2;/PTOUT port trom timer / event counter (PTOUT) ae FipPidg High current igh-otage 170 par 10 Negative power supp iy for high-voltage output pre- 17-20 Prlp-Prig, High-voltage, high-current 170 port 11 rivers (for ports 2-5, 8-11). a Yoo Positive power supply VioaD 22-25 P99-P33 High-voltage, high-current output port 9 5e0 Pac, voltage high-curentoulpatporta Negative power supply for optional load resistors (pull- 26-29 High-voltage,high-current output port 8 eee down resistors) of high-voltage output drivers (for ports 30-33 Plo PayHigh-voltage |/O port 2-5, 8-11). This pin is only on the xPD7527A/28A. 34-37 P3p-P33 High-voltage output port 3 38 P03/SI 4-bit input of port 0; of serial data input P53-P59.

39 P02/S0_ (Si), serial data output (SO), serial clock

40 0;/SCK 1/0 (SCK), andexternal interupt input bit, high-voltage I/O port. 4 POp/INTO (INTO) or zero-cross detect input (POp).

2 Ves Ground P2-P23

bit, high-voltage output port 2. 3-54

PTOUT Pin Functions, .PD75CG28E EPROM Output port from the timer/event counter. MSEL P103-P109 Changes the addressing area of the external EPROM , . and the on-chip RAM (with a pull-down resistor). Con- 4-bit, high-voltage, high-current I/O port 10. Capable of |—_ necting a jumper between socket pins 27 (MSEL) and 28 bit set/reset by SPBL/RPBL instructions. (Vpp) selects uPD7527A mode (2-Kbyte EPROM, 128 x 4- bit RAM). Leaving MSEL open selects »PD7528A mode Ptig-Ptip (4-Kbyte EPROM, 160 x 4-bit RAM). 4bit, high-voltage, high-current |/O port 11. Capable of bit set/reset by SPBL/RPBL instructions. Ao-Ato v Output the low-order 11 bits of the program counter DD (PCo-PCi9). Used as EPROM address signals. Positive power supply. An 3 P93-P99 When MSEL is high level, Ay} outputs high-level signals. 4-bit, high-voltage, high-current output port 9. Capable When MSEL is open, Ay; outputs the MSB of the PC, of bit set/reset by SPBL/RPBL instructions. which is used as the most significant address signal of the 4-Kbyte EPROM 2732. P83-P89 4+it, high-voltage, high-current output port 8. Capable '0-!7 of bit set/reset by SPBL/RPBL instructions. Input data read from the EPROM. P43-P49, CE 4-bit, high-voltage I/O port 4. Outputs the chip enable signal to the EPROM. P33-P3q Vpp 4-bit, high-voltage output port 3. Pin 26 is electrically equivalent to the bottom Vpp pin and is used to supply Vcc to the EPROM. Pin 28 is elec- P0p-P03 trically equivalent to the bottom Vpp pin and is used to he high level signai to MSEL. Pin 1 connects t¢ Abit input port 0. PQp is also used as the zero-cross de- owt NPDISCG2BE. tos! " Sto tection input. si Vss | Pin 14 is electrically equivalent to the bottom Vgs pin in Serfal data Input. voltage, and is connected to the EPROM GND pin. Pin so 22s electrically equivalent to the bottom Vgs pin andis used to supply the OE signal to the EPROM. Serial data output. Instruction Set SCK Refer to the User's Manual. The instruction set appears 1/0 serial clock. also as subset A4 in the data sheet for the «PD7500 se- ries of single-chip microcomputers. INTO External interrupt input. Vss Ground. 3-55

yPD7527A/28A!75CG28E NEC Block Diagram, p.PD7527A/28A POS/INTO. POSER POSSI 7 a) wNT0, 4 0980 Oo TRL See Pe To] 7 Ee (= [= CE Kb a 3-56

Block Diagram, .PD75CG28E . poorer PoySEk poy st wa pes0 nt wee cst Treen as ' cet, cone Ceumer = FETE’: [k= Fort P2-Pey wncel LHe o Ep i i Poa cxcommmn | KLEE Ke mse [| ere =u Ce KD Piha 7 Ep nn arson (2 =] Ee a KEI TEE KD mm a ot oo Veo Yes ¥ss RESET Bufe Absolute Maximum Ratings Ta=25°C Power supply voltage, Vop =0.31047V Output current high, ports 3, 4. 8, 9 total. In =55mA Power supply voltage, Vigap (UPD7527A/28A) Vpp-40Vt0Vpp +0.3V Output current high, ports 2, 5, 10, T1total, lon =55mA Power supply voltage, Vere Vop—12V to Vp +0.3V Output current iow, per pin, lox. mA Input voltage, except ports 4, 5, 10, 11, Vin =0.3Vt0Vpp +0.3V Output current iow, all ports total. 1g, 15 mA Input voltage, ports 4, §, 10,11, Vin Vop-40VtoVpp +0.3V Operating temperature, Topt 10°C to +70°C Output voltage, except ports 2-5, 8-11, Vo =0.3Vt0Vpp +0.3V Storage temperature, Ts1g = 85°C to +150°C ‘Output voltage, ports 2-5, 8-11, Vo Vop-40V10Vpp +0.3V Comment: Exposing the device to stresses above those listed in Abso- Quins cuventhoh cera P0..Pslae mA, lute Maximum Ratings could cause permanent damage. The device is Gutput current high. per pin:PO1,POz:lox TMA gt meant to be operated under conditions outside the limits de- Output current high, per pin: ports 2-5, 8-11: lon =30mA scribed in the operational sections of the specification. Exposure to ——LLLLLLLS——L— SKS absolute maximum rating conditions for extended periods may affect device reliability. 3-67

Ta=—10°C to +70°C, Vpp = +2.7V106.0V —— Test ee ‘Test Parameter Symbol Min” Typ Max Unit Conditions Parameter Symbol_Min_ Typ Max Unt Conditions inputvottage, Vin 0 0.3Vp9 _V__ Porto, RESET Outputieakage lou =3__ wh _Vo=0V: PO;, PO ‘ow Vi 0 05 Vout Current. 1OW ou =10 WA Vp=Vp9~35V: Vus Voo-35 0.3Vpp V Ports4,5,10.11 rts 275, Be ~ Output leakage IoH1 3 pA Vo=Vpp; except 1 ). Heal to he ea an = ‘ ee current, high ports 4,5, 10, 11 Miwa Nopw bo lon 80 vA Vo=Vpp: ports 4, Viws_0.7Vo0 Yoo V Fars, 6, 1.1 5,10, 11 45Ve < — bov. Supply current, loot 40 3.0 mA Vpp=5V210%, COO ee rormal ration R=39kQ Vpo-0.5 Voo V Ports, 5, 10, 11; moral ope ie 2.7V< Vop< 04 10 mA Vpp=3¥. ay R=82ko Oupatvotage Vou POY, POs < — Supplyeurrent. tape 200 600 yA Vpp=5V210%, me ou Von < 60¥. HALT mode R=39kQ (Note 4) Iou=1.6mA (Note 6) 60 200 uA Vpp=3¥.

0.5 V PO, Pop, RR (Note

Io. =400 pA 210 640 WA Vpp=5V+10%, Output voltage. Vow Voo-2.0 V_ Ports 2-5, RK (Note 5) high lon=—4mA 67 230 WA Vpp=3V, (Note 1) R=82kQ (Note 5) Vop-20 V Ports é-ti, Supply current. ons O01 10 WA _Vpp=3V (Note 4) Igy= -10mA ‘STOP mode 040 AV p= p= 5V 10% z = y (Note 6) (Note 5) (po- 2.0 v rts 2-5, 749 uA Vnn=3V (Note 5) low= —2mA 7 30 vA Vpp=3V (Note 5) {Note 2) On-chip pull- AL 80 140-220. kKQ Vpp—Vigan=35V Vop-2.0 V_ Ports 8-11, Gownresistance loa= —5mA Note: {ote 2) (9) Vere =Vop ~9V£1V. The circuit in figure is recommended. Voo-10 V PO;,POz, (2 Vere =0V.Vpp=45V t060V. ie 3 ma (8) Vop=45V to60V. Voo-05.SOS*C«S*C*«i i Ps (4) Without zero-cross detector. los = 100 pA (©) With zero-cross detector. inputlearage yr SA VSO POg-POy (©) Ports 4,5, 10, 11are low tevel output or low level input. current, low (Note 4) Suu 40 uA Vin= OV; PO (Note 5) hug. 10 vA _Vin=0V; CLI Nua —10 pA Vin=Vpp-35V: ports 4,5, 10, 11 Inputieakage Iu 3 uA Viw=Voo: current, high P>Og-Po (Note 4) une 40 WA Vin=Voo; Pp (Note §) tus 10 vA _Vin=Voo: CL ium 80 WA Vin=Vpo. ports 4, 5,10, 11 3-58

tas bo 1) 5, tune 40 yA_Vin=Vop: P00. 05 PO, PO, luna 80 WA Yin Von: pos. TT {1 Vere = Von — 9V +1¥. The circuit in figure 6 Is recommended. (3) Ports 4, 5, 10, 11 are output off or low input. Figure 1. Recommended Circuit, uPD7527A/7528A Figure 2. Recommended Circuit, uPD75CG28E

• Bros.se wporscazs + B rosie.

Zero-Cross Detection Characteristics AC Characteristics uPD7527A/28A: Ta = — 10°C to +70°C, Vp =45V 106.0V uPD75CG2BE: Ta = — 10°C to +70°C, Vop = +5V 210% uPD7527A/28A tite Ta = 10°C to +70°C, Vo = 42.7 Vt06.0V Parameter Symbol Min Typ Max Unit —_ Conditions Cit Test Zero-cross Vzx(PP) 1 3 Vap A0coupled, Parameter Symbol Min Typ Max Unit —_ Conditions detection input C=0.1 uF Cydetme toy 3.3 200 aS Vpp=4.5Vt0 voltage (Note 1) 6.0v Zero-cross Vax ‘£100 mV 50Hzto60 Hz sine 0 uw accu wave OO __ sey POp event input fpp 0 610 KHz Vpp=4.5Vto Zero-cmss tx 45 1000 Hz frequency 6.0V detection input —_ Sa a frequency 0 290 KHz TT _ Paring rise thor ot ws Zero-Cross Detection Waveform te Pop input fal togr ots time kd POpinput pulse tp, 1.63 8 width, low some VA Vou) Pop input pulse teoy 0.72 ws Vpp=4.5V 10 ! | ‘azx width, high 6.0V ' i SCKcycletime tkcy 3.0 uS Input: Vpp=4.5V i i \\ | 106.0V i " ! ! 33 us Output: i Hl H | Vpp=4.5V to Zoro Grose LTO. 6.0V Sigel —H 69 ws _Input Note: pre rprteer peli intr hee dihynier re poaeraoper ac 8.0 ws Output Gueen owostigh an high tow nations ot ——OO_ OO oo Input signal, respectively. However It's possible tht the 2ero-croes detection SCK pulse tk 3.35 us Input Ines tonto ghand/orhigro-ow waralions) fhe AC np sig wth ow SS a ‘esos 38 ¥S_ Output StKpuse ky 14 1S Input: Vpp=4.5V Capacitance width, high 106.0V Ta = 25°C, Vop = OV, f = 1.0 MHz, Unmeasured pins returned to GND 155, ws Output; eee Vop=4.5V 10 Parameter Symbol Min Typ Max Unit Condition Sisetuptime tg 300 as Input Cy 15 pF PO, POs (to rising-edge capacitance ‘of SCK) Output Co 1% pF Pon? Sihoidtime tks; 450 1s capacitance OF Poa eo —_Catter rising- 35 pF Ports3,8,9 one ase) V0 ance OD EPP _ St lay Tes $50 ns Vop=45Vi0 Capacitance 36 pF Ports4,5, 10, 11 time (after 6.0V {faling-edge af —_ Ea 2001s INTO pulse tion 0 us width, high, low tio. RESET pulse tag, 10 us width, high, low tas 3-60

AC Characteristics (cont) Oscillation Characteristics uPD75CG28E »PD7527A/28A Ta= —10°Cto +70°C, Vop = +5V#10% Ty = -10°C to 470°C, Vop = 27 Vt0 60V Limits Test Parameter Symbol Min Typ Max Unit Conditons Parameter Symbol Min Typ Max Unit —_ Conditions System clock foo 900 400 600 Kh R= S0KD 22% Cycietime toy 4.0 200 ys oscillation Vpo = 45V to (Note) frequency 6ov POp event input tpg 0 500 kHz 9 350200 250 kHz R= 82 k0 2% frequency ‘System clock tc 0 610 kHz Vpp = 4.5Vto POp inputrise tron 02 us bo input 60V ‘ u a mes 0 200 kz POp input fall tpor 02 4s a or time CLtinputrise tcp Of ps width, high, low tpo, cu Inputfall tog O1 pe SCKcycletime tycy 3.0 HS Input ee ere in ¥ _ 40 us Output pwr Lad SK pulse, HS Output low (Note 2) with, low Cliinputt463.~S as Vp = a CLt input tH 163. 50 BS Vp = 45Vt0 SCK pulse ky 13 vs Input pulse width, 60V wiath, high high (Note 2) Sisetuptime tg 300 ns (torising-edge .PD75CG28E of SCK) Ta= = °C to +70°C, Vop =5V 10% ‘St hold time ks} 450 ns ints (ater rising- —_— Test bdge of SCR) Parameter Symbol Win. Typ Max Unit Conditions SOoutpudeay yo CCR SSST~CS*«temelock gg == 80000 SOD RR OKO RDM time (ater osciiation M0 50190 —KHz«-R=NOKQE2% falling-edge of frequency Sc) {Note 1) inTopuse tg SOS CSC*Sy ter ok Hg 0 500 —kHz width, high, Iow tio. CL input eee truancy Meal pulse fash, 10 us (Note 2) width gn Tow ARs inputs ton 02 8 Data input delay tacc 700 ons time (Note 2) time from a 9 address CLI input fall tor 02 ws ee. time (Note 2) Data input delay tog 700 ns Fe time from CE CLinput pulse toy, 0.8 50 us i width, high, low toy Input hold time — thy 0 ns ——— Sse after address Note: _—$—$——ue i i... (1) R, C (see figure 3). (2) Externai clock (see figure 4), Note: ( toy=2lteg or2ite Figure 3. Recommended RC Oscillator Circuit ‘AC Waveform Measurement Points (Except CL1) = = cu ou sscnoue| ©: C= 35pF 25% [3CI= 6oppmrc 3-61

Figure 4. Recommended External Clock Circuit Data Retention Mode Timing supply current (Note 1) der to access the upper 2-Kbytes of the 4-Kbyte EPROM. ‘voltage high uPD75CG28E connected with the 2732.

2 With zero-cross detector

Figure 6. Connection with the 2732 (uPD7527A Mode) Figure 7. Connection with the 2732 (uPD7528A Mode) Figure 8. EPROM Read Timing

1 Machine Cyle

Timing Waveforms . EPROM (uPD75CG28E only) Serial Interface wer Aon tL rt = — tke ce =x bad tsk | xsi, tee te {— ssovren ~stxs0 * f owwom Clock somo Wie tet- tow Interrupt Input ‘cLiinpat TE tenet tor Reser sonzee| woe ‘ro Reset Input PO input od ne tpoF 43-0010734, INTO peer Differences Among the yPD7527A/28AiCG28E PD7SCQ28E OTS27A yPD7526A Program memory 4Kbyte EPROM On-chip 2Kbyte On-chip 4 Kbyte (2732) ROM ROM ‘connectable ‘on top Data memory 160%4 128x4 160x4 (RAM) High-voltage ‘Allopen-drain On-chip load capacitor or open drain ‘output lines ‘outputs ‘output (dit by bit, mask optional) ‘Veoap pin No Zer0-cross Yes ‘Mask optional detection Package 42pin ceramic 42-pin plastic DIP piggyback DIP 42-pin plastic bottom pin shrink DIP ‘compatible with #P07527A/28A Powersupply 5V 27V106.0V 3-64