75229P

HUF75229P3 FAIRCHILD | Alldatasheet

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Technical content

Features

 44A, 50V  Low On-Resistance, rDS(ON) = 0.022Ω  Temperature Compensating PSPICE® Model  Thermal Impedance SPICE Model  Peak Current vs Pulse Width Curve  UIS Rating Curve  Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-220AB Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

Ordering Information

HUF75229P3 TO-220AB 75229P NOTE: When ordering use the entire part number. D G S DRAIN SOURCE GATE DRAIN (FLANGE) Data Sheet December 2001

©2001 Fairchild Semiconductor Corporation HUF75229P3 Rev. B Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS Drain Current Figure 5 A 0.6 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V (Figure 11) 50 - - V Gate to Source Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA (Figure 10) 2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = 45V, VGS = 0V - - 1 µA VDS = 40V, VGS = 0V, TC = 150oC - - 250 µA Gate to Source Leakage Current I GSS VGS = ±20V - - ±100 nA Drain to Source On Resistance r DS(ON) ID = 44A, VGS = 10V (Figure 9) 0.017 0.020 0.022 Ω Turn-On Time t ON VDD = 30V, ID ≅ 44A, R L = 0.68Ω , VGS = 10V, R GS = 9.1Ω (Figures 18, 19) - - 105 ns Turn-On Delay Time t d(ON) -1 2-n s Rise Time t r -5 8-n s Turn-Off Delay Time t d(OFF) -3 3-n s Fall Time t f -3 3-n s Turn-Off Time t OFF - - 100 ns Total Gate Charge Q g(TOT) VGS = 0V to 20V V DD = 30V, ID ≅ 44A, R L = 0.68Ω Ig(REF) = 1.0mA (Figures 13, 16, 17) -6 0 7 5 n C Gate Charge at 10V Q g(10) VGS = 0V to 10V - 35 43 nC Threshold Gate Charge Q g(TH) VGS = 0V to 2V - 2.0 2.5 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) - 1060 - pF Output Capacitance C OSS - 405 - pF Reverse Transfer Capacitance C RSS -9 5-p F Thermal Resistance Junction to Case R θJC (Figure 3) - - 1.66 oC/W Thermal Resistance Junction to Ambient R θJA TO-220 - - 62 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 44A - - 1.25 V Reverse Recovery Time t rr ISD = 44A, dISD /dt = 100A/µs- - 7 2 n s Reverse Recovered Charge Q RR ISD = 44A, dISD /dt = 100A/µs - - 120 nC HUF75229P3

©2001 Fairchild Semiconductor Corporation HUF75229P3 Rev. B SUBCKT HUF75229P3 2 1 3 ; rev 6/19/97 CA 12 8 1.72e-9 CB 15 14 1.52e-9 CIN 6 8 9.61e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 58.13 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.86e-9 LSOURCE 3 7 2.69e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1e-3 RGATE 9 20 1.52 RLDRAIN 2 5 10 RLGATE 1 9 26.9 RLSOURCE 3 7 28.6 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 13.85e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))} .MODEL DBREAKMOD D (RS = 2.14e- 1TRS1 = 9.62e- 4TRS2 = 1.23e-6) .MODEL DPLCAPMOD D (CJO = 13.5e-1 0IS = 1e-3 0N = 10 M = 0.85) .MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52) .MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = 1.94e-7) .MODEL RDRAINMOD RES (TC1 = 8.04e-2 TC2 = 1.37e-4) .MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -3.43e-3 TC2 = -1.63e-5) .MODEL RVTEMPMOD RES (TC1 = -1.35e- 3TC2 = 1.16e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.90 VOFF= -4.90) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.90 VOFF= -7.90) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= 2.50) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.50 VOFF= -0.50) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. + - + - RBREAK RVTEMP VBAT RVTHRES IT 17 18 S1A S1B S2A S2B CA CB EGS EDS MWEAK EBREAK DBODY RSOURCE SOURCE 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 1621 MMED MSTRO DRAIN LDRAIN RLDRAIN DBREAK DPLCAP ESLC RSLC1 RSLC2 GATE RGATE EVTEMP ESG LGATE RLGATE HUF75229P3

©2001 Fairchild Semiconductor Corporation HUF75229P3 Rev. B SPICE Thermal Model REV 16 June 97 HUF75229P3 CTHERM1 7 6 4.90e-7 CTHERM2 6 5 4.90e-4 CTHERM3 5 4 1.96e-3 CTHERM4 4 3 7.90e-3 CTHERM5 3 2 1.85e-1 CTHERM6 2 1 2.70 RTHERM1 7 6 1.10e-2 RTHERM2 6 5 3.30e-2 RTHERM3 5 4 1.64e-1 RTHERM4 4 3 7.90e-1 RTHERM5 3 2 3.60e-1 RTHERM6 2 1 1.60e-1 RTHERM4 RTHERM6 RTHERM5 RTHERM3 RTHERM2 RTHERM1 CTHERM4 CTHERM6 CTHERM5 CTHERM3 CTHERM2 CTHERM1

7 JUNCTION

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