SN65176B_07 TI | Alldatasheet
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SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D – JULY 1985 – REVISED APRIL 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Bidirectional Transceivers /C0068 Meet or Exceed the Requirements of ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27 /C0068 Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments /C0068 3-State Driver and Receiver Outputs /C0068 Individual Driver and Receiver Enables /C0068 Wide Positive and Negative Input/Output Bus Voltage Ranges /C0068 Driver Output Capability . . .±60 mA Max /C0068 Thermal Shutdown Protection /C0068 Driver Positive and Negative Current Limiting /C0068 Receiver Input Impedance. . . 12 kΩ Min /C0068 Receiver Input Sensitivity . . .±200 mV /C0068 Receiver Input Hysteresis. . . 50 mV Typ /C0068 Operate From Single 5-V Supply description/ordering information The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. They are designed for balanced transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27. The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or V CC = 0. These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (P) Tube of 50 SN75176BP SN75176BP 0°Ct o7 0°C SOIC (D) Tube of 75 SN75176BD 75176B0°C to 70°C SOIC (D) Reel of 2500 SN75176BDR 75176B SOP (PS) Reel of 2000 SN75176BPSR A176B PDIP (P) Tube of 50 SN65176BP SN65176BP –40°C to 105°C SOIC (D) Tube of 75 SN65176BD 65176BSOIC (D) Reel of 2500 SN65176BDR 65176B † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. R RE DE D VCC B A GND SN65176B ...D O R P PACKAGE SN75176B . . . D, P, OR PS PACKAGE (TOP VIEW) On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D – JULY 1985 – REVISED APRIL 2003
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description/ordering information (continued) The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 kΩ , an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV. The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers. Function Tables DRIVER INPUT ENABLE OUTPUTS D DE A B H H H L L H L H X L Z Z RECEIVER DIFFERENTIAL INPUTS ENABLE OUTPUT A –B RE R VID ≥ 0.2 V L H –0.2 V < VID < 0.2 V L ? VID ≤ –0.2 V L L X H Z Open L ? H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) logic diagram (positive logic) DE RE R B A Bus D
SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D – JULY 1985 – REVISED APRIL 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematics of inputs and outputs Output 85 Ω NOM TYPICAL OF RECEIVER OUTPUT Input/Output Port 960 Ω NOM 16.8 kΩ NOM TYPICAL OF A AND B I/O PORTS Driver input: R(eq) = 3 kΩ NOM Enable inputs: R(eq )= 8 kΩ NOM R (eq) = Equivalent Resistor R (eq) VCC EQUIVALENT OF EACH INPUT VCC Input 960 Ω NOM VCC GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D – JULY 1985 – REVISED APRIL 2003
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recommended operating conditions MIN TYP MAX UNIT VCC Supply voltage 4.75 5 5.25 V VIor VIC Voltage at any bus terminal (separately or common mode) VVI or VIC Voltage at any bus terminal (separately or common mode) V VIH High-level input voltage D, DE, and RE 2 V VIL Low-level input voltage D, DE, and RE 0.8 V VID Differential input voltage (see Note 4) ±12 V IOH High level output current Driver –60 mA IOH High-level output current Receiver –400 µA IOL Low level output current Driver 60 mAIOL Low -level output current Receiver 8 mA TA O perating free air temperature SN65176B –40 105 °CTA Operating free-air temperature SN75176B 0 70 NOTE 4: Differential input/output bus voltage is measured at the noninverting terminal A, with respect to the inverting terminal B.
SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D – JULY 1985 – REVISED APRIL 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS † MIN TYP ‡ MAX UNIT VIK Input clamp voltage II = –18 mA –1.5 V VO Output voltage IO = 0 0 6 V |VOD1 | Differential output voltage IO = 0 1.5 3.6 6 V |VOD2 | Differential output voltage R L = 100 Ω, See Figure 1 1/2 VOD1 or 2¶ VOD2 g R L = 54 Ω, See Figure 1 1.5 2.5 5 VOD3 Differential output voltage See Note 5 1.5 5 V ∆|VOD | Chan ge in magnitude R L =5 4Ω or 100Ω See Figure 1 ±02 V∆|VOD | gg of differential output voltage§ R L = 54 Ω or 100 Ω , See Figure 1 ±0.2 V VOC Common mode out put voltage R L =5 4Ω or 100Ω See Figure 1 +3 VVOC Common -mode output voltage R L = 54 Ω or 100 Ω , See Figure 1 –1 V ∆|VOC | Chan ge in magnitude R L =5 4Ω or 100Ω See Figure 1 ±02 V∆|VOC | gg of common-modeoutput voltage§ R L = 54 Ω or 100 Ω , See Figure 1 ±0.2 V IO Output current Output disabled, VO = 12 V 1 mAIO Output current , See Note 6 VO = –7 V –0.8 mA IIH High-level input current VI = 2.4 V 20 µA IIL Low-level input current VI = 0.4 V –400 µA VO = –7V –250 IOS Short circuit output current VO = 0 –150 mAIOS Short-circuit output current VO = VCC 250 mA VO = 12 V 250 ICC Supply current (totalpackage) No load Outputs enabled 42 70 mAICC Supply current (total package) No load Outputs disabled 26 35 mA † The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs. ‡ All typical values are at VCC = 5 V and TA = 25°C. § ∆|VOD | and ∆|VOC | are the changes in magnitude of VOD and VOC , respectively, that occur when the input is changed from a high level to a low level. ¶ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater. NOTES: 5. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2. 6. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for a combined driver and receiver terminal. switching characteristics, VCC = 5 V, RL = 110 Ω , TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(OD) Differential-output delay time R L = 54 Ω , See Figure 3 15 22 ns tt(OD) Differential-output transition time R L = 54 Ω , See Figure 3 20 30 ns tPZH Output enable time to high level See Figure 4 85 120 ns tPZL Output enable time to low level See Figure 5 40 60 ns tPHZ Output disable time from high level See Figure 4 150 250 ns tPLZ Output disable time from low level See Figure 5 20 30 ns
SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D – JULY 1985 – REVISED APRIL 2003
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DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A VO Voa, Vob Voa, Vob |VOD1 | Vo Vo |VOD2 | Vt (RL = 100 Ω ) Vt (RL = 54 Ω ) |VOD3 | Vt (test termination|VOD3 | t( measurement 2) VOC |Vos| |Vos| IOS |Isa|, |Isb| IO |Ixa|, |Ixb| Iia, Iib RECEIVER SECTION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2‡ V Vhys Input hysteresis voltage (VIT+ – VIT–) 50 mV VIK Enable Input clamp voltage II = –18 mA –1.5 V VOH High level output voltage VID = 200 mV, IOH = –400 µA, 27 VVOH High-level output voltage ID , See Figure 2 OH µ , 2.7 V VOL Low level output voltage VID = –200 mV, IOL = 8 mA, 04 5 VVOL Low -level output voltage ID , See Figure 2 OL , 0.45 V IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA II Line input current Other input = 0 V, VI = 12 V 1 mAII Line input current , See Note 7 VI = –7 V –0.8 mA IIH High-level enable input current VIH = 2.7 V 20 µA IIL Low-level enable input current VIL = 0.4 V –100 µA rI Input resistance VI = 12 V 12 kΩ IOS Short-circuit output current –15 –85 mA ICC Supply current (totalpackage) No load Outputs enabled 42 55 mAICC Supply current (total package) No load Outputs disabled 26 35 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only. NOTE 7: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.
Figure 1. Driver VOD and VOC Figure 2. Receiver VOH and VOL
1.5 VInput
NOTES: A. C L includes probe and jig capacitance. Figure 3. Driver Test Circuit and Voltage Waveforms
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0 V or 3 V
NOTES: A. C L includes probe and jig capacitance. Figure 4. Driver Test Circuit and Voltage Waveforms
3 V or 0 V
NOTES: A. C L includes probe and jig capacitance. Figure 5. Driver Test Circuit and Voltage Waveforms NOTES: A. C L includes probe and jig capacitance. Figure 6. Receiver Test Circuit and Voltage Waveforms
0.5 VOutput
NOTES: A. C L includes probe and jig capacitance. Figure 7. Receiver Test Circuit and Voltage Waveforms
SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D – JULY 1985 – REVISED APRIL 2003
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VOH – High-Level Output Voltage – V DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT VCC = 5 V 4.5 3.5 2.5 1.5 0.5 –120 IOH – High-Level Output Current – mA VOH TA = 25°C Figure 9 DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VCC = 5 V TA = 25°C IOL – Low-Level Output Current – mA 0 120 20 40 60 80 100 0.5 1.5 2.5 3.5 4.5 – Low-Level Output Voltage – VVOL VOD – Differential Output Voltage – V DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT 3.5 2.5 1.5 0.5 908070605040302010 100 IO – Output Current – mA VOD VCC = 5 V TA = 25°C Figure 10
SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D – JULY 1985 – REVISED APRIL 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VO – Output Voltage – V RECEIVER OUTPUT VOLTAGE vs ENABLE VOLTAGE VCC = 5 V VCC = 5.25 V TA = 25°C VID = 0.2 V VI – Enable Voltage – V 30.5 1 1.5 2 2.5 VO Load = 8 kΩ to GND VCC = 4.75 V Figure 16 VO – Output Voltage – V RECEIVER OUTPUT VOLTAGE vs ENABLE VOLTAGE 2.521.510.5 VI – Enable Voltage – V VO Load = 1 kΩ to VCC VCC = 5 V VCC = 5.25 V TA = 25°C VID = –0.2 V VCC = 4.75 V
APPLICATION INFORMATION
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO ). Stub lengths off the main line should be kept as short as possible. Figure 17. Typical Application Circuit
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN65176BD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65176BPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75176BD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75176BPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75176BPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2006 Addendum-Page 1
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2006 Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 1
Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN65176BDR D 8 FMX 330 12 6.4 5.2 2.1 8 12 Q1 SN75176BDR D 8 FMX 330 12 6.4 5.2 2.1 8 12 Q1 SN75176BPSR PS 8 MLA 330 16 8.2 6.6 2.5 12 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65176BDR D 8 FMX 338.1 340.5 20.64 SN75176BDR D 8 FMX 338.1 340.5 20.64 SN75176BPSR PS 8 MLA 342.9 336.6 28.58 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3
MPDI001A – JANUARY 1995 – REVISED JUNE 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.015 (0,38) Gage Plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM MAX 0.430 (10,92) 4040082/D 05/98 0.200 (5,08) MAX 0.125 (3,18) MIN 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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