SN74VMEH22501A TI | Alldatasheet
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/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Member of the Texas Instruments Widebus Family /C0068UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes /C0068OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference (EMI) /C0068Compliant With VME64, 2eVME, and 2eSST Protocols /C0068Bus Transceiver Split LVTTL Port Provides Feedback Path for Control and Diagnostics Monitoring /C0068I/O Interfaces Are 5-V Tolerant /C0068B-Port Outputs (−48 mA/64 mA) /C0068Y and A-Port Outputs (−12 mA/12 mA) /C0068Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion /C0068Bus Hold on 3A-Port Data Inputs /C006826-/C0087 Equivalent Series Resistor on 3A Ports and Y Outputs /C0068Flow-Through Architecture Facilitates Printed Circuit Board Layout /C0068Distributed VCC and GND Pins Minimize High-Speed Switching Noise /C0068Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II /C0068ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP − DGG Tape and reel SN74VMEH22501ADGGR VMEH22501A −40°C to 85°C TVSOP − DGV Tape and reel SN74VMEH22501ADGVR VK501A−40 C to 85C VFBGA − GQL Tape and reel SN74VMEH22501AGQLR VK501A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Motorola is a trademark of Motorola, Inc. OEC, UBT, and Widebus are trademarks of Texas Instruments. 1OEBY GND VCC 2OEBY 3A1 GND LE 3A2 3A3 OE GND 3A4 CLKBA VCC 3A5 3A6 GND 3A7 3A8 DIR 1OEAB V CC GND BIAS V CC V CC 2OEAB 3B1 GND V CC 3B2 3B3 V CC GND 3B4 CLKAB V CC 3B5 3B6 GND 3B7 3B8 V CC DGG OR DGV PACKAGE (TOP VIEW) /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued) The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBT transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320 † backplane topologies. The SN74VMEH22501A is pin-for-pin capatible to the VMEH22501, but operates at a wider operating temperature (−40°C to 85°C) range. High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (1/2 V CC ±50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane. All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for live-insertion applications using I off, power-up 3-state, and BIAS VCC . The Ioff circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS V CC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. When V CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied to VCC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input. † VME320 is a patented backplane construction by Arizona Digital, Inc. terminal assignments 123456 A 1OEBY NC NC NC NC 1OEAB B 1Y 1A GND GND VCC 1B C 2Y 2A VCC VCC BIAS VCC 2B D 3A1 2OEBY GND GND 2OEAB 3B1 E 3A2 LE VCC 3B2 F 3A3 OE VCC 3B3 G 3A4 CLKBA GND GND CLKAB 3B4 H 3A5 3A6 VCC VCC 3B6 3B5 J 3A7 3A8 GND GND 3B8 3B7 K DIR NC NC NC NC VCC NC − No internal connection GQL PACKAGE (TOP VIEW) 123456 A B C D E F G H J K
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional description The SN74VMEH22501A is a high-drive (–48/64 mA), 8-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true logic. The device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus transceivers. functional description for two 1-bit bus transceivers The OEAB inputs control the activity of the 1B or 2B port. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are disabled. Separate 1A and 2A inputs and 1Y and 2Y outputs provide a feedback path for control and diagnostics monitoring. The OEBY inputs control the 1Y or 2Y outputs. When OEBY is low, the Y outputs are active. When OEBY is high, the Y outputs are disabled. The OEBY and OEAB inputs can be tied together to form a simple direction control where an input high yields A data to B bus and an input low yields B data to Y bus. 1-BIT BUS TRANSCEIVER FUNCTION TABLE INPUTS OUTPUT MODE OEAB OEBY OUTPUT MODE L H Z Isolation H H A data to B bus True driverL L B data to Y bus True driver H L A data to B bus, B data to Y busTrue driver with feedback path
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
the low-to-high transition of CLKAB. The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA. † 3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA. The UBT transceiver can replace any of the functions shown in Table 1. Table 1. SN74VMEH22501A UBT Transceiver Replacement Functions
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) CLK CLK 3B1 CLKAB LE CLKBA 3A1 To Seven Other Channels OE DIR 1OEAB 1OEBY 2OEAB 2OEBY Pin numbers shown are for the DGG and DGV packages.
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high-impedance Voltage range applied to any output in the high or low state, VO † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Notes 3 and 4) MIN TYP MAX UNIT VCC , BIAS VCC Supply voltage 3.15 3.3 3.45 V VI Input voltage Control inputs or A port VCC 5.5 VVI Input voltage B port VCC 5.5 V VIH High-level input voltage Control inputs or A port 2 VVIH High-level input voltage B port 0.5 VCC + 50 mV V VIL Low-level input voltage Control inputs or A port 0.8 VVIL Low-level input voltage B port 0.5 VCC − 50 mV V IIK Input clamp current −18 mA IOH High-level output current 3A port and Y output −12 mAIOH High-level output current B port −48 mA IOL Low-level output current 3A port and Y output 12 mAIOL Low-level output current B port 64 mA ∆t/∆v Input transition rise or fall rateOutputs enabled 10 ns/V ∆t/∆VCC Power-up ramp rate 20 µs/V TA Operating free-air temperature −40 85 °C NOTES: 3. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first.
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range for A and B ports (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 3.15 V, II = −18 mA −1.2 V 3A port, any B ports, and Y outputs VCC = 3.15 V to 3.45 V, IOH = −100 µA VCC −0.2 VOH 3A port and Y outputs VCC = 3.15 V IOH = −6 mA 2.4 VVOH 3A port and Y outputs VCC = 3.15 V IOH = −12 mA 2 V Any B port VCC = 3.15 V IOH = −24 mA 2.4 Any B port VCC = 3.15 V IOH = −48 mA 2 3A port, any B ports, and Y outputs VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2 3A port and Y outputs VCC = 3.15 V IOL = 6 mA 0.55 VOL 3A port and Y outputs VCC = 3.15 V IOL = 12 mA 0.8 VVOL IOL = 24 mA 0.4 V Any B port VCC = 3.15 V IOL = 48 mA 0.55Any B port VCC = 3.15 V IOL = 64 mA 0.6 II Control inputs, VCC = 3.45 V, VI = VCC or GND ±1 AII Control inputs, 1A and 2A VCC = 0 or 3.45 V, VI = 5.5 V 5 µA IOZH ‡ 3A port, any B port, and Y outputs VCC = 3.45 V, VO = VCC or 5.5 V 5 µA IOZL ‡ 3A port and Y outputs VCC = 3.45 V, VO = GND AIOZL ‡ Any B port VCC = 3.45 V, VO = GND −20 µA Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V ±10 µA IBHL § 3A port VCC = 3.15 V, VI = 0.8 V 75 µA IBHH ¶ 3A port VCC = 3.15 V, VI = 2 V −75 µA IBHLO # 3A port VCC = 3.45 V, VI = 0 to VCC 500 µA IBHHO || 3A port VCC = 3.45 V, VI = 0 to VCC −500 µA IOZ(PU/PD)/C0107 VCC ≤ 1.3 V, VO = 0.5 V to VCC , VI = GND or VCC , OE = don’t care ±10 µA † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For I/O ports, the parameters IOZH and IOZL include the input leakage current. § The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND, then raising it to VIL max. ¶ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC , then lowering it to VIH min. # An external driver must source at least IBHLO to switch this node from low to high. ||An external driver must sink at least IBHHO to switch this node from high to low. /C0107High-impedance state during power up or power down
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range for A and B ports (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VCC = 3.45 V, IO = 0, Outputs high 30 ICC VCC = 3.45 V, IO = 0, VI = VCC or GND Outputs low 30 mAICC VI = VCC or GND Outputs disabled 30 mA ICCD VCC = 3.45 V, IO = 0, VI = VCC or GND, One data input switching at Outputs enabled 76 µA/ clockICCD IC C One data input switching at one-half clock frequency, 50% duty cycle Outputs disabled 19 clock MHz/ input ∆ICC /C0104 VCC = 3.15 V to 3.45 V, One input at VCC − 0.6 V, Other inputs at VCC or GND 750 µA C i 1A and 2A inputs VI = 3.15 V or 0 2.8 pFC i Control inputs VI = 3.15 V or 0 2.6 pF C o 1Y or 2Y outputs VO = 3.15 V or 0 5.6 pF C io 3A port VCC = 3.3 V, VO = 3.3 V or 0 7.9 pFC io Any B port VCC = 3.3 V, VO = 3.3 V or 0 11 12.5 pF † All typical values are at VCC = 3.3 V, TA = 25°C. /C0104This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. live-insertion specifications over recommended operating free-air temperature range for B port PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT ICC (BIAS VCC ) VCC = 0 to 3.15 V, BIAS VCC = 3.15 V to 3.45 V,IO(DC) = 0 5 mA ICC (BIAS VCC ) VCC = 3.15 V to 3.45 V‡, BIAS VCC = 3.15 V to 3.45 V,IO(DC) = 0 10 µA IO VCC = 0 VO = 0, BIAS VCC = 3.15 V −20 −100 AIO VCC = 0 VO = 3 V, BIAS VCC = 3.15 V 20 100 µA † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ VCC − 0.5 V < BIAS VCC
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating conditions for UBT transceiver (unless otherwise noted) (see Figures 1 and 2) MIN MAX UNIT fclock Clock frequency 120 MHz tw Pulse duration LE high 2.5 nstw Pulse duration CLK high or low 3 ns 3A before CLK↑ Data high 2.1 3A before CLK↑ Data low 2.2 3A before LE↓ CLK high 2 tsu Setup time 3A before LE↓ CLK low 2 nstsu Setup time 3B before CLK↑ Data high 2.5 ns 3B before CLK↑ Data low 2.7 3B before LE↓ CLK high 2 3B before LE↓ CLK low 2 3A after CLK↑ Data high 0 3A after CLK↑ Data low 0 3A after LE↓ CLK high 1 th Hold time 3A after LE↓ CLK low 1 nsth Hold time 3B after CLK↑ Data high 0 ns 3B after CLK↑ Data low 0 3B after LE↓ CLK high 1 3B after LE↓ CLK low 1 switching characteristics over recommended operating conditions for bus transceiver function (unless otherwise noted) (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT tPLH 1A or 2A 1B or 2B 4.8 8.9 nstPHL 1A or 2A 1B or 2B 4.5 7.8 ns tPLH 1A or 2A 1Y or 2Y 6.2 14.5 nstPHL 1A or 2A 1Y or 2Y 6.1 13 ns tPZH OEAB 1B or 2B 3.9 8.1 nstPZL OEAB 1B or 2B 3.7 7.4 ns tPHZ OEAB 1B or 2B 3.3 9.7 ns tPLZ OEAB 1B or 2B 1.8 4.8 ns tr Transition time, B port (10%−90%) 4.3 ns tf Transition time, B port (90%−10%) 4.3 ns tPLH 1B of 2B 1Y or 2Y 1.6 5.6 nstPHL 1B of 2B 1Y or 2Y 1.6 5.6 ns tPZH OEBY 1Y or 2Y 1.2 5.6 nstPZL OEBY 1Y or 2Y 1.8 4.9 ns tPHZ OEBY 1Y or 2Y 0.9 5.4 ns tPLZ OEBY 1Y or 2Y 1.4 4.5 ns
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions for UBT transceiver (unless otherwise noted) (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT fmax 120 MHz tPLH 3A 3B 5.1 9.3 nstPHL 3A 3B 4.7 8.3 ns tPLH LE 3B 5.5 10.6 nstPHL LE 3B 4.9 8.7 ns tPLH CLKAB 3B 5.8 10.1 nstPHL CLKAB 3B 4.2 8.4 ns tPZH OE 3B 4.2 9.3 nstPZL OE 3B 3.2 8.5 ns tPHZ OE 3B 4.2 9.3 ns tPLZ OE 3B 2.4 5.7 ns tr Transition time, B port (10%−90%) 4.3 ns tf Transition time, B port (90%−10%) 4.3 ns tPLH 3B 3A 1.5 5.9 nstPHL 3B 3A 1.7 5.9 ns tPLH LE 3A 1.7 5.9 nstPHL LE 3A 1.7 5.9 ns tPLH CLKBA 3A 1.1 5.5 nstPHL CLKBA 3A 1.4 5.5 ns tPZH OE 3A 1.5 6.2 nstPZL OE 3A 2.1 5.5 ns tPHZ OE 3A 0.8 6.2 ns tPLZ OE 3A 2.3 5.6 ns skew characteristics for bus transceiver for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tsk(LH) 1A or 2A 1B or 2B 0.8 ns tsk(HL) 1A or 2A 1B or 2B 0.7 ns tsk(LH) 1B or 2B 1Y or 2Y 0.7 ns tsk(HL) 1B or 2B 1Y or 2Y 0.7 ns tsk(t)† 1A or 2A 1B or 2B 3.9 nstsk(t)† 1B or 2B 1Y or 2Y 1.5 ns tsk(pp) 1A or 2A 1B or 2B 3.6 nstsk(pp) 1B or 2B 1Y or 2Y 1.4 ns † tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 skew characteristics for UBT for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tsk(LH) 3A 3B 1.4 ns tsk(HL) 3A 3B 1.1 ns tsk(LH) CLKAB 3B 0.8 ns tsk(HL) CLKAB 3B 0.8 ns tsk(LH) 3B 3A 0.7 ns tsk(HL) 3B 3A 0.6 ns tsk(LH) CLKBA 3A 0.7 ns tsk(HL) CLKBA 3A 0.6 ns 3A 3B 3.9 tsk(t)† CLKAB 3B 3.9 nstsk(t)† 3B 3A 1.6 ns CLKBA 3A 1.2 3A 3B 3.6 tsk(pp) CLKAB 3B 3.5 nstsk(pp) 3B 3A 1.3 ns CLKBA 3A 1.2 † tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2n s. D. The outputs are measured one at a time, with one transition per measurement.
1.5 V 0 V
Figure 1. Load Circuit and Voltage Waveforms
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2n s. D. The outputs are measured one at a time, with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
this device has been designed for optimum performance in the VME64x backplane as shown in Figure 3. † Unloaded backplane trace natural impedence (ZO ) is 45 Ω. 45 Ω to 60 Ω is allowed, with 50 Ω being ideal. ‡ Card stub natural impedence (ZO ) is 60 Ω. Figure 3. VME64x Backplane performance of the VME device in this typical backplane. See www.ti.com/sc/etl for more information. § All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. ¶ All tr and tf times are taken at the first receiver.
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 driver in slot 11, with receiver cards in all other slots (full load) (continued) switching characteristics over recommended operating conditions for UBT (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP † MAX UNIT tPLH 3A 3B 6.2 8.9 nstPHL 3A 3B 5.6 9 ns tPLH LE 3B 6.1 9.1 nstPHL LE 3B 5.6 9 ns tPLH CLKAB 3B 6.2 9.1 nstPHL CLKAB 3B 5.7 9 ns tr‡ Transition time, B port (10%−90%) 9 8.6 11.4 ns tf‡ Transition time, B port (90%−10%) 8.9 9 10.8 ns † All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. ‡ All tr and tf times are taken at the first receiver. skew characteristics for bus transceiver for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP † MAX UNIT tsk(LH) 1A or 2A 1B or 2B 2.5 ns tsk(HL) 1A or 2A 1B or 2B ns tsk(t)§ 1A or 2A 1B or 2B 1 ns tsk(pp) 1A or 2A 1B or 2B 0.5 3.4 ns † All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. § tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)]. skew characteristics for UBT for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP † MAX UNIT tsk(LH) 3A 3B 2.4 ns tsk(HL) 3A 3B 3.4 ns tsk(LH) CLKAB 3B 2.7 ns tsk(HL) CLKAB 3B 3.4 ns tsk(t)§ 3A 3B 1 nstsk(t)§ CLKAB 3B 1 ns tsk(pp) 3A 3B 0.5 3.4 nstsk(pp) CLKAB 3B 0.6 3.5 ns † All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. § tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
driver in slot 1, with one receiver in slot 21 (minimum load) switching characteristics over recommended operating conditions for bus transceiver function (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP † MAX UNIT tPLH 1A or 2A 1B or 2B 5.5 7.4 nstPHL 1A or 2A 1B or 2B 5.3 7.4 ns tr‡ Transition time, B port (10%−90%) 3.9 3.4 4.4 ns tf‡ Transition time, B port (90%−10%) 3.7 3.4 4.8 ns † All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. ‡ All tr and tf times are taken at the first receiver. switching characteristics over recommended operating conditions for UBT (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP † MAX UNIT tPLH 3A 3B 5.8 7.9 nstPHL 3A 3B 5.5 7.7 ns tPLH LE 3B 5.9 8 nstPHL LE 3B 5.5 7.8 ns tPLH CLKAB 3B 5.9 8.1 nstPHL CLKAB 3B 5.5 7.7 ns tr‡ Transition time, B port (10%−90%) 3.9 3.4 4.4 ns tf‡ Transition time, B port (90%−10%) 3.7 3.4 4.8 ns † All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. ‡ All tr and tf times are taken at the first receiver. skew characteristics for bus transceiver for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP † MAX UNIT tsk(LH) 1A or 2A 1B or 2B 1.7 ns tsk(HL) 1A or 2A 1B or 2B 2.1 ns tsk(t)§ 1A or 2A 1B or 2B 1 ns tsk(pp) 1A or 2A 1B or 2B 0.2 2.1 ns † All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. § tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. directions, both low to high (LH) and high to low (HL) [tsk(t)]. driving the lumped load shown in Figure 4. Figure 4. Equivalent AC Peak Output-Current Lumped Load
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004
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driver in slot 1, with one receiver in slot 21 (minimum load) (continued) In general, the rise- and fall-time distribution is shown in Figure 5. Since VME devices were designed for use into distributed loads like the VME64x backplane (B/P), there are significant differences between low-to-high (LH) and high-to-low (HL) values in the lumped load shown in the PMI (see Figures 1 and 2). 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 HL LH Full B/P Load Minimum B/P Load PMI Lumped Load Time − ns Figure 5 Characterization-laboratory data in Figures 6 and 7 show the absolute ac peak output current, with different supply voltages, as the devices change output logic state. A typical nominal process is shown to demonstrate the devices’ peak ac output drive capability. Figure 6 3.15 3.30 3.45 Peak IO(LH) − mA VCC − V 137 136 135 134 133 132 131 130 129 128 Figure 7 3.15 3.30 3.45 Peak IO(HL) − mA VCC − V 162 160 158 156 154 152 150 148 146 144
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 10. VOL vs IOL Figure 11. VOH vs IOH
/C0083/C0078/C0055/C0052/C0086/C0077/C0069/C0072/C0050/C0050/C0053/C0048/C0049/C0065 /C0056/C0262/C0066/C0073/C0084 /C0085/C0078/C0073/C0086/C0069/C0082/C0083/C0065/C0076 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 /C0065/C0078/C0068 /C0084/C0087/C0079 /C0049/C0262/C0066/C0073/C0084 /C0066/C0085/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0080/C0076/C0073/C0084 /C0076/C0086/C0084/C0084/C0076 /C0080/C0079/C0082/C0084/C0044 /C0070/C0069/C0069/C0068/C0066/C0065/C0067/C0075 /C0080/C0065/C0084/C0072/C0044 /C0065/C0078/C0068 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES620 – DECEMBER 2004 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VMEbus SUMMARY In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications. The data-transfer protocols used to define the VMEbus came from the Motorola VERSA bus architecture, which owed its heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when introduced, defined two basic data-transfer operations – single-cycle transfers consisting of an address and a data transfer, and a block transfer (BLT) consisting of an address and a sequence of data transfers. These transfers were asynchronous, using a master-slave handshake. The master puts address and data on the bus and waits for an acknowledgment. The selected slave either reads or writes data to or from the bus, then provides a data-acknowledge (DTACK*) signal. The VMEbus system data throughput was 40 Mbyte/s. Previous to the VMEbus, it was not uncommon for the backplane buses to require elaborate calculations to determine loading and drive current for interface design. This approach made designs difficult and caused compatibility problems among manufacturers. To make interface design easier and to ensure compatibility, the developers of the VMEbus architecture defined specific delays based on a 21-slot terminated backplane and mandated the use of certain high-current TTL drivers, receivers, and transceivers. In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby doubling the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the double-edge transfer (2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade Association (VITA) established a task group to specify a synchronous protocol to increase data-transfer rates to 320 Mbyte/s, or more. The unreleased specification, VITA 1.5 [double-edge source synchronous transfer (2eSST)], is based on the asynchronous 2eVME protocol. It does not wait for acknowledgement of the data by the receiver and requires incident-wave switching. Sustained data rates of 1 Gbyte/s, more than ten times faster than traditional VME64 backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320 star-configuration backplane. The VME320 backplane approximates a lumped load, allowing substantially higher-frequency operation over the VME64x distributed-load backplane. Traditional VME64 backplanes with no changes theoretically can sustain 320 Mbyte/s. From BLT to 2eSST − A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director, VITA, provides additional information on VMEbus and can be obtained at www.vita.com. maximum data transfer rates DATE TOPOLOGY PROTOCOL DATA BITS DATA TRANSFERS PER SYSTEM FREQUENCY (MHz) DATE TOPOLOGY PROTOCOL DATA BITS PER CYCLE DATA TRANSFERS PER CLOCK CYCLE PER SYSTEM (Mbyte/s) BACKPLANE CLOCK
1981 VMEbus IEEE-1014 BLT 32 1 40 10 10
1989 VME64 MBLT 64 1 80 10 10
1995 VME64x 2eVME 64 2 160 10 20
1997 VME64x 2eSST 64 2-No Ack 160−320 10−20 20−40
1999 VME320 2eSST 64 2-No Ack 320−1000 20−62.5 40−125 applicability Target applications for VME backplanes include industrial controls, telecommunications, simulation, high-energy physics, office automation, and instrumentation systems.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74VMEH22501ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501ADGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501AGQLR NRND BGA MI CROSTA R JUNI OR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74VMEH22501AZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 1
Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74VMEH22501ADGGR DGG 48 MLA 330 24 8.6 15.8 1.8 12 24 Q1 SN74VMEH22501ADGVR DGV 48 MLA 330 24 6.8 10.1 1.6 12 24 Q1 SN74VMEH22501AGQLR GQL 56 HIJ 330 16 4.8 7.3 1.45 8 16 Q1 SN74VMEH22501AZQLR ZQL 56 HIJ 330 16 4.8 7.3 1.45 8 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74VMEH22501ADGGR DGG 48 MLA 333.2 333.2 31.75 SN74VMEH22501ADGVR DGV 48 MLA 333.2 333.2 31.75 SN74VMEH22501AGQLR GQL 56 HIJ 346.0 346.0 33.0 SN74VMEH22501AZQLR ZQL 56 HIJ 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97
48 PINS SHOWN
0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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