74VHC112 FAIRCHILD | Alldatasheet

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■ High speed: fMAX = 200 MHz (typ) at VCC = 5.0V ■ Low power dissipation: ICC = 2 µA (max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Pin and function compatible with 74HC112 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Order Number Package Number Package Description 74VHC112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74VHC112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC112N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description J1, J2, K1, K2 Data Inputs CLK1, CLK2 Clock Pulse Inputs (Active Falling Edge) CLR1, CLR2 Direct Clear Inputs (Active LOW) PR1, PR2 Direct Preset Inputs (Active LOW) Q1, Q2, Q1, Q2 Outputs

www.fairchildsemi.com 2 74VHC112 Truth Table H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial /c16 = HIGH-to-LOW Clock Transition Q 0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) Inputs Outputs PR CLR CP JK Q Q LHX X X H L HLX X X L H LLX X X H H HH /c16 hhQ 0 Q 0 HH /c16 lhL H HH /c16 hl H L HH /c16 ll Q 0 Q 0

3 www.fairchildsemi.com 74VHC112 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. Fairchild does not recommend operation outside databook specifica- tions. Note 2: Unused inputs must be held HIGH or LOW. They may not float. Supply Voltage (VCC ) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V DC Output Voltage (VOUT ) −0.5V to VCC + 0.5V Input Diode Current (IIK) −20 mA Output Diode Current (IOK ) ±20 mA DC Output Current (IOUT ) ±25 mA DC VCC /GND Current (ICC ) ±50 mA Storage Temperature (TSTG ) −65°C to +150°C Lead Temperature (TL) (Soldering, 10 seconds) 260 °C Supply Voltage (VCC ) 2.0V to +5.5V Input Voltage (VIN) 0V to +5.5V Output Voltage (VOUT ) 0V to V CC Operating Temperature (TOPR ) −40°C to +85°C Input Rise and Fall Time (tr, tf) V CC = 3.3V ± 0.3V 0 ∼ 100 ns/V V CC = 5.0V ± 0.5V 0 ∼ 20 ns/V Symbol Parameter VCC (V) TA = 25°C T A = −40°C to +85°C Units Conditions Min Typ Max Min Max VIH HIGH Level 2.0 1.50 1.50 V Input Voltage 3.0 − 5.5 0.7 VCC 0.7 VCC VIL LOW Level 2.0 0.50 0.50 V Input Voltage 3.0 − 5.5 0.3 V CC 0.3 VCC VOH HIGH Level 2.0 1.9 2.0 1.9 V IN = VIH IOH = −50 µA Output Voltage 3.0 2.9 3.0 2.9 V or V IL 4.5 4.4 4.5 4.4 3.0 2.58 2.48 V IOH = −4 mA 4.5 3.94 3.80 I OH = −8 mA VOL LOW Level 2.0 0.0 0.1 0.1 V IN = VIH IOL = 50 µA Output Voltage 3.0 0.0 0.1 0.1 V or V IL 4.5 0.0 0.1 0.1 3.0 0.36 0.44 V IOL = 4 mA 4.5 0.36 0.44 I OL = 8 mA IIN Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µA V IN = 5.5V or GND ICC Quiescent Supply Current 5.5 2.0 20.0 µA V IN = VCC or GND

www.fairchildsemi.com 4 74VHC112 Note 3: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC /4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 • n AC Operating Requirements Note 4: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V Symbol Parameter VCC (V) TA = 25°C T A = −40°C to +85°C Units Conditions Min Typ Max Min Max fMAX Maximum Clock 3.3 ± 0.3 110 150 100 MHz CL = 15 pF Frequency 90 120 80 C L = 50 pF 5.0 ± 0.5 150 200 135 MHz CL = 15 pF 120 185 110 C L = 50 pF ns CL = 15 pF tPHL Time (CP to Qn or Qn) 10.0 15.0 1.0 16.5 C L = 50 pF ns CL = 15 pF 6.3 10.5 1.0 12.0 C L = 50 pF ns CL = 15 pF tPHL (PR or CLR to Qn or Qn) 9.7 13.5 1.0 15.0 C L = 50 pF ns CL = 15 pF 6 . 4 9 . 5 1 . 0 1 1 . 0 C L = 50 pF CIN Input Capacitance 4 10 10 pF V CC = Open CPD Power Dissipation 18 pF (Note 3) Capacitance Symbol Parameter VCC (Note 4) (V) TA = 25°C T A = −40°C to +85°C Units Typ Guaranteed Minimum tW Minimum Pulse Width 3.3 5.0 5.0 ns (CP or CLR or PR) 5.0 5.0 5.0 tS Minimum Setup Time 3.3 5.0 5.0 ns (Jn or Kn to CPn) 5.0 4.0 4.0 tH Minimum Hold Time 3.3 1.0 1.0 ns (Jn or Kn to CPn) 5.0 1.0 1.0 tREC Minimum Recovery Time 3.3 6.0 6.0 ns (CLR or PR to CP) 5.0 5.0 5.0

5 www.fairchildsemi.com 74VHC112 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com 6 74VHC112 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC112 Dual J-K Flip-Flops with Preset and Clear LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E