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Features

■ High Speed: tPD = 4.3ns (Typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protection is provided on all inputs ■ Low power dissipation: ICC = 2µA (Max.) @ TA = 25°C ■ Low noise: VOLP = 0.8V (Max.) ■ Pin and function compatible with 74HC08 General Description The VHC08 is an advanced high speed CMOS 2 Input AND Gate fabricated with silicon gate CMOS technol- ogy. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 4 stages including buffer output, which provide high noise immunity and stable output. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as bat- tery backup. This circuit prevents device destruction due to mismatched supply and input voltages.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Pack age Number Package Description 74VHC08M M14A 14-Lead Small Outline Integr ated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC08 — Quad 2-Input AND Gate Connection Diagram Pin Description Logic Symbol IEEE/IEC Truth TablePin Names Description An, Bn Inputs On Outputs AB O LLL LHL HL L HHH www.onsemi.com

74VHC08 — Quad 2-Input AND Gate Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to absolute maximum ratings. Note: 1. Unused inputs must be held HIGH or LOW. They may not float. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage –0.5V to VCC + 0.5V IIK Input Diode Current –20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current ±50mA TSTG Storage Temperature –65°C to +150°C TL Lead Temperature (Soldering, 10 seconds) 260°C Symbol Parameter Rating VCC Supply Voltage 2.0V to +5.5V VIN Input Voltage 0V to +5.5V VOUT Output Voltage 0V to VCC TOPR Operating Temperature –40°C to +85°C tr, tf Input Rise and Fall Time, V CC = 3.3V ± 0.3V V CC = 5.0V ± 0.5V 0ns/V ∼ 100ns/V 0ns/V ∼ 20ns/V www.onsemi.com

74VHC08 — Quad 2-Input AND Gate Noise Characteristics Note: 2. Parameter guaranteed by design. Symbol Parameter V CC (V) Conditions TA = 25°C TA = –40°C to +85°C UnitsMin. T yp. Max. Min. Max. VIH HIGH Lev el Input Voltage 2.0 1.50 1.50 V 3.0–5.5 0.7 x VCC 0.7 x VCC VIL LOW Le vel Input Voltage 2.0 0.50 0.50 V 3.0–5.5 0.3 x VCC 0.3 x VCC VOH HIGH Lev el Output Voltage

2.0 V IN = VIH

IOH = –50µA 1.9 2.0 1.9 V 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 IOH = –4mA 2.58 2.48 4.5 IOH = –8mA 3.94 3.80 VOL LOW Le vel Output Voltage IOL = 50µA 0.0 0.1 0.1 V 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 IOL = 4mA 0.36 0.44 4.5 IOL = 8mA 0.36 0.44 IIN Input Leakage Current 0–5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current 5.5 V IN = VCC or GND 2.0 20.0 µA Symbol P arameter V CC (V) Conditions TA = 25°C UnitsTyp. Limits VOLP (2) Quiet Output Maximum Dynamic VOL 5.0 CL = 50pF 0.3 0.8 V VOLV (2) Quiet Output Minimum Dynamic VOL 5.0 CL = 50pF –0.3 –0.8 V VIHD (2) Minimum HIGH Le vel Dynamic Input Voltage 5.0 C L = 50pF 3.5 V VILD 2) Maximum LO W Level Dynamic Input Voltage 5.0 C L = 50pF 1.5 V www.onsemi.com

74VHC08 — Quad 2-Input AND Gate Note: 3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 4 (per gate). Symbol P arameter V CC (V) Conditions TA = 25°C TA = –40°C to +85°C CL = 50pF 8.7 12.3 1.0 14.0 CL = 50pF 5.8 7.9 1.0 9.0 CIN Input Capacitance VCC = Open 4 10 10 pF CPD Power Dissipation Capacitance (3) 18 pF www.onsemi.com

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