74VHC04 ONSEMI | Alldatasheet
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74VHC04 — Hex Inverter ©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC04 Rev. 1.3.0 February 2008 74VHC04 Hex Inverter
Features
High Speed: t PD 3.8ns (typ.) at V CC High noise immunity: V NIH V NIL 28% V CC (min.) Power down protection is provided on all inputs Low Noise: V OLP 0.4V (typ.) Low power dissipation: I CC 2µA (max.) @ T A 25°C Pin and function compatible with 74HC04 General Description The VHC04 is an advanced high speed CMOS Inverter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as bat- tery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74VHC04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC04SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC04MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC04 Rev. 1.3.0 2 74VHC04 — Hex Inverter Connection Diagram Pin Description Logic Symbol IEEE/IEC Truth Table Pin Names Description A n Inputs O n Outputs AO LH HL
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC04 Rev. 1.3.0 3 74VHC04 — Hex Inverter Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Recommended Operating Conditions (1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Note: 1. Unused inputs must be held HIGH or LOW. They may not float. Symbol Parameter Rating V CC Supply Voltage –0.5V to +7.0V V IN DC Input Voltage –0.5V to +7.0V V OUT DC Output Voltage –0.5V to V CC + 0.5V I IK Input Diode Current –20mA I OK Output Diode Current ±20mA I OUT DC Output Current ±25mA I CC DC V CC /GND Current ±50mA T STG Storage Temperature –65°C to +150°C T L Lead Temperature (Soldering, 10 seconds) 260°C Symbol Parameter Rating V CC Supply Voltage 2.0V to +5.5V V IN Input Voltage 0V to +5.5V V OUT Output Voltage 0V to V CC T OPR Operating Temperature –40°C to +85°C t r , t f Input Rise and Fall Time, V CC 3.3V ± 0.3V V CC 5.0V ± 0.5V 0ns/V 100ns/V 0ns/V 20ns/V
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC04 Rev. 1.3.0 4 74VHC04 — Hex Inverter Noise Characteristics Note: 2. Parameter guaranteed by design. Symbol Parameter V CC (V) Conditions T A 25°C T A –40°C to +85°C V IH HIGH Level Input Voltage 2.0 1.50 1.50 V 3.0–5.5 0.7 x V CC 0.7 x V CC V IL LOW Level Input Voltage 2.0 0.50 0.50 V 3.0–5.5 0.3 x V CC 0.3 x V CC V OH HIGH Level Output Voltage 2.0 V IN V IH or V IL I OH –50µA 1.9 2.0 1.9 V 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 I OH –4mA 2.58 2.48 4.5 I OH –8mA 3.94 3.80 V OL LOW Level Output Voltage 2.0 V IN V IH or V IL I OL 50µA 0.0 0.1 0.1 V 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 I OL 4mA 0.36 0.44 4.5 I OL 8mA 0.36 0.44 I IN Input Leakage Current 0–5.5 V IN 5.5V or GND ±0.1 ±1.0 µA I CC Quiescent Supply Current 5.5 V IN V CC or GND 2.0 20.0 µA Symbol Parameter V CC (V) Conditions T A 25°C UnitsTyp. Limits V OLP (2) Quiet Output Maximum Dynamic V OL 5.0 C L 50pF 0.4 0.8 V V OLV (2) Quiet Output Minimum Dynamic V OL 5.0 C L 50pF –0.4 –0.8 V V IHD (2) Minimum HIGH Level Dynamic Input Voltage 5.0 C L 50pF 3.5 V V ILD (2) Maximum LOW Level Dynamic Input Voltage 5.0 C L 50pF 1.5 V
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC04 Rev. 1.3.0 5 74VHC04 — Hex Inverter Note: 3. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC (opr.) C PD
- V CC
- f IN + I CC / 6 (per gate). Symbol Parameter V CC (V) Conditions T A = 25°C TA = –40°C to +85°C CL = 50 pF 7.5 10.6 1.0 12.0 CL = 50 pF 5.3 7.5 1.0 8.5 CIN Input Capacitance V CC = OPEN 4 10 10 pF CPD Power Dissipation Capacitance (3) 18 pF
NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 2009. E. LANDPATTERN STANDARD: SOP65P640X110-14M. F. DRAWING FILE NAME: MKT-MTC14rev7. 0.43TYP
0.2 C B A
A B 3.2 6.4 PIN#1 IDENT
1.2 MAX
0.1 C ALL LEAD TIPS C 0.65 0.30 0.19
0.13 A B C
0.90+0.15 -0.10 0.20 0.09 SEE DETAIL A 723 %27720 GAGE PLANE 0.25 SEATING PLANE
0.09 MIN
1.00 DETAIL A RECOMMENDED LAND PATTERN 6.10 0.65 1.65 0.45
1.70 5.60 1.27 0.65 1.50 1.25
1.75 MAX
0.25 0.10 C 4.00 3.80 8.75 8.50 6.00 (0.33) 0.51 0.35 7.62 1.27 1PIN #1 IDENT. A B 0.25 0.19 A 0.50 0.25 x 45 R0.10 R0.10 (1.04) 0.36 0.90 0.50 DETAIL A SCALE 16 : 1 GAGE PLANE SEATING PLANE TOP VIEW FRONT VIEW SIDE VIEW 1 7 LAND PATTERN RECOMMENDATION NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D. LAND PATTERN STANDARD: SOIC127P600X145-14M E. CONFORMS TO ASME Y14.5M, 2009 D. DRAWING FILENAME: MKT-M14Arev14 0.10 C
0.25 M C B A
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