74VCX162373MTD

74VCX162373 ONSEMI | Alldatasheet

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© 2005 Fairchild Semiconductor Corporation DS500236 www.fairchildsemi.com January 2000 Revised June 2005 74VCX162373 Low Voltage 16-Bit Transparent Latch 74VCX162373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26/G58 Series Resistors in Outputs General Description The VCX162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE ) is LOW. When OE is HIGH, the out- puts are in a high impedance state. The VCX162373 is also designed with 26/c58 resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters. The 74VCX162373 is designed for low voltage (1.4V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX162373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation.

Features

■ 1.4V–3.6V VCC supply operation ■ 3.6V tolerant inputs and outputs ■ 26/c58 series resistors in outputs ■ tPD (In to On) 3.3 ns max for 3.0V to 3.6V VCC ■ Power-off high impedance inputs and outputs ■ Support live insertion and withdrawal (Note 1) ■ Static Drive (IOH /IOL ) /c114 12 mA @ 3.0V VCC ■ Latch-up performance exceeds 300 mA ■ ESD performance: Human body model /c33 2000V Machine model /c33 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Ordering Number Package Package DescriptionNumber 74VCX162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDE C MO-153, 6.1mm Wide Pin Names Description OE n Output Enable Input (Active LOW) LEn Latch Enable Input I0–I15 Inputs O 0–O 15 Outputs ■ Uses proprietary noise/EMI reduction circuitry

www.fairchildsemi.com 2 74VCX162373 Connection Diagram Truth Tables H /c32 HIGH Voltage Level L /c32 LOW Voltage Level X /c32 Immaterial (HIGH or LOW, inputs may not float) Z /c32 High Impedance O 0 /c32 Previous O0 before HIGH-to-LOW of Latch Enable Functional Description The 74VCX162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable (OE n) input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Outputs LE 1 OE 1 I0–I7 O 0–O 7 XHX Z HLL L HLHH LLX O 0 Inputs Outputs LE 2 OE

2 I8–I15 O 8–O 15

3 www.fairchildsemi.com 74VCX162373 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions (Note 4) Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat- ings. The “Recommended Operating Conditions” table will define the condi- tions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused inputs must be held HIGH or LOW. Supply Voltage (VCC ) /c16 0.5V to /c14 4.6V DC Input Voltage (VI) /c16 0.5V to /c14 4.6V Output Voltage (VO ) Outputs 3-STATED /c16 0.5V to /c14 4.6V Outputs Active (Note 3) /c16 0.5V to VCC /c14 0.5V DC Input Diode Current (IIK) VI /c31 0V /c16 50 mA DC Output Diode Current (IOK ) VO /c31 0V /c16 50 mA VO /c33 VCC /c14 50 mA DC Output Source/Sink Current (IOH /IOL ) /c114 50 mA DC V CC or GND Current per Supply Pin (ICC or GND) /c114 100 mA Storage Temperature Range (TSTG ) /c16 65/c113 C to /c14 150/c113 C Power Supply Operating 1.4V to 3.6V Input Voltage /c16 0.3V to /c14 3.6V Output Voltage (VO ) Output in Active States 0V to V CC Output in “OFF ” State 0.0V to 3.6V Output Current in IOH /IOL VCC /c32 3.0V to 3.6V /c114 12 mA VCC /c32 2.3V to 2.7V /c114 8 mA VCC /c32 1.65V to 2.3V /c114 3 mA VCC /c32 1.4V to 1.6V /c114 1 mA Free Air Operating Temperature (TA) /c16 40/c113 C to /c14 85/c113 C Minimum Input Edge Rate (/c39 t//c39 V) VIN /c32 0.8V to 2.0V, VCC /c32 3.0V 10 ns/V Symbol Parameter Conditions VCC Min Max Units (V) VIH HIGH Level Input Voltage 2.7 - 3.6 2.0 V 2.3 - 2.7 1.6 1.65 - 2.3 0.65 x VCC 1.4 - 1.6 0.65 x VCC VIL LOW Level Input Voltage 2.7 - 3.6 0.8 V 2.3 - 2.7 0.7 1.65 - 2.3 0.35 x V CC 1.4 - 1.6 0.35 x V CC VOH HIGH Level Output Voltage I OH /c32 /c16 100 /c80 A 2.7 - 3.6 V CC - 0.2 V IOH /c32 /c16 6 mA 2.7 2.2 IOH /c32 /c16 8 mA 3.0 2.4 IOH /c32 /c16 12 mA 3.0 2.2 IOH /c32 /c16 100 /c80 A 2.3 - 2.7 V CC - 0.2 IOH /c32 /c16 4 mA 2.3 2.0 IOH /c32 /c16 6 mA 2.3 1.8 IOH /c32 /c16 8 mA 2.3 1.7 IOH /c32 /c16 100 /c80 A 1.65 - 2.3 V CC - 0.2 IOH /c32 /c16 3 mA 1.65 1.25 IOH /c32 /c16 100 /c80 A 1.4 - 1.6 V CC - 0.2 IOH /c32 /c16 1 mA 1.4 1.05

www.fairchildsemi.com 4 74VCX162373 Note 5: Outputs disabled or 3-STATE only. Symbol Parameter Conditions VCC Min Max Units (V) VOL LOW Level Output Voltage I OL /c32 100 /c80 A 2.7 - 3.6 0.2 V IOL /c32 6 mA 2.7 0.4 IOL /c32 8 mA 3.0 0.55 IOL /c32 12 mA 3.0 0.8 IOL /c32 100 /c80 A 2.3 - 2.7 0.2 IOL /c32 6 mA 2.3 0.4 IOL /c32 8 mA 2.3 0.6 IOL /c32 100 /c80 A 1.65 - 2.3 0.2 IOL /c32 3 mA 1.65 0.3 IOL /c32 100 /c80 A 1.4 - 1.6 0.2 IOL /c32 1 mA 1.4 0.35 II Input Leakage Current 0 /c100 VI /c100 3.6V 1.4 - 3.6 /c114 5.0 /c80 A IOZ 3-STATE Output Leakage 0 /c100 VO /c100 3.6V, VI /c32 VIH or VIL 1.4 - 3.6 /c114 10.0 /c80 A IOFF Power-OFF Leakage Current 0 /c100 (VI, VO ) /c100 3.6V 0 10.0 /c80 A ICC Quiescent Supply Current V I /c32 VCC or GND 1.4 - 3.6 20.0 /c80 A VCC /c100 (VI, VO ) /c100 3.6V (Note 5) 1.4 - 3.6 /c114 20.0 /c80 A /c39 ICC Increase in ICC per Input V IH /c32 VCC /c16 0.6V 2.7 - 3.6 750 /c80 A Symbol Parameter Conditions VCC TA /c32 /c16 40/c113 C to /c14 85/c113 C Units Figure (V) Min Max Number tPHL Propagation Delay C L /c32 30 pF, RL /c32 500/c58 3.3 /c114 0.3 0.8 3.6 ns Figures 1, 2tPLH LE to On 2.5 /c114 0.2 1.0 4.9 1.8 /c114 0.15 1.5 9.8 C L /c32 15 pF, RL /c32 2k/c58 1.5 /c114 0.1 1.0 19.6 Figures 7, 8 tPHL Propagation Delay C L /c32 30 pF, RL /c32 500/c58 3.3 /c114 0.3 0.8 3.3 ns Figures 1, 2tPLH In to On 2.5 /c114 0.2 1.0 4.5 1.8 /c114 0.15 1.5 9.0 C L /c32 15 pF, RL /c32 2k/c58 1.5 /c114 0.1 1.0 18.0 Figures 7, 8 tPZL Output Enable Time C L /c32 30 pF, RL /c32 500/c58 3.3 /c114 0.3 0.8 3.9 ns Figures 1, 3, 4tPZH 2.5 /c114 0.2 1.0 5.4 1.8 /c114 0.15 1.5 9.8 C L /c32 15 pF, RL /c32 2k/c58 1.5 /c114 0.1 1.0 19.6 Figures 7, 9, 10 tPLZ Output Disable Time C L /c32 30 pF, RL /c32 500/c58 3.3 /c114 0.3 0.8 4.0 ns Figures 1, 3, 4tPHZ 2.5 /c114 0.2 1.0 4.4 1.8 /c114 0.15 1.5 7.9 C L /c32 15 pF, RL /c32 2k/c58 1.5 /c114 0.1 1.0 15.8 Figures 7, 9, 10 tS Setup Time C L /c32 30 pF, RL /c32 500/c58 3.3 /c114 0.3 1.5 ns Figures 1, 62.5 /c114 0.2 1.5 1.8 /c114 0.15 2.5 C L /c32 15 pF, RL /c32 2k/c58 1.5 /c114 0.1 3.0 Figures 6, 7 tH Hold Time C L /c32 30 pF, RL /c32 500/c58 3.3 /c114 0.3 1.0 ns Figures 1, 62.5 /c114 0.2 1.0 1.8 /c114 0.15 1.0 C L /c32 15 pF, RL /c32 2k/c58 1.5 /c114 0.1 2.0 Figures 6, 7

5 www.fairchildsemi.com 74VCX162373 Note 6: For CL /c32 50PF, add approximately 300 ps to the AC maximum specification. Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL ) or LOW-to-HIGH (tOSLH ). Dynamic Switching Characteristics Capacitance Symbol Parameter Conditions VCC TA /c32 /c16 40/c113 C to /c14 85/c113 C Units Figure (V) Min Max Number tW Pulse Width C L /c32 30 pF, RL /c32 500/c58 3.3 /c114 0.3 1.5 ns Figures 1, 52.5 /c114 0.2 1.5 1.8 /c114 0.15 4.0 C L /c32 15 pF, RL /c32 2k/c58 1.5 /c114 0.1 4.0 Figures 5, 7 tOSHL Output to Output Skew C L /c32 30 pF, RL /c32 500/c58 3.3 /c114 0.3 0.5 ns tOSLH (Note 7) 2.5 /c114 0.2 0.5 1.8 /c114 0.15 0.75 C L /c32 15 pF, RL /c32 2k/c58 1.5 /c114 0.1 1.5 Symbol Parameter Conditions VCC TA /c32 /c14 25/c113 C Units (V) Typical VOLP Quiet Output Dynamic Peak VOL C L /c32 30 pF, VIH /c32 VCC , VIL /c32 0V 1.8 0.15 V2.5 0.25 3.3 0.35 VOLV Quiet Output Dynamic Valley VOL C L /c32 30 pF, VIH /c32 VCC , VIL /c32 0V 1.8 /c16 0.15 V2.5 /c16 0.25 3.3 /c16 0.35 VOHV Quiet Output Dynamic Valley VOH C L /c32 30 pF, VIH /c32 VCC , VIL /c32 0V 1.8 1.55 V2.5 2.05 3.3 2.65 Symbol Parameter Conditions TA /c32 /c14 25/c113 C Units Typical C IN Input Capacitance V CC /c32 1.8V, 2.5V or 3.3V, VI /c32 0V or VCC 6p F C OUT Output Capacitance V I /c32 0V or VCC , VCC /c32 1.8V, 2.5V or 3.3V 7 pF C PD Power Dissipation Capacitance V I /c32 0V or VCC , f /c32 10 MHz, 20 pF VCC /c32 1.8V, 2.5V or 3.3V

www.fairchildsemi.com 8 74VCX162373 Low Voltage 16-Bit Transparent Latch Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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