74VCX162373 FAIRCHILD | Alldatasheet

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■ 1.65V–3.6V VCC supply operation ■ 3.6V tolerant inputs and outputs ■ 26Ω series resistors in outputs ■ tPD (In to On) 3.3 ns max for 3.0V to 3.6V VCC 4.5 ns max for 2.3V to 2.7V VCC 9.0 ns max for 1.65V to 1.95V VCC ■ Power-off high impedance inputs and outputs ■ Support live insertion and withdrawal (Note 1) ■ Static Drive (IOH /IOL ) ±12 mA @ 3.0V VCC ±8 mA @ 2.3V VCC ±3 mA @ 1.65V V CC ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Ordering Number Package Package DescriptionNumber 74VCX162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description OE n Output Enable Input (Active LOW) LEn Latch Enable Input I0–I15 Inputs O 0–O 15 Outputs

www.fairchildsemi.com 2 74VCX162373 Connection Diagram Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O 0 = Previous O0 before HIGH-to-LOW of Latch Enable Functional Description The 74VCX162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LE n) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3- STATE outputs are controlled by the Output Enable (OEn) input. When OEn is LOW the standard outputs are in the 2- state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Outputs LE 1 OE 1 I0–I7 O 0–O 7 XHX Z HLL L HLHH LLX O Inputs Outputs LE 2 OE 2 I8–I15 O 8–O 15 XHX Z HLL L HLHH LLX O 0

3 www.fairchildsemi.com 74VCX162373 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions (Note 4) Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat- ings. The “Recommended Operating Conditions” table will define the condi- tions for actual device operation. Note 3: I O Absolute Maximum Rating must be observed. Note 4: Floating or unused inputs must be held HIGH or LOW. Note 5: Outputs disabled or 3-STATE only. Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Output Voltage (VO ) Outputs 3-STATED −0.5V to +4.6V Outputs Active (Note 3) −0.5V to VCC +0.5V DC Input Diode Current (IIK) VI < 0V −50 mA DC Output Diode Current (IOK ) VO < 0V −50 mA VO > VCC +50 mA DC Output Source/Sink Current (IOH /IOL ) ±50 mA DC V CC or GND Current per Supply Pin (ICC or GND) ±100 mA Storage Temperature Range (TSTG ) −65°C to +150°C Power Supply Operating 1.65V to 3.6V Data Retention Only 1.2V to 3.6V Input Voltage −0.3V to +3.6V Output Voltage (V O ) Output in Active States 0V to V CC Output in “OFF” State 0.0V to 3.6V Output Current in IOH /IOL VCC = 3.0V to 3.6V ±12 mA VCC = 2.3V to 2.7V ±8 mA VCC = 1.65V to 2.3V ±3 mA Free Air Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (Δt/ΔV) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Symbol Parameter Conditions VCC (V) Min Max Units VIH HIGH Level Input Voltage 2.7–3.6 2.0 V VIL LOW Level Input Voltage 2.7–3.6 0.8 V VOH HIGH Level Output Voltage I OH = −100 µA 2.7–3.6 V CC − 0.2 V IOH = −6 mA 2.7 2.2 V IOH = −8 mA 3.0 2.4 V IOH = −12 mA 3.0 2.2 V VOL LOW Level Output Voltage I OL = 100 µA 2.7–3.6 0.2 V IOL = 6 mA 2.7 0.4 V IOL = 8 mA 3.0 0.55 V IOL = 12 mA 3.0 0.8 V II Input Leakage Current 0 ≤ VI ≤ 3.6V 2.7–3.6 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 2.7–3.6 ±10 µA VI = VIH or VIL IOFF Power-OFF Leakage Current 0 ≤ (VI, VO ) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current V I = VCC or GND 2.7–3.6 20 µA VCC ≤ (VI, VO ) ≤ 3.6V (Note 5) 2.7–3.6 ±20 µA ΔICC Increase in ICC per Input V IH = VCC −0.6V 2.7–3.6 750 µA

www.fairchildsemi.com 4 74VCX162373 Note 6: Outputs disabled or 3-STATE only. Note 7: Outputs disabled or 3-STATE only. Symbol Parameter Conditions V CC (V) Min Max Units VIH HIGH Level Input Voltage 2.3 − 2.7 1.6 V VIL LOW Level Input Voltage 2.3 − 2.7 0.7 V VOH HIGH Level Output Voltage I OH = −100 µA 2.3 − 2.7 V CC − 0.2 V IOH = −4 mA 2.3 2.0 V IOH = −6 mA 2.3 1.8 V IOH = −8 mA 2.3 1.7 V VOL LOW Level Output Voltage I OL = 100 µA 2.3 − 2.7 0.2 V IOL = 6 mA 2.3 0.4 V IOL = 8 mA 2.3 0.6 V II Input Leakage Current 0 ≤ VI ≤ 3.6V 2.3 − 2.7 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 2.3 − 2.7 ±10 µA VI = VIH or VIL IOFF Power-OFF Leakage Current 0 ≤ (VI, VO ) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current V I = VCC or GND 2.3 − 2.7 20 µA VCC ≤ (VI, VO ) ≤ 3.6V (Note 6) 2.3 − 2.7 ±20 µA Symbol Parameter Conditions VCC (V) Min Max Units VIH HIGH Level Input Voltage 1.65 - 2.3 0.65 × VCC V VIL LOW Level Input Voltage 1.65 - 2.3 0.35 × VCC V VOH HIGH Level Output Voltage I OH = −100 µA 1.65 - 2.3 V CC − 0.2 V IOH = −3 mA 1.65 1.25 V VOL LOW Level Output Voltage I OL = 100 µA 1.65 - 2.3 0.2 V IOL = 3 mA 1.65 0.3 V II Input Leakage Current 0 ≤ VI ≤ 3.6V 1.65 - 2.3 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 1.65 - 2.3 ±10 µA VI = VIH or VIL IOFF Power-OFF Leakage Current 0 ≤ (VI, VO ) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current V I = VCC or GND 1.65 - 2.3 20 µA VCC ≤ (VI, VO ) ≤ 3.6V (Note 7) 1.65 − 2.3 ±20 µA

5 www.fairchildsemi.com 74VCX162373 Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification. Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL ) or LOW-to-HIGH (tOSLH ). Dynamic Switching Characteristics Capacitance Symbol Parameter T A = −40°C to +85°C, CL = 30 pF, RL = 500Ω Min Max Min Max Min Max tS Setup Time 1.5 1.5 2.5 ns tH Hold Time 1.0 1.0 1.0 ns tW Pulse Width 1.5 1.5 4.0 ns tOSHL Output to Output Skew 0.5 0.5 0.75 ns tOSLH (Note 9) Symbol Parameter Conditions V CC (V) TA = +25°C Units Typical VOLP Quiet Output Dynamic Peak VOL C L = 30 pF, VIH = VCC , VIL = 0V 1.8 0.15 V2.5 0.25 3.3 0.35 VOLV Quiet Output Dynamic Valley VOL C L = 30 pF, VIH = VCC , VIL = 0V 1.8 −0.15 V2.5 −0.25 3.3 −0.35 VOHV Quiet Output Dynamic Valley VOH C L = 30 pF, VIH = VCC , VIL = 0V 1.8 1.55 V2.5 2.05 3.3 2.65 Symbol Parameter Conditions TA = +25°C Units Typical C IN Input Capacitance V CC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC 6p F C OUT Output Capacitance V I = 0V or VCC , VCC = 1.8V, 2.5V or 3.3V 7 pF C PD Power Dissipation Capacitance V I = 0V or VCC , f = 10 MHz, 20 pF VCC = 1.8V, 2.5V or 3.3V

7 www.fairchildsemi.com 74VCX162373 Low Voltage 16-Bit Transparent Latch Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com