74V2G00 STMICROELECTRONICS | Alldatasheet

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n HIGH SPEED: tPD = 3.7 ns (TYP.) at VCC =5 V n LOW POWER DISSIPATION: ICC =1 µA (MAX.) at TA =2 5oC n HIGH NOISE IMMUNITY: VNIH =V NIL =2 8 %VCC (MIN.) n POWER DOWN PROTECTION ON INPUTS AND OUTPUTS n SYMMETRICAL OUTPUT IMPEDANCE: |IOH |=IOL = 8 mA (MIN) n BALANCED PROPAGATION DELAYS: t PLH ≅ tPHL n OPERATING VOLTAGE RANGE: VCC (OPR)= 2V to 5.5V n IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V2G00 is an advanced high-speed CMOS DUAL 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R SOT23-8L 74V2G00STR SOT23-8L

Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7.0 V V I DC Input Voltage -0.5 to +7.0 V V O DC Output Voltage (see note 1) -0.5 to +7.0 V V O DC Output Voltage (see note 2) -0.5 to V CC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ICC or IGND DC V CC or Ground Current ± 50 mA Tstg Storage Temperature -65 to +150 oC TL Lead Temperature (10 sec) 260 oC AbsoluteMaximum Ratingsarethose values beyond whichdam age to the device may occur. Functional operation un der these condition isnot implied. 1) VCC =0V 2) High or Low State TRUTH TABLE ABY LLH LHH HLH HHL PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 5 1A, 2A Data Input 2, 6 1B, 2B Data Input 7, 3 1Y, 2Y Data Output

4 GND Ground (0V)

8V CC Positive Supply Voltage RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Supply Voltage 2.0 to 5.5 V V I Input Voltage 0 to 5.5 V V O Output Voltage (see note 1) 0 to 5.5 V V O Output Voltage (see note 2) 0 to V CC V Top Operating Temperature -40 to +85 oC dt/dv Input Rise and Fall Time (see note 3) (VCC =3 . 3± 0.3V) (VCC =5 . 0± 0.5V) 0 to 100 0t o2 0 ns/V ns/V 1) VCC =0V 2) High or Low State 3) VINfrom 30% to70%of VCC 74V2G00

Symbol Parameter Test Conditions Value Unit V CC (V) TA =2 5 o C -40 to 85 o C VIH High Level Input Voltage 2.0 1.5 1.5 V 3.0 to 5.5 0.7V CC 0.7VCC VIL Low Level Input Voltage 2.0 0.5 0.5 V 3.0 to 5.5 0.3V CC 0.3VCC VOH High Level Output Voltage 2.0 I O =-50 µ A 1.9 2.0 1.9 V 3.0 I O =-50µA 2.9 3.0 2.9 4.5 I O =-50µA 4.4 4.5 4.4 3.0 I O =-4 mA 2.58 2.48 4.5 I O =-8 mA 3.94 3.8 VOL Low Level Output Voltage 2.0 I O =50 µ A 0.0 0.1 0.1 V 3.0 I O =50 µA 0.0 0.1 0.1 4.5 I O =50 µA 0.0 0.1 0.1 3.0 I O =4 mA 0.36 0.44 4.5 I O =8 mA 0.36 0.44 II Input Leakage Current 0 to 5.5 VI = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current

5.5 V I =V CC or GND 1 10 µA

0V OUT = 5.5V 0.5 5.0 µA CAPACITIVE CHARACTERISTICS Symbol Parameter Test Conditions Value Unit TA =2 5 o C -40 to 85 o C C IN Input Capacitance 4 10 10 pF C PD Power Dissipation Capacitance (note 1) 19 pF 1) CPD isdefined as thevalue of the IC’sinternal equivalent capacitance whichis calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained bythe followingequation. ICC (opr) = CPD • VCC • fIN+ICC /2 AC ELECTRICAL CHARACTERISTICS (Input tr =tf=3 ns) Symbol Parameter Test Condition Value Unit V CC (V) C L (pF) TA =2 5 o C -40 to 85 o C tPLH tPHL Propagation Delay Time (*) Voltag erange is 3.3V± 0.3V (**) Voltagerange is 5V± 0.5V 74V2G00

CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT =Z OUT of pulse generator (typically50Ω ) WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 74V2G00

DIM. mm mils A 0.90 1.45 35.4 57.1 A1 0.00 0.15 0.0 5.9 A2 0.90 1.30 35.4 51.2 b 0.22 0.38 8.6 14.9 C 0.09 0.20 3.5 7.8 D 2.80 3.00 110.2 118.1 E 2.60 3.00 102.3 118.1 E1 1.50 1.75 59.0 68.8 L 0.35 0.55 13.8 21.6 e 0.65 25.6 e1 1.95 76.7 SOT23-8L MECHANICAL DATA 74V2G00

Information furnished isbelieved to be accurate and reliable. However, STMicroelectroni cs assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. Thispublication supersedes and replaces all informati on previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 74V2G00