74OL6001

74OL6000 FAIRCHILD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

LOGIC-TO-LOGIC OPTOCOUPLERS 3/19/03 Page 1 of 15 © 2003 Fairchild Semiconductor Corporation TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO

DESCRIPTION

OPTOLOGIC™ is the first family of truly logic compatible optically coupled logic interface gates. The family consists of four device types offering LSTTL to TTL and LSTTL to CMOS interfacing. Each of these interfacing functions is available as a buffer (A=B), or as an inverter (A=B). The LSTTL input compatibility is provided by an input integrated circuit, with industry standard logic levels. This input amplifier IC switches a temperature compensated current source driving a high speed 850 nm AlGaAs LED emitter. This novel integration scheme eliminates CTR degradation over time and temperature. The emitter is optically coupled to an integrated photodetector/high-gain, high-speed output amplifier IC. The superior 15kV/µS common-mode noise rejection is ensured through the use of an optically transparent noise shield. The TTL compatible output has a totem-pole with a fan-out of 10. The CMOS compatible output has an open collector Schottky- clamped transistor that interfaces to any CMOS logic between 4.5 and 15 volts. The 74OL6010/11 may also by used to drive power MOSFETS or transistors up to 15 volts. The Optologic coupler family typically offers propagation of delays of 60 ns and can support 15 MBaud data communication. The two input chips and the output chip are assembled in a 6-pin DIP high insulation voltage plastic package. It provides a with- stand test voltage of 5300 VRMS (1 minute). BUFFER INVERTER

FEATURES

• Industry first LSTTL to TTL and LSTTL to CMOS complete logic-to-logic optocoupler
• Incorporates LED drive circuitry — use as logic gate
• V ery high speed
• Choice of buffer or inverter
• Choice of TTL or CMOS compatible output up to 15 volts
• F an-out of 10 TTL loads, fan-in 1 LSTTL load
• Internal noise shield — very high CMR of ±15 kV/µS
• UL recognized (File #E90700)
• Same noise immunity as LSTTL/TTL.

APPLICATIONS

• T ransmission line interface — receiver and driver
• Excellent as bridged receiver in fast LAN highways
• Bus interface
• Logic family interface with ground loop noise elimination
• High speed AC/DC voltage sensing
• D river for power semiconductor devices
• L evel shifting
• Replaces fast pulse transformers

© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO PIN CONFIGURATION 1-V CCI (Input V CC ) 6-V CCO (Output V CC 2-V IN (Data In) 5-V O (Data Out) 3-GND, (Input GND) 4-GND O (Output GND) DEVICE CONFIGURATION Part Number Logic Compatibility Logic Function Output Configuration Input Output 74OL 6000 LSTTL TTL BUFFER TOTEM POLE 74OL 6001 LSTTL TTL INVERTER TOTEM POLE 74OL 6010 LSTTL CMOS BUFFER OPEN COLLECTOR 74OL 6011 LSTTL CMOS INVERTER OPEN COLLECTOR 22 kΩ TYP. INPUT Vcc GND LSTTL INPUT CIRCUIT Vcc 150 Ω TYP. TTL OUTPUT CIRCUIT GND OUTPUT Vcc R GND CMOS OUTPUT CIRCUIT OUTPUT L All Inputs 74OL6000/01 Output 74OL6010/11 Output

© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO SCHEMATIC LSTLL to TTL Buffer NOISE SHIELD 74OL6000 LSTLL to TTL Inverter NOISE SHIELD 74OL6001 LSTLL to CMOS Buffer NOISE SHIELD 74OL6010 LSTLL to CMOS Inverter NOISE SHIELD 74OL6011

© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO *All typical values are at T A =25°C

ELECTRICAL CHARACTERISTICS

A = 0°C to 70°C Unless otherwise specified) Parameter Symbol Min Typ* Max Units Test Conditions Notes 74OL6000 74OL6001 74OL6000/01 TTL OUTPUT 74OL6000/01 Input Supply Voltage V CCI 4.5 5.0 5.5 V 1 Output Supply Voltage V CCO 4.5 5.0 5.5 V 1 High-Level Input Voltage V IH

2.0 V 1

0.8 V 1

-1.2 V V CCI = 4.5 V, I I = -18 mA 1 High-Level Input Current I IH 1.0 40.0 µA V CCI = 5.5 V, V IH = 4.5 V 1 Low-Level Input Current I IL -200.0 -400.0 µA V CCI = 5.5 V, V IL = 0.4 V 1 Input Supply Current (high) I CCIH 10.0 14.0 mA V CCI = 5.5 V, V IN = V IH Input Supply Current (low) I CCIL 10.0 14.0 mA V CCI = 5.5 V, V IN = V IL High-Level Output Voltage V OH 2.4 3.0 V V IN = 2.0 V V IN = 0.8 V V CCI = 4.5 V, V CCO = 4.5 V, I OH = -400 mA 1 Low-Level Output Voltage V OL 0.3 0.6 VV IN = 0.8V V IN = 2.0V V CCI = 4.5 V, V CCO = 4.5 V, I OL = 16 mA 1 0.5 V CCI = 4.5 V, V CCO = 4.5 V, I OL = 4 mA High-Level Output Current I OH -8.0 -10.0 mA V IN = V IH V IN = V IL V CCI = 4.5 V, V CCO = 4.5 V, V OH = 2.4 V 1 Low-Level Output Current I OL 16.0 mA V IN = 0.8 V V IN = 2.0V V CCI = 4.5 V, V CCO = 4.5 V, V OL = 0.6 V 1 Short-Circuit Output Current I OS IN = V IH V IN = V IL V CCI = 5.5 V, V CCO = 5.5 V, 1 Output Supply Current (high) I CCOH 9.0 15.0 mA V IN = V IH V IN = V IL V CCI = 5.5 V, V O = V OH V CCO = 5.5 V 1 Output Supply Current (low) I CCOL 8.0 12.0 mA V IN = V IL V IN = V IH V CCI = 5.5 V, V O = V OL V CCO = 5.5 V 1 SWITCHING CHARACTERISTCS A = 25°C Unless otherwise specified) Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes TTL OUTPUT 74OL6000/01 V CCI = 5 V, V CCO = 5 V Propagation Delay Time For Output Low Level t PHL 60 100 ns 15, 17 1 Propagation Delay Time For Output High Level t PLH 70 100 ns 15, 17 1 Output Rise Time For Output High Level t r 45 n 15, 17 1 Output Fall Time For Output Low Level t f 5n s 15, 17 1

© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO *All typical values are at TA=25°C ELECTRICAL CHARACTERISTICS (TA = 0°C to 70°C Unless otherwise specified) Parameter Symbol Min Typ* Max Units Test Conditions Notes 74OL6010 74OL6011 74OL6010/11 CMOS OUTPUT 74OL6010/11 Input Supply Voltage V CCI 4.5 5.0 5.5 V 1 Output Supply Voltage V CCO 4.5 15.0 V 1,3 High-Level Input Voltage V IH 2.0 V 1 Low-Level Input Voltage V IL 0.8 V 1 Input Clamp Voltage V IK -1.2 V V CCI = 4.5 V, II = -18 mA 1 High-Level Input Current I IH 1.0 40.0 µA V CCI = 5.5 V, VIH = 4.5 V 1 Low-Level Input Current I IL -200.0 -400.0 µA V CCI = 5.5 V, VIL = -0.4 V 1 Input Supply Current (high) I CCIH 10.0 14.0 mA V CCI = 5.5 V, VIN = VIH 1 Input Supply Current (low) I CCIL 10.0 14.0 mA V CCI = 5.5 V, VIN = VIL 1 Low-Level Output Voltage V OL 0.4 0.6 VV IN = 0.8V V IN = 2.0V VCCI = 4.5 V, VCCO = 4.5 V, IOL = 16 mA 1 0.5 VCCI = 4.5 V, VCCO = 4.5 V, IOL = 4 mA High-Level Output Current I OH 1.0 100.0 µA V IN = VIH VIN = VIL VCCI = 4.5 V, VOH = 15 V, VCCO = 4.5 - 15 V 1 VCCO = 4.5 - 15 V 1 Output Supply Current (high) I CCOH 9.0 12.0 mA V IN = VIH VIN = VIL VCCI = 5.5 V, VO = VOH, VCCO = 4.5 V 1 11.0 18.0 VCCI = 5.5 V, VO = VOL, VCCO = 15 V Output Supply Current (low) I CCOL 8.0 12.0 mA V IN = VIL VIN = VIH VCCI = 5.5 V, VO = VOL, VCCO = 4.5 V 1 11.0 18.0 VCCI = 5.5 V, VO = VOL, VCCO = 15 V SWITCHING CHARACTERISTCS (TA = 25°C Unless otherwise specified) Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes TTL OUTPUT 74OL6010/11 VCCI = 5 V, VCCO = 5 V, RL = 470 Ω Propagation Delay Time For Output Low Level t PHL 60 120 ns 15, 18 1 Propagation Delay Time For Output High Level t PLH 100 180 ns 15, 18 1 Output Rise Time For Output High Level t r 50 ns 15, 18 1 Output Fail Time For Output Low Level t f 5n s 15, 18 1

3/19/03Page 6 of 15© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified) Parameter Symbol Device Value Units TOTAL DEVICE Storage Temperature T STG All -55 to +125 °C Operating Temperature T OPR All 0 to +70 °C Lead Solder Temperature T SOL All 260 for 10 sec °C Power Dissipation P D All 350 mW EMITTER Input Supply Voltage V CCI All 7 V Input Voltage V IN All 7 V DETECTOR Average Output Current I O (avg) All 40 mA Output Supply Voltage V CCO 74OL6000/01 7 V 74OL6010/11 18 Output Voltage V O 74OL6000/01 7 V 74OL6010/11 18 ELECTRICAL CHARACERISTICS (TA = 0°C to 70°C Unless otherwise specified) Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes 74OL6000/01/10/11 Common Mode Transient Immunity at Logic High Level Output CMH 5000 15000 V/µS VCCI = 5 V, VCCO = 5 V, VCM = 50 Vp-p 16, 19 Common Mode Transient Immunity at Logic Low Level Output CML -5000 -15000 V/µS 16, 19 Common Mode Coupling Capacitance C CM 0.005 pF Capacitance (input-output) C I-O 0.7 pF VI-O = 0, f = 1 MHz 2 Withstand Insulation Test Voltage V ISO 5300 VRMS TA = 25°C, t = 1 min, II-O ≤ 1mA 2 Insulation Resistance R ISO 10 Ω VI-O = 500 VDC 2

3/19/03Page 11 of 15© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO NOTE All dimensions are in inches (millimeters) Package Dimensions (Through Hole) Package Dimensions (Surface Mount) Package Dimensions (0.4” Lead Spacing) Recommended Pad Layout for Surface Mount Leadform 0.100 (2.54) TYP 0.020 (0.51) MIN 0.350 (8.89) 0.330 (8.38) 0.270 (6.86) 0.240 (6.10) PIN 1 ID. 0.022 (0.56) 0.016 (0.41) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.115 (2.92) 0.300 (7.62) TYP0° to 15° 0.154 (3.90) 0.100 (2.54) SEATING PLANE 0.016 (0.40) 0.008 (0.20) Lead Coplanarity : 0.004 (0.10) MAX 0.270 (6.86) 0.240 (6.10) 0.350 (8.89) 0.330 (8.38) 0.300 (7.62) TYP 0.405 (10.30) MAX 0.315 (8.00) MIN 0.016 (0.40) MIN PIN 1 ID. 0.016 (0.41) 0.008 (0.20) 0.100 (2.54) TYP 0.022 (0.56) 0.016 (0.41) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08)SEATING PLANE 0.165 (4.18) 0.020 (0.51) MIN SEATING PLANE 0.016 (0.40) 0.008 (0.20) 0.070 (1.78) 0.045 (1.14) 0.350 (8.89) 0.330 (8.38) 0.154 (3.90) 0.100 (2.54) 0.200 (5.08) 0.135 (3.43) 0.004 (0.10) MIN 0.270 (6.86) 0.240 (6.10) 0.400 (10.16) TYP 0.016 (0.41) 0.100 (2.54) TYP PIN 1 ID. 0.070 (1.78) 0.060 (1.52) 0.030 (0.76) 0.100 (2.54) 0.295 (7.49) 0.415 (10.54)

3/19/03Page 12 of 15© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO

ORDERING INFORMATION

Option Order Entry Identifier Description S. S Surface Mount Lead Bend SD .SD Surface Mount; Tape and Reel W. W 0.4" Lead Spacing 300 .300 VDE 0884 300W .300W VDE 0884, 0.4" Lead Spacing 3S .3S VDE 0884, Surface Mount 3SD .3SD VDE 0884, Surface Mount, Tape and Reel 74OL6000 V XX YY K 43 5 Definitions 1F airchild logo 2D evice number

3 VDE mark (Note: Only appears on parts ordered with VDE

option – See order entry table) 4T wo digit year code, e.g., ‘03’ 5T wo digit work week ranging from ‘01’ to ‘53’

6 Assembly package code

3/19/03Page 13 of 15© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO Reflow Profile (Black Package, No Suffix)

• Peak reflow temperature: 225° C (package surface temperature)
• Time of temperature higher than 183° C for 60–150 seconds
• One time soldering reflow is recommended 215°C, 10–30 s

225 C peak

Time (Minute) 300 250 200 150 100 Temperature (°C) Time above 183° C, 60–150 sec Ramp up = 3 C/sec

3/19/03Page 14 of 15© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO 0.1 µF 10 Ω1.1 KΩ 100 µF 1 KΩ 1.1 KΩ 1N6263 ALL DIODES 2N4252 2N4252 2N2222 PRSG 100 ns BIT INTERVAL 1 2 250 FT. 74OL6000 LS04 9 LS04 250 FT. 1110 250 FT.250 FT. LS04 LS04 BUFFER 600174OL 6001OL74 6001 OL74 6001 74OL 1000 FT. 75 Ω TERMINAION APPLICATION Local area data communication systems can greately improve their noise immunity by including OPOTOLOGIC gates in the design. The Optologic input amplifier offers the feature of very high input impedance that permits their use as bridged line receivers. The system show above illustrates an optically isolated transmitter and multidrop receiver system. The network uses a 74OL6000 and buffer (Figure D) to isolate the transmitter and drive the 75Ω coax cable. This application uses a 1000 ft. aerial suspension 75Ω CATV coax cable with data taps at 250 ft. intervals. The 74OL6001s function as bridged receivers, and as many as 30 receivers could be placed along the line with minimal signal degradation. The communication cable is terminated with a single 75Ω load at the far end of the line. Signal quality "Eye Pattern" is shown in Figures A, B and C with a 10MBaud NRZ Psuedo-Random Sequence (PRS). Traces 1-3 in Figure A describes the transmitter section. Traces 4-7 in Figure B show the output of the four Optologic bridged terminations. Traces 8-11 in Figure C illustrate "Eye Pattern" as seen at the output of a 74LS04 logic gate. The data quality is well preserved in that only a 30% Eye closure is seen at the receiver located 1000 ft. from the transmitter. The data communication system is completely optically isolated from all of the terminal equipments. Power for the transmitter CCO) and receiver (VCCI) is taken from an isolated power supply and distributed through a drain or messenger wire. Figure A Figure B Figure C HORIZONTAL = 20 ns/DIV 42-11 HORIZONTAL = 20 ns/DIV 42-12, 02 HORIZONTAL = 20 ns/DIV 42-13/03 VERTICAL = 2 V/DIV VERTICAL = 2 V/DIV VERTICAL = 2 V/DIV Figure D Buffer

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 3/19/03Page 15 of 15© 2003 Fairchild Semiconductor Corporation HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER 74OL6000 TTL INVERTER 74OL6001 CMOS BUFFER 74OL6010 CMOS INVERTER 74OL6011 LSTTL TO