74OL6000

74OL6000 QT | Alldatasheet

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OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS eS TTL BUFFER 740L6000 LSTTL to TTL INVERTER 740L6001 OPTO/LOGIC CMOS BUFFER 740L6010 ™ CMOS INVERTER 740L6011 GADER INFORMATION PART Se Onl OUTPUT @ Industry first LSTTL to TTL and LSTTL to NUMBER| INPUT | OUTPUT | CONFIGURATION] CMOS complete logic-to-logic optocoupler 740L6000] usTTL [| TTL | BUFFER | TOTEMPOLE | m Incorporates LED drive circuitry—use as 7406001] LSTTL | TTL | INVERTER] TOTEM POLE logic gate 740L6010] LSTTL | CMOS | BUFFER |OPENCOLLECTOR| , ov ger 74oteo11| LSTTL | CMOS_| INVERTER | OPEN COLLECTOR| ™ Very high speed = Choice of buffer or inverter = Choice of TTL or CMOS compatible output up to 15 volts SYMBOL a Faroutt 0 Toads ann 1.877 ad = Internal noise shield—very high CMR of +15 A " KV/ps . Yansmission line interface—receiver and ® Provides superior 5300 VRMS Withstand = Excellent as bridged receiver in fast LAN Test Voltage (WIV)—guarantees 480 vac Butfer highways pera ™ Bus interface = Compact 6-pin DIP = Logic family interface with ground loop noise & UL recognized (File #£90700) choimation 1 Same noise immunity as LSTTL/TTL. = High speed AC/DC voltage sensing '® Driver for power semiconductor devices PIN CONFIGURATION Inverter = Level shifting = Replaces fast pulse transformers 1-Vea (Input Vec) 6 Veco (Output Vc) 2-Vy, (Data in) 5-Vo (Data out) 3-GND, (Input GND) _ 4-GND. (Output GND) 74016000 74016001 74016010 74016011 NOISE SHIELD L 1} 1} Ly ] hig 4 lGuinl f Gulia re} OR 23} ey 2004 2005 C2002 2003 LSTTL to TTL Buffer LSTTL to TTL Inverter LSTTL to CMOS Buffer LSTTL to CMOS Inverter

QT] HIGH-SPEED OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS eel

DESCRIPTION

OPTOLOGIC™ is the first family of This novel integration scheme The 740L6010/11 may also be used truly logic compatible optically eliminates CTR degradation over to drive power MOS FETS or coupled logic interface gates. time and temperature. transistors up to 15 volts. The family consists of four device The emitter is optically coupled to an The Optologic coupler family types offering LSTTL to TTL and integrated photodetector/high-gain, typically offers propagation of delays LSTTL to CMOS interfacing. Each of high-speed output amplifier IC. The __of 60 ns and can support 15 MBaud these interfacing functions is superior 15 kV/us common-mode data communication. available as a buffer (A=B), or as an noise rejection is ensured through inverter (A=B). the use of an optically transparent The two input chips and the output noise shield. chip are assembled in a 6-pin DIP. The LSTTL input compatibility is high insulation voltage plastic provided by an input integrated The TTL compatible output has a package. It provides a withstand test circuit, with industry standard logic _totem-pole with a fan-out of 10. The _voltage of 500 VRMS (1 minute), levels. This input amplifier IC CMOS compatible output has an which is recognized as a working switches a temperature open collector Schottky-clamped voltage of 480 VRMS. compensated current source driving _ transistor that interfaces to any ahigh speed GaAsP/GaAs 700nm CMOS logic between 4.5 and 15 LED emitter. volts. Vee [77 o- Veo ---———0 vec 22 kia TYP. 150.0 TYP AL INPUT -- -- . ouTPUT ourput = Gno _ _ LSTTL INPUT CIRCUIT = ano = GND c2010 TTL OUTPUT CIRCUIT Mos OUTPUT CIRCUIT All Inputs 2009 2026 7401.6000/01 Output 740L6010/11 Output ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS 7401.6000/01 7401L.6010/11 Output current cee ceceeeeeeeseseeees 40MA— Outputourtent o.oo veveeeees 40MA Lead temperature (soldering, 10 sec) .. 260°C —_ Lead temperature (soldering, 10 sec) seve. 260°C *See Fig. 12 for maximum allowable output supply voltage.

OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS SS ELECTRICAL CHARACTERISTICS (1,=0°C to 70°C Unless Otherwise Specified) PARAMETER SYM = MIN ‘TyP* MAX UNITS —___TESTCONDITIONS__ rig. Notes! 74016000 74016001 740L6000/01 TTL OUTPUT 74016000/01 Input supply voltage Voo 45 5.0 55 v 1 Outputsupply y. 450 5085 v 1 voltage oxo High-levelinput ya v ; voltage ia Low-levelinput 08 Vv ; voltage a Input clamp _ = -_ voltage Vu 120° Veoi=4.5 V, L=-18 mA, 1 High-level input = = current a 10 40.0 4A Veo=5.5 V, Vie=4.5 V 1 Low-level input _ a = - current he 200.0 -400.0 4A Voo=5.5 V, Vy=0.4 V 1 Input supply — 7 current (high) eo 100 14.0 = mA Veo=5.5 V, Vn=Vos 1 Input supply _ 7 current (low) = 100 140 = mA Veo=5.5 V, Vn=Vi 1 High-level = = Vea=4.5 V, Veco=4.5 V, ‘output voltage Vow 24 3.0 v Vn=2.0 V Vy=0.8 V lov=—400pA 1 Veor=4.5 V, Voco=4.5 V, os OV co=4.5 V, Vero=4.5 V, output voltage y Vara V, Vou=45V, 08 ln =4 mA High-level - - = = Voa=4.5 V, Veco=4.5 V, output current!" 80 10.0 mA Vo=Ver Vne=Ve Vor=2.4 V 1 Low-level _ . Vea=4.5 V, Veco=4.5 V, cutgtcorent l= 160 MA Ww=0.8V Vy=2.0V cosy 1 Short-circuit 7 ~ ~ Output supply <I = Voa=5.5 V, Vo=Vor, current (high) lecon 9.0 15.0 mA Vin= Vow Va=Ve Veoo=5.5 V 1 Output supply Z Z Vea=5.5 V, Vo=Vou ‘current (low) Necon 8.0 12.0 mA Vane Vu VV Veco=5.5 V 1 *All typical values are at T.=25°C SWITCHING CHARACTERISTICS (1,=25°C Unless Otherwise Specified) PARAMETER ‘SYM MIN ‘TYP MAX ‘UNITS ‘TEST CONDITIONS FIG. NOTES| TTL OUTPUT 7401L6000/01 Propagation delay time for output low level toe 60 100 ns 15,17 1 Propagation delay time for output high level tun 70 100 ns Veo 5V, Vease5V 15,17 1 Output rise time for output high level t 4“ ns 15,17 1 ‘Output fall time for output low level iW 5 ns 15,17 1

OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS EEE EEO el ELECTRICAL CHARACTERISTICS (1,=0°C to 70°C Unless Otherwise Specified) PARAMETER SYM MIN TYP* MAX UNITS —______TESTCONDITIONS _ rig. ores 74016010 ‘74016011 740L6010/11 CMOS OUTPUT 740L6010/11 Input supply voltage Veet 45 5.0 55 Vv 1 Output supply voltage Veco 45 15.0 v 1,3 High-level input voltage Vow 20 v 1 Low-level input voltage Ve 08 ov 1 Input clamp Ve “12 =~ Vei=4.5 V, l=—18 mA, 1 High-level input bn 10° 40.0 pA Veo=5.5 V, V4.5 V 1 Low‘levelinput |, 200.0 -400.0 yA Veo=5.5 V, Va=0.4 V 1 Input supply - - current (high) _'e=™ 100 140 mA Veo=5.5 V, Vir=Ver 1 Input supply = = current (iow) 100 140)—omA Veo=5.5 V, Va=Vi 1 06 Vea=4.5 V, Voco=45 V, Lowievel Va 04 ——— Vv Wyeoev Vyezoy ———=t6ma : output voltage os Voo=4.5 V, Voo=45V, la=4 mA High-level = =! Voa=4.5 V, Vox=15 V, output current! 1.0 100.00 0 HA Vn=Vn Va=Ve Veco=4.5 -15 V 1 Low-level _ _. Veo=4.5 V, Va=0.6 V, outputcurent = 160 MA — Vy=0.8V Wu=2.0V Vezo=4.5 ~15V 1 Voo=5.5 V, Vo=Vou, 90 12.0 V-Co=4.5 V Sutput supAty ln ————— MA WV VV eee BV 1 Current (high} Vin 5.5 V, Vo=V. 11.0 18.0 oo vey Veco= 15 V 30. 120 Veo=5.5 V, Vo=Vou Output supply beco. ——— m wn Va=V, ————Wen4SV 1 current (low) Veo™5.5 V, Vo=Veu 1.0 18.0 Veco= 15 V “All typical values are at T,=25°C SWITCHING CHARACTERISTICS (7,=25°C Uniess Otherwise Specified) PARAMETER sYM MIN TYP MAX UNITS: ‘TEST CONDITIONS FIG. NOTES} TTL OUTPUT 740L6010/11 Propagation delay time for cutput low level toe 60 120 ns 15,181 Propagation delay time for output high level ha 100 160 ns Vox V, 1618 1 Output rise time Veoo=5 V, Ri=470 0 for output high level * 50 ne 15,181 Output fall time for output low level ‘ 5 ns 15,181

OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS EEE nnn nel ELECTRICAL CHARACTERISTICS (1,=0°C to 70°C Unless Otherwise Specified) PARAMETER SYMBOL MIN TYP MAX UNITS ‘TEST CONDITIONS FIG. NOTE: 740L6000/01/10/11 Common mode transient immunity at logic high level output CM. 000, 15000 VHS V..=5V, Veco=5 V, 16.19 Vew=50 Vow Common mode transient immunity _ _ at logic low level output cM, 5000-15000 Vins 16,19 Common mode coupling citance Cow 0.005, pF Capacitance (input-output) Co 07 pF Vio=0, f=1 MHz 2 Withstand insulation test T.=25°C, voltage Vico 5300 VRMS t=1 min, ho <1 pA 2 Insulation resistance Reso 10" a Vio=500 VDC 2 TYPICAL CHARACTERISTIC CURVES (1,=25°C Uniess Otherwise Specified) z 8 z 100 f,f-- TT TTT) < ey ee 3 4 a ee Fa [co — TAOLBOOO-6O 5 | at ee fq Vooi= 5.5 Hi 3" cal § 1007— vy -04v oe 3 Sl 3 | a) lec — 74016001-6011 2 = 5 Speen raganr sen 1 eT 2 {| esl i | 6 Voc = 5.5 V: 5 sL_ [| Sr a a 8 “49-200 20 40 60 00 100 ‘Ta — AMBIENT TEMPERATURE — (°C) ‘Ta — AMBIENT TEMPERATURE — (°C) ©2028 C2029 Ambient Temperature vs. Ambient Temperature Zz 60 z PALIT TT TT] goe-LLL TT 5 ee = T 4 ee 2 i . St lecon g 30 Veco = 45V tt 3° SSS eGo = Vou = 08V > tO logon a Von =24v 7 J | z , ossenennncfpeeh ICCOL © 0 —— +— 3° F=rosoroeo% 7 Iecon 2 6 | 2 | voo=ssv ge a 2 3b Voco=16Vv 3 +10 a: lon E ° |= 7oLsoroeon = 740160007600 i (7401.6000/6001) Veo = 5.5 V Veci = 5.5 V Q -20 1 Q -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 ~ — Ta — AMBIENT TEMPERATURE — (°C) Ta — AMBIENT TEMPERATURE — (°C) C2030 C2031 vs. Ambient Temperature Ambient Temperature

OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS EO TYPICAL CHARACTERISTIC CURVES (1,=25°C Unless Otherwise Specified) (Cont'd)

5 S05

| T att vecos sv “Ton = 400 nA 5 04 e LLEET BL | pee | Po) eR EE 3 ° 3 PE ry @lo=4ma g dE messy |

5 Sos Voog= 48

24-200 20 40 6) 80 100 a) Ta — AMBIENT TEMPERATURE — (°C) > Th — AMBIENT TEMPERATURE — (°C) ©2032 C2033 Fig. 5. High-Level Output Voltage Fig. 6. Low-Level Output Voltage vs. Ambient Temperature vs. Ambient Temperature 5 or ———— | veco= Soy Veen = 45 V | ew = 200 ‘ ooo = 18V F 20} peniod= 148 +11 1 |_| eee ot gs ———— 3 - ne 1 8S Serer re

5 TPA = woettl | tt

§ Ot = — : LY : 4 o Lt iLL TT TT | “4g 200 ~=20 40606000 ‘4-200 2040 60 80 100 Ta — AMBIENT TEMPERATURE — (°C) Ta — AMBIENT TEMPERATURE — (°C) acs 2035 Fig. 7. 740L6010/11 Leakage Current Fig. 8. 7401L6000/01 Switching Times vs. Ambient Temperature vs. Ambient Temperature Sears ar 2 20] wou z 2 vopdeeoieiecet thet oo 100 eect et] Be LT tco- ‘sv a 23 7 Von av} @ Perry 32 sf vol - av Zz FEEEELT B= a Ru__= 470 £1 (74016010/6011) oe a 7 83 | a co 2 Ss oe a -40 -20 0 20 40 60 80 100 oO 500 1000 1500 2000 2500 Ta — AMBIENT TEMPERATURE — (°C) Vo — COMMON MODE TRANSIENT 2096 2037 vs. Ambient Temperature ‘Common Mode Voltage 1-62

OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS SN TYPICAL CHARACTERISTIC CURVES (,=25°C Uniess Otherwise Specified) (Cont'd) 12) MAXIMUM ALLOWABLE POWER 7 TU . ee Elie 4 & I “TTT TTT 3s wo LTT TTT TT ee ge ar ate| ST $) a Tee | g6 PSS Z| RANGE FoR moLs000/6001 Br Sogn 3 ¢ n| £8 sol epee | ewe §? To | easesy [TT TT | * CT TTT e« OTT : 1 ; 456 7 8 9 10 11 12 13:14:15 465 6 7 8 9 10111213 1415 Vcc — SUPPLY VOLTAGE — (V) Veco — OUTPUT SUPPLY VOLTAGE — (V) C2038 C2039 Supply Voltage Ambient Temperature Ss 16 5 100 TNX TT | TT : gL IAT TT $ Bu} VON T - HES LOT 8 g go | TN 5 : g Dy naa Fis 2 z 3 |/ 5 10 [| | Vee = 5.0V | 7200) | 09 = -40 -20 0 20 40 60 80 100 ~300) 5 o 1 2 3 4 5 6 > Ta — AMBIENT TEMPERATURE — (°C) Vw — INPUT VOLTAGE — (V)

2040 C2041

Ambient Temperature Input Voltage louse “ Lhe ue d TH 888mm Fig. 15. Switching Time Test Circuit Fig. 16. Common Mode Rejection Test Circuit

OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS SL TYPICAL CHARACTERISTIC CURVES (1,=25°C Unless Otherwise Specified) (Cont'd) TF weuty =-f-----} gy woe ate [ ee | =| v a'r pst Ea = aad feotsomn ---\\---- f= =13y (souseny -A — vs. Ambient Temperature 74QL6010/11 PACKAGE DIMENSIONS Vom Vom. Vow ov / \\ “a Pa i = Vou Ma 1 mad LZ. ~—-Vo=2.0v (min) 83 6.86 1k — Vo = 0.8 V (MAX) 6.10 03 /\\ rr] Vou cM. me . + 2046 L > Fig. 19. Common Mode Rejection

8.89 Waveforms

8.38 2.33 REF INPUT, | INPUT output oureut Vee | I 1) GND GNO |} it Veg BUS | | | Bus BUS || yy BUS 254 19 7 Ho wel] [ve egy i ee GO PE i MAX DATA i + DATA : t iv | = our a ry a ed Asy7 = ree Oe 254 ta TO By I AMIN Os moo oy I ut Mi \\ | 1.50 it i H it 056 124 V4 | i i} rT 20a? 040 DIMENSIONS IN mm Fig. 20. Suggested PCB Lay-out PACKAGE CODE K svis03a 1. The Veco and Vcc, supply voltages to the device must each be bypassed by a 0.1 uf capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize the operation of the high-gain amplifiers. Failure to provide the bypass will impair the DC and switching properties. The total lead length between capacitor and optocoupler should not exceed 1.5mm. See Fig. 20. 2. Device considered a two-terminal device: Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together. 3. For example, assuming a Veo, of 5.0 V, and an ambient temperature of 70°C, the maximum allowable Veco is 12.1 V. 1-64

OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS SS APPLICATION 1 2 3 \\ ZA vsoLgooo BUFFER = TF C7 CC Local area data communication Nt S ¥ ‘ systems can greatly improve ther \\Vireorseo: Vjeorso0r Yrrorsoo1 V/rsousoo: noise immunity by including 4 & & z The Optologic input amplifier offers coos the feature of very high input impedance that permits their use as__signal degradation. The seen at the output of a 74LS04 logic bridged line receivers. The system communication cable is terminated _gate. The data quality is well shown above illustrates an optically _with a single 75 load at the farend —_ preserved in that only a 30% Eye isolated transmitter and multidrop of the line. closure is seen at the receiver receiver system. The network uses a located 1000 ft. from the transmitter. 74016000 and butfer (Figure D) to —-Signal quality “Eye Pattern” is isolate the transmitter and drive the shownin Figures A,BandC witha The data communication system is 750 coax cable. This application 40MBaud NRZ Psuedo-Random completely optically isolated from all uses a 1000 ft. aerial suspension 750 — Sequence (PRS). Traces 1-3 in of the terminal equipments. Power CATV coax cable with data taps at Figure A describes the transmitter for the transmitter (Vcco) and receiver 250 ft. intervals. The 740L6001s section. Traces 4-7 in Figure B show (Vcc) is taken from an isolated power function as bridged receivers, and as __the output of the four Optologic supply and distributed through a many as 30 receivers could be bridged terminations. Traces 8-11 in _drain or messenger wire. placed along the line with minimal Figure C illustrate “Eye Pattern” as oo a 7 < sen — ns a - —cepenomnememeegtomnreeree a : — — HORIZONTAL =20 ns/DIV. 4241 HORIZONTAL=20 ns/DIV 42-12,02 HORIZONTAL=20 ns/DIV 42:13,03 VERTICAL=2 ViDIV VERTICAL=2 VIDIV VERTICAL=2 ViDIV Figure A Figure B Figure C MT Sian 10 —All Optologic Gate Input and Output Amplifiers Bypassed With 0.1 uF Capacitors 2ue2s2 — PRSG=Pseudo Random Sequence Generator uae —1 to 11 Refer To Testpoints; See Waveforms on Figs. A, B and C ff ana2ee ALL DIODES i" = caer Figure D Buffer 1-65