Logic IC

74LXCH8T245RHLRG4

Texas Instruments

SN74LXCH8T245 8-bit Translating Transceiver with Configurable Level Shifting REVISED MARCH 2021

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SN74LXCH8T245 8-bit Translating Transceiver with Configurable Level Shifting

1 Features

Fully Configurable Dual-Rail Design Allows Each Port to Operate from 1.1 V to 5.5 V
Robust, Glitch-Free Power Supply Sequencing
Up to 420-Mbps Support for 3.3 V to 5.0 V
Bus Hold on Data Inputs Eliminates the Need for External Pull-Up and Pull-Down Resistors
Schmitt-Trigger Control Inputs Allow for Slow or Noisy Inputs
Control Inputs with Integrated Static Pull-Down Resistors Allow for Floating Control Inputs
High Drive Strength (up to 32 mA at 5 V)
Low Power Consumption – 4-µA Maximum (25°C) – 12-µA Maximum (–40°C to 125°C)
VCC Isolation and VCC Disconnect feature – If Either V CC Supply is < 100 mV All I/O's Become High-Impedance – I off-float Supports VCC Disconnect Operation
I off Supports Partial-Power-Down Mode Operation
Compatible with LVC Family Level Shifters
Control Logic (DIR and OE) are Referenced to VCCA
Operating Temperature from –40°C to +125°C
Latch-Up Performance Exceeds 100 mA per JESD 78, Class II
ESD Protection Exceeds JESD 22 – 4000-V Human-Body Model – 1000-V Charged-Device Model

2 Applications

Eliminate Slow or Noisy Input Signals
Driving Indicator LEDs or Buzzers
Debouncing a Mechanical Switch
General Purpose I/O Level Shifting
Push-Pull Level Shifting (UART, SPI, JTAG, and so forth.)

3 Description

The SN74LXCH8T245 is an 8-bit, dual-supply noninverting bidirectional voltage level translation device with bus-hold circuitry. Ax pins and control pins (DIR and OE) are referenced to VCCA logic levels, and Bx pins are referenced to V CCB logic levels. The A port is able to accept I/O voltages ranging from 1.1 V to 5.5 V, while the B port can accept I/O voltages from 1.1 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a summary of the operation of the control logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74LXCH8T245PWR TSSOP (24) 7.80 mm × 6.40 mm SN74LXCH8T245RHLR VQFN (24) 5.50 mm × 3.50 mm (1) See the orderable addendum at the end of the data sheet for all available packages. A8 B8 A1 B1 OE DIR VCCA VCCB To other 7 channels GND Bus-Hold Bus-Hold Functional Block Diagram SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.2 Receiving Notification of Documentation Updates..26

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (January 2021) to Revision B (March 2021) Page

Changed the t sk – output skew's maximum operating free-air temperature (TA) range for VCCI and VCCO in the Changes from Revision * (January 2021) to Revision A (January 2021) Page SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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5 Pin Configuration and Functions

All packages are on the same relative scale. Figure 5-1. PW, and RHL Package 24-Pin TSSOP, and VQFN Transparent Top View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME PW, RHL A1 3 I/O Input or output A1. Referenced to VCCA. A2 4 I/O Input or output A2. Referenced to VCCA. A3 5 I/O Input or output A3. Referenced to VCCA. A4 6 I/O Input or output A4. Referenced to VCCA. A5 7 I/O Input or output A5. Referenced to VCCA. A6 8 I/O Input or output A6. Referenced to VCCA. A7 9 I/O Input or output A7. Referenced to VCCA. A8 10 I/O Input or output A8. Referenced to VCCA. B1 21 I/O Input or output B1. Referenced to VCCB. B2 20 I/O Input or output B2. Referenced to VCCB. B3 19 I/O Input or output B3. Referenced to VCCB. B4 18 I/O Input or output B4. Referenced to VCCB. B5 17 I/O Input or output B5. Referenced to VCCB. B6 16 I/O Input or output B6. Referenced to VCCB. B7 15 I/O Input or output B7. Referenced to VCCB. B8 14 I/O Input or output B8. Referenced to VCCB. DIR 2 I Direction-control signal for all ports. Referenced to VCCA. GND 11 — Ground. 12 — Ground. 13 — Ground. OE 22 I Output Enable. Pull to GND to enable all outputs. Pull to VCCA to place all outputs in high-impedance mode. Referenced to VCCA. VCCA 1 — A-port supply voltage. 1.1 V ≤ VCCA ≤ 5.5 V. VCCB 23 — B-port supply voltage. 1.1 V ≤ VCCB ≤ 5.5 V. 24 — B-port supply voltage. 1.1 V ≤ VCCB ≤ 5.5 V. PAD — — Thermal pad. May be grounded (recommended) or left floating. www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74LXCH8T245

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCA Supply voltage A –0.5 6.5 V VCCB Supply voltage B –0.5 6.5 V VI Input Voltage(2) I/O Ports (A Port) –0.5 6.5 VI/O Ports (B Port) –0.5 6.5 Control Inputs –0.5 6.5 VO Voltage applied to any output in the high-impedance or power-off state(2) A Port –0.5 6.5 V B Port –0.5 6.5 VO Voltage applied to any output in the high or low state(2) (3) A Port –0.5 VCCA + 0.5 V B Port –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current –50 50 mA Continuous current through VCC or GND –200 200 mA Tj Junction Temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure beyond the limits listed in Recommended Operating Conditions. may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCCA Supply voltage A 1.1 5.5 V VCCB Supply voltage B 1.1 5.5 V VIH High-level input voltage Data Inputs (Ax, Bx) (Referenced to VCCI) VCCI = 1.1 V - 1.3 V VCCI x 0.8 V VCCI = 1.4 V - 1.95 V VCCI x 0.65 VCCI = 2.3 V - 2.7 V 1.7 VCCI = 3.0 V - 3.6 V 2 VCCI = 4.5 V - 5.5 V VCCI x 0.7 VIL Low-level input voltage Data Inputs (Ax, Bx) (Referenced to VCCI) VCCI = 1.1 V - 1.3 V VCCI x 0.2 V VCCI = 1.4 V - 1.95 V VCCI x 0.35 VCCI = 2.3 V - 2.7 V 0.7 VCCI = 3.0 V - 3.6 V 0.8 VCCI = 4.5 V - 5.5 V VCCI x 0.3 IOH High-level output current VCCO = 1.1 V –0.1 mA VCCO = 1.4 V –2 VCCO = 1.65 V –4 VCCO = 2.3 V –12 VCCO = 3 V –24 VCCO = 4.5 V –32 IOL Low-level output current VCCO = 1.1 V 0.1 mA VCCO = 1.4 V 2 VCCO = 1.65 V 4 VCCO = 2.3 V 12 VCCO = 3 V 24 VCCO = 4.5 V 32 VI Input voltage 0 5.5 V VO Output voltage Active State 0 VCCO V Tri-State 0 5.5 Δt/Δv Input transition rise and fall time 20 ns/V TA Operating free-air temperature –40 125 °C (1) V CCI is the VCC associated with the input port. VCCO is the VCC associated with the output port.

6.4 Thermal Information

THERMAL METRIC(1) SN74LXC8T245 UNITPW (TSSOP) RHL (VQFN)

24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 98.2 45.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 42.3 41.0 °C/W RθJB Junction-to-board thermal resistance 53.3 23.3 °C/W YJT Junction-to-top characterization parameter 5.8 2.2 °C/W YJB Junction-to-board characterization parameter 52.9 23.3 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A 13.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics app report. www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74LXCH8T245

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –40°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX VT+ Positive- going input- threshold voltage Control Inputs (OE, DIR) (Referenced to VCCA) V 3 V 3 V 1.48 1.92 1.48 1.92 VT- Negative- going input- threshold voltage Control Inputs (OE, DIR) (Referenced to VCCA) V 2.3 V 2.3 V 0.56 1 0.56 1 3 V 3 V 0.89 1.5 0.89 1.5 4.5 V 4.5 V 1.51 2 1.51 2 ΔVT Input- threshold hysteresis (VT+ – VT-) Control Inputs (OE, DIR) (Referenced to VCCA) V 3 V 3 V 0.46 0.72 0.46 0.72 VOH High-level output voltage (3) IOH = –100 µA 1.1V – 5.5V 1.1V – 5.5V VCCO – 0.1 VCCO – 0.1 V IOH = –4 mA 1.4 V 1.4 V 1 1 IOH = –8 mA 1.65 V 1.65 V 1.2 1.2 IOH = –12 mA 2.3 V 2.3 V 1.9 1.9 IOH = –24 mA 3 V 3 V 2.4 2.4 IOH = –32 mA 4.5 V 4.5 V 3.8 3.8 VOL Low-level output voltage (4) V IOL = 4 mA 1.4 V 1.4 V 0.3 0.3 IOL = 8 mA 1.65 V 1.65 V 0.45 0.45 IOL = 12 mA 2.3 V 2.3 V 0.3 0.3 IOL = 24 mA 3 V 3 V 0.55 0.55 IOL = 32 mA 4.5 V 4.5 V 0.55 0.55 IBHL Bus-hold low sustaining current Port A or Port B (6) VI = 0.39 1.1 V 1.1 V 4 4 µA VI = 0.49 1.4 V 1.4 V 15 10 VI = 0.58 1.65 V 1.65 V 25 20 VI = 0.70 2.3 V 2.3 V 45 45 VI = 0.80 3 V 3 V 75 75 VI = 1.35 4.5 V 4.5 V 100 100 SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –40°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX IBHH Bus-hold high sustaining current Port A or Port B (7) VI = 0.71 V 1.1 V 1.1 V –4 –4 µA VI = 0.91 V 1.4 V 1.4 V –15 –10 VI = 1.07 V 1.65 V 1.65 V –25 –20 VI = 1.70 V 2.3 V 2.3 V –45 –45 VI = 2.00 V 3 V 3 V –75 –75 VI = 3.15 V 4.5 V 4.5 V –100 –100 IBHLO Bus-hold low overdrive current (8) Ramp input up VI = 0 to VCCI 1.3 V 1.3 V 75 75 µA 1.6 V 1.6 V 125 125 1.95 V 1.95 V 200 200 2.7 V 2.7 V 300 300 3.6 V 3.6 V 500 500 5.5 V 5.5 V 900 900 IBHHO Bus-hold high overdrive current (9) Ramp input down VI = VCCI to 0 1.3 V 1.3 V –75 –75 µA 1.6 V 1.6 V –125 –125 1.95 V 1.95 V –200 –200 2.7 V 2.7 V –300 –300 3.6 V 3.6 V –500 –500 5.5 V 5.5 V –900 –900 II Input leakage current Control inputs (DIR, OE) VI = VCCA or GND Data Inputs (Ax, Bx) VI = VCCI or GND Ioff Partial power down current A Port VI or VO = 0 V - 5.5 V µA B Port VI or VO = 0 V - 5.5 V Ioff-float Floating supply Partial power down current A Port µA B Port IOZ Tri-state output current (5) A or B Port: (Rev) VI = VCCI or GND VO = VCCO or GND OE = VT+(MAX) 1.1V – 5.5V 1.1V – 5.5V –1 1 –1 1 –2 2 µA ICCA VCCA supply current VI = VCCI or GND IO = 0 1.1V – 5.5V 1.1V – 5.5V 2 4 8 µA

5.5 V 0 V 2 4 8

5.5 V Floating 2 4 8

VI = VCCI or GND IO = 0 1.1V – 5.5V 1.1V – 5.5V 2 4 8 µA 0 V 5.5 V 2 4 8 Floating 5.5 V 2 4 8 www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74LXCH8T245

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –40°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX ICCA + ICCB Combined supply current VI = VCCI or GND IO = 0 1.1V – 5.5V 1.1V – 5.5V 4 8 12 µA ΔICCA VCCA additional supply current per input Control inputs (DIR, OE): VI = VCCA – 0.6 V A port = VCCA or GND B Port = open

3.0 V –

5.5V 5.5V 50 75 µA Ci Control Input Capacitance VI = 3.3 V or GND 3.3 V 3.3 V 2.9 5 5 pF Cio Data I/O Capacitance OE = VCCA, VO = 1.65V DC +1 MHz -16 dBm sine wave 3.3 V 3.3 V 5.9 10 10 pF (1) V CCI is the VCC associated with the input port. (2) V CCO is the VCC associated with the output port. (3) Tested at V I = VT+(MAX). (4) Tested at V I = VT-(MIN). (5) For I/O ports, the parameter I OZ includes the input leakage current. (6) I BHL should be measured after lowering VI to GND and then raising it to the defined input voltage. (7) I BHH should be measured after raising VI to VCCI and then lowering it to the defined input voltage. (8) An external driver must source at least I BHLO to switch this node from low-to-high. (9) An external driver must sink at least I BHHO to switch this node from high to low. SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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6.6 Switching Characteristics, VCCA = 1.2 ± 0.1 V See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay A B -40°C to 85°C 10 65 10 31 7 25 7 24 5 22 5 21 ns -40°C to 125°C 10 70 10 33 7 27 7 26 5 24 5 23 B A -40°C to 85°C 10 62 10 55 10 49 8 42 8 40 8 39 -40°C to 125°C 10 68 10 60 10 54 8 47 8 45 8 44 tdis Disable time OE A -40°C to 85°C 20 64 20 64 20 64 20 64 20 64 20 64 ns -40°C to 125°C 20 69 20 69 20 69 20 69 20 69 20 69 OE B -40°C to 85°C 20 80 20 62 20 54 20 48 20 47 20 45 -40°C to 125°C 20 85 20 67 20 59 20 52 20 50 20 48 ten Enable time OE A -40°C to 85°C 20 90 20 91 20 91 20 91 20 90 20 90 ns -40°C to 125°C 20 97 20 98 20 97 20 96 20 96 20 96 OE B -40°C to 85°C 20 95 20 57 15 48 10 38 10 36 10 36 -40°C to 125°C 20 100 20 61 15 53 10 42 10 39 10 39 www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74LXCH8T245

6.7 Switching Characteristics, VCCA = 1.5 ± 0.1 V See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay A B -40°C to 85°C 10 52 5 25 5 23 5 17 5 14 3 13 ns -40°C to 125°C 10 57 5 26 5 23 5 18 5 16 3 14 B A -40°C to 85°C 8 36 7 28 7 26 5 20 5 18 5 17 -40°C to 125°C 8 40 7 29 7 26 5 22 5 20 5 18 tdis Disable time OE A -40°C to 85°C 15 40 15 40 15 40 15 40 15 40 15 40 ns -40°C to 125°C 15 44 15 44 15 44 15 44 15 44 15 44 OE B -40°C to 85°C 20 69 20 50 15 45 15 35 15 34 14 31 -40°C to 125°C 20 74 20 54 15 48 15 39 15 37 14 33 ten Enable time OE A -40°C to 85°C 15 48 15 48 15 48 15 48 15 48 15 48 ns -40°C to 125°C 15 52 15 52 15 52 15 52 15 52 15 52 OE B -40°C to 85°C 20 85 15 50 15 40 10 31 10 26 10 24 -40°C to 125°C 20 91 15 54 15 44 10 33 10 29 10 26 SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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6.8 Switching Characteristics, VCCA = 1.8 ± 0.15 V See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay A B -40°C to 85°C 8 50 6 21 6 18 4 14 4 11 2 10 ns -40°C to 125°C 8 53 6 23 6 20 4 15 4 12 2 11 B A -40°C to 85°C 5 32 5 21 5 19 4 17 4 15 4 15 -40°C to 125°C 5 33 5 23 5 21 4 18 4 16 4 16 tdis Disable time OE A -40°C to 85°C 10 34 10 33 10 33 10 33 10 33 10 33 ns -40°C to 125°C 10 36 10 35 10 35 10 35 10 35 10 35 OE B -40°C to 85°C 20 64 15 45 15 40 12 31 12 31 10 26 -40°C to 125°C 20 69 15 49 15 44 12 33 12 38 10 28 ten Enable time OE A -40°C to 85°C 10 38 10 38 10 38 10 38 10 38 10 38 ns -40°C to 125°C 10 40 10 40 10 40 10 40 10 40 10 40 OE B -40°C to 85°C 20 84 15 47 10 38 10 29 10 25 8 23 -40°C to 125°C 20 89 15 51 10 42 10 30 10 26 8 25 www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74LXCH8T245

6.9 Switching Characteristics, VCCA = 2.5 ± 0.2 V See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay A B -40°C to 85°C 7 40 5 21 4 16 3 12 3 10 3 8 ns -40°C to 125°C 7 45 5 22 4 17 3 13 3 11 3 9 B A -40°C to 85°C 5 26 5 16 5 15 4 12 3 11 3 10 -40°C to 125°C 5 28 5 17 5 15 4 13 3 12 3 11 tdis Disable time OE A -40°C to 85°C 10 24 10 24 10 24 10 24 10 22 10 24 ns -40°C to 125°C 10 26 10 26 10 24 10 24 10 24 10 24 OE B -40°C to 85°C 15 56 15 41 12 34 12 25 10 24 10 21 -40°C to 125°C 15 62 15 44 12 37 12 29 10 26 10 22 ten Enable time OE A -40°C to 85°C 8 25 8 25 8 25 8 25 8 25 8 25 ns -40°C to 125°C 8 27 8 27 8 27 8 27 8 27 8 27 OE B -40°C to 85°C 20 80 15 46 10 34 10 25 5 23 5 18 -40°C to 125°C 20 86 15 48 10 37 10 27 5 25 5 20 SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay A B -40°C to 85°C 8 41 6 19 4 15 3 10 3 9 2 6.5 ns -40°C to 125°C 8 43 6 21 4 16 3 11 3 10 2 7.5 B A -40°C to 85°C 5 22 5 15 4 12 3 10 3 9 3 8.5 -40°C to 125°C 5 24 5 16 4 13 3 11 3 10 3 9 tdis Disable time OE A -40°C to 85°C 9 19 9 19 9 19 8 19 8 19 8 19 ns -40°C to 125°C 9 20 9 20 9 20 8 20 8 20 8 20 OE B -40°C to 85°C 15 52 15 38 12 32 10 23 10 22 9 18 -40°C to 125°C 15 59 15 41 12 35 10 26 10 23 9 20 ten Enable time OE A -40°C to 85°C 5 20 5 20 5 20 5 20 5 20 5 20 ns -40°C to 125°C 5 22 5 22 5 22 5 22 5 22 5 22 OE B -40°C to 85°C 20 80 15 43 10 34 5 24 5 19 5 16 -40°C to 125°C 20 85 15 46 10 36 5 27 5 21 5 18 www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN74LXCH8T245

6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay A B -40°C to 85°C 8 38 6 15 3 14 3 9.5 2 8 2 6 ns -40°C to 125°C 8 42 6 17 3 15 3 10.5 2 8.5 2 7 B A -40°C to 85°C 5 22 4 13 3 10.5 3 8 2 7.5 2 7 -40°C to 125°C 5 24 4 15 3 11.5 3 8.5 2 8 2 7.5 tdis Disable time OE A -40°C to 85°C 7 15 5 15 5 15 5 15 5 14 5 14 ns -40°C to 125°C 7 16 5 16 5 16 5 16 5 15 5 15 OE B -40°C to 85°C 15 52 12 33 10 31 10 22 10 21 5 16 -40°C to 125°C 15 56 12 37 10 35 10 24 10 23 5 18 ten Enable time OE A -40°C to 85°C 5 15 5 15 5 15 5 15 5 15 5 15 ns -40°C to 125°C 5 16 5 16 5 16 5 16 5 16 5 16 OE B -40°C to 85°C 20 80 15 44 10 33 5 24 5 18 5 15 -40°C to 125°C 20 85 15 48 10 35 5 26 5 20 5 17 SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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6.12 Switching Characteristics: Tsk, TMAX

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCI VCCO Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching 20% of pulse > 0.7*VCCO 20% of pulse < 0.3*VCCO Up Translation 3.0 V – 3.6 V 4.5 V – 5.5 V 200 420 Mbps 1.65 V – 1.95 V 4.5 V – 5.5 V 100 200 Mbps 1.1 V – 1.3 V 4.5 V – 5.5 V 20 40 Mbps 1.65 V – 1.95 V 3.0 V – 3.6 V 100 210 Mbps 1.1 V – 1.3 V 3.0 V – 3.6 V 10 20 Mbps 1.1 V – 1.3 V 1.65 V – 1.95 V 5 10 Mbps Down Translation 4.5 V – 5.5 V 3.0 V – 3.6 V 100 210 Mbps 4.5 V – 5.5 V 1.65 V – 1.95 V 50 75 Mbps 4.5 V – 5.5 V 1.1 V – 1.3 V 15 30 Mbps 3.0 V – 3.6 V 1.65 V – 1.95 V 40 75 Mbps 3.0 V – 3.6 V 1.1 V – 1.3 V 10 20 Mbps 1.65 V – 1.95 V 1.1 V – 1.3 V 5 10 Mbps tsk – Output skew Timing skew between any two switching outputs within the same device Up Translation ns 1.65 V – 1.95 V 4.5 V – 5.5 V 1 1.65 V – 1.95 V 3.0 V – 3.6 V 1 1.1 V – 1.3 V 1.65 V – 1.95 V 2 Down Translation 4.5 V – 5.5 V 1.65 V – 1.95 V 1 3.0 V – 3.6 V 1.65 V – 1.95 V 1 1.65 V – 1.95 V 1.1 V – 1.3 V 2

6.13 Operating Characteristics

TA = 25℃ (1) PARAMETER Test Conditions Supply Voltage (VCCB = VCCA) TYP TYP TYP TYP TYP TYP CpdA (2) A to B: outputs enabled A Port CL = 0, RL = Open f = 10 MHz trise = tfall = 1 ns 1 4 4 4 5 5 pF A to B: outputs disabled 3 3 3 4 4 4 B to A: outputs enabled 22 22 22 23 24 25 B to A: outputs disabled 1 1 1 1 1 2 CpdB (2) A to B: outputs enabled B Port CL = 0, RL = Open f = 10 MHz trise = tfall = 1 ns 22 22 22 23 24 25 pF A to B: outputs disabled 1 1 1 1 1 2 B to A: outputs enabled 1 1 1 1 1 5 B to A: outputs disabled 3 3 3 1 1 1 (1) See the CMOS Power Consumption and Cpd Calculation application report for more information about power dissipation capacitance. (2) C pdA and CpdB are respectively A-Port and B-Port power dissipation capacitances per transceiver. www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN74LXCH8T245

6.14 Typical Characteristics

IOH  Output High Current (mA) V OH  Output High Voltage (V) 0 5 10 15 20 25 30 35 40 45 50 1.5 2.5 3.5 4.5 VCC = 5 V VCC = 3.3 V VCC = 2.5 V Figure 6-1. Typical (TA=25°C) Output High Voltage (VOH) vs Source Current (IOH) IOH  Output High Current (mA) V OH  Output High Voltage (V) 0.4 0.6 0.8 1.2 1.4 1.6 1.8 VCC = 1.8 V VCC = 1.5 V VCC = 1.2 V Figure 6-2. Typical (TA=25°C) Output High Voltage (VOH) vs Source Current (IOH) IOL  Output Low Current (mA) V OL  Output Low Voltage (V) 0 5 10 15 20 25 30 35 40 45 50 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 VCC = 5 V VCC = 3.3 V VCC = 2.5 V Figure 6-3. Typical (TA=25°C) Output High Voltage (VOL) vs Sink Current (IOL) IOL  Output Low Current (mA) V OL  Output Low Voltage (V) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 VCC = 1.8 V VCC = 1.5 V VCC = 1.2 V Figure 6-4. Typical (TA=25°C) Output High Voltage (VOL) vs Sink Current (IOL) VIN  Input Voltage (V) ICC  Supply Current (mA) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 VCC = 5 V VCC = 3.3 V VCC = 2.5 V Figure 6-5. Typical (TA=25°C) Supply Current (ICC) vs Input Voltage (VIN) VIN  Input Voltage (V) ICC  Supply Current (mA) 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 VCC = 1.8 V VCC = 1.5 V VCC = 1.2 V Figure 6-6. Typical (TA=25°C) Supply Current (ICC) vs Input Voltage (VIN) SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

f = 1 MHz
Z O = 50 Ω
Δt/ΔV ≤ 1 ns/V Output Pin Under Test CL (1) RL RL GND Open 2 x VCCO Measurement Point A. C L includes probe and jig capacitance. Figure 7-1. Load Circuit Table 7-1. Load Circuit Conditions Parameter VCCO RL CL S1 VTP tpd Propagation (delay) time 1.1 V – 5.5 V 2 kΩ 15 pF Open N/A ten, tdis Enable time or disable time 1.1 V – 1.6 V 2 kΩ 15 pF 2 × VCCO 0.1 V 1.65 V – 2.7 V 2 kΩ 15 pF 2 × VCCO 0.15 V 3.0 V – 5.5 V 2 kΩ 15 pF 2 × VCCO 0.3 V ten, tdis Enable time or disable time 1.1 V – 1.6 V 2 kΩ 15 pF GND 0.1 V 1.65 V – 2.7 V 2 kΩ 15 pF GND 0.15 V 3.0 V – 5.5 V 2 kΩ 15 pF GND 0.3 V Input A, B VCCI (1) VCCI / 2 0 V Output B, A VOH (2) VOL (2) tpd tpd VCCI / 2 VCCI / 2 V CCI / 2 1. V CCI is the supply pin associated with the input port. 2. V OH and VOL are typical output voltage levels that occur with specified RL, CL, and S1. Figure 7-2. Propagation Delay VCCI (1) 0 V 100 kHz 500 ps/V ± 1 s/V VOH (2) VOL (2) Ensure Monotonic Rising and Falling EdgeOutput B, A Input A, B 1. V CCI is the supply pin associated with the input port. 2. V OH and VOL are typical output voltage levels that occur with specified RL, CL, and S1. Figure 7-3. Input Transition Rise and Fall Rate www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN74LXCH8T245

Output(1) tdis GND VCCA / 2 VCCO (3) VOL (4)VOL + VTP ten VCCO / 2 Output(2) VOH (4) GND VOH - VTP VCCO / 2 OE 1. Output waveform on the condition that input is driven to a valid Logic Low. 2. Output waveform on the condition that input is driven to a valid Logic High. 3. V CCO is the supply pin associated with the output port. 4. V OH and VOL are typical output voltage levels with specified RL, CL, and S1. Figure 7-4. Enable Time And Disable Time SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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8 Detailed Description

8.1 Overview

The SN74LXCH8T245 is an 8-bit translating transceiver that uses two individually configurable power-supply rails. The device is operational with V CCA and VCCB supplies as low as 1.1 V and as high as 5.5 V. Additionally, the device operates with V CCA = VCCB. The A port is designed to track V CCA, and the B port is designed to track VCCB. The SN74LXCH8T245 device is designed for asynchronous communication between data buses and transmits data from the A bus to the B bus or from the B bus to the A bus based on the logic level of the direction-control input (DIR). The output-enable input ( OE) is used to disable the outputs so the buses are effectively isolated. The control pins of the SN74LXCH8T245 (DIR and OE) are referenced to V CCA. The OE pin should be tied to VCCA through a pullup resistor to ensure the high-impedance state of the level shifter I/Os during power up or power down. This device is fully specified for partial-power-down applications using the I off current. The Ioff protection circuitry ensures that no excessive current is drawn from or sourced into an input, output, or I/O while the device is powered down. The V CC isolation and V CC disconnect feature ensures that if either V CC is less than 100 mV or floating with the complementary supply within the recommended operating conditions, both I/O ports are set to the high-impedance state by disabling their outputs and the supply current is maintained. Glitch-free power supply sequencing allows either supply rail to power on or off in any order while providing robust power sequencing performance.

8.2 Functional Block Diagram

Note: Bus-hold circuits are only present for data inputs, not control inputs Bus-Hold Bus-Hold Bus-Hold Bus-Hold Figure 8-1. SN74LXCH8T245 Functional Block Diagram www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: SN74LXCH8T245

8.3 Feature Description

8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings , and the maximum input leakage current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics , which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly will increase dynamic current consumption of the device. See Understanding Schmitt Triggers for additional information regarding Schmitt-trigger inputs.

8.3.1.1 Control Inputs with Integrated Static Pull-Down Resistors

Similar to the data I/O's, floating control inputs can cause high current consumption. This device has integrated weak static pull-downs of 5-M Ω typical on the control inputs (DIR and OE) to help avoid this concern. These pull-downs are always present. For example, if the DIR pin is left floating, then the B port will be configured as an input and the A port will be configured as an output.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.

8.3.3 Partial Power Down (Ioff)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting current backflow into the device. Ioff in the Electrical Characteristics specifies the maximum leakage into or out of any input or output pin on the device.

8.3.4 VCC Isolation and VCC Disconnect

The inputs and outputs for this device enter a high-impedance state when either supply is <100 mV, requiring one supply to connect to the device. Note: the bus-hold circuitry always remains active even when the device is disabled and all outputs are in the high-impedance state. Either supply can be disconnected (floated), while the other supply is still connected and the device will maitain the maximum supply current specified by I CCx(floating), in the Electrical Characteristics. The I/O's will not enter a high-impedance state unless the supply is disconnected after it is driven to <100 mV. I off(float) in the Electrical Characteristics specifies the maximum leakage into or out of any input or output pin on the device. Hi-Z Hi-Z A1 B1 OE VCCBVCCA DIR VCCA VCCB Supply disconnected ICCB maintained Disabled Disabled Ioff(float)Ioff(float) GND Bus-Hold Bus-Hold Figure 8-2. VCC Disconnect Feature SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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8.3.5 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage as long as they remain below the maximum input voltage value specified in the Recommended Operating Conditions.

8.3.6 Glitch-Free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the output erroneously transitions to VCC when it should be held low or vice versa). Glitches of this nature can be misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device configuration of the peripheral, or even a false data initialization by the peripheral.

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in Figure 8-3. CAUTION Voltages beyond the values specified in Section 6.1 table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. GND Level Shifter Input or I/O configured as input VCCA Device -IIK -IOK VCCB I/O configured as output Figure 8-3. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

The V CCA and V CCB pins can be supplied at any voltage from 1.1 V to 5.5 V, making the device suitable for

8.3.9 Supports High-Speed Translation

The SN74LXCH8T245 device can support high data-rate applications. The translated signal data rate can be up to 420 Mbps when the signal is translated from 3.3 V to 5.0 V. www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: SN74LXCH8T245

8.3.10 Bus-Hold Data Inputs

Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low state. After data is sent through a channel, the latch maintains the previous state on the input (if the line is left floating). It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as it may cause undefined inputs to occur which leads to excessive current consumption. Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs application report explains the problems associated with leaving the CMOS inputs floating. These latches remain active at all times, independent of all control signals such as direction control or output enable. The latches also remain active when the device is in the partial power down state, corresponding supply is still present, or when the I/O's are floated. The Bus-Hold Circuit application report has additional details regarding bus-hold inputs. Ax BxLevel Shifter Bus-Hold Bus-Hold Figure 8-4. Schematic Description of Location of Bus-Hold Circuits

8.4 Device Functional Modes

Table 8-1. Function Table(1) CONTROL INPUTS Port Status OPERATION OE DIR A PORT B PORT L L Output (Enabled) Input (Hi-Z) B data to A bus L H Input (Hi-Z) Output (Enabled) A data to B bus H X Input (Hi-Z) Input (Hi-Z) Isolation (1) Input circuits of the data I/Os are always active. SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The SN74LXCH8T245 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The SN74LXCH8T245 device is ideal for use in applications where a push-pull driver is connected to the data I/Os. The maximum data rate can be up to 420 Mbps when the device translates a signal from 3.3 V to 5.0 V.

9.2 Typical Application

1.2 V 5.0 V 0.1 µF 0.1 µF SN74LXC8T245 GND GPIO1 A2GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 Figure 9-1. LED Driver Application

9.2.1 Design Requirements

Use the parameters listed in Table 9-1 for this design example. Table 9-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Input voltage range 1.1 V to 5.5 V Output voltage range 1.1 V to 5.5 V www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: SN74LXCH8T245

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

Input voltage range: – Use the supply voltage of the device that is driving the SN74LXCH8T245 device to determine the input voltage range. The value must exceed the high-level input voltage (VIH) of the input port for a valid logic-high. The value must be less than the low-level input voltage (VIL) of the input port for a valid logic low.
Output voltage range: – Use the device's supply voltage that the SN74LXCH8T245 device is driving to determine the output voltage range.

9.2.3 Application Curve

Figure 9-2. Up Translation at 2.5 MHz (1.2 V to 5 V) SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing without any supply sequencing requirements such as ramp order or ramp rate. Section 8.3.6 describes how this device was designed with various power supply sequencing methods in mind to help prevent unintended triggering of downstream devices.

11 Layout

11.1 Layout Guidelines

Following common printed-circuit board layout guidelines are recommended to ensure reliability of the device, which follows:

Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF capacitors in parallel as bypass capacitors.
The high drive capability of this device creates fast edges into light loads; so routing and load conditions should be considered to prevent ringing.

11.2 Layout Example

B G Legend SN74LXCH8T245RHLR PAD DIR GND GND VCCA VCCB VCCB GND OE G G G G To LED Array From Controller B B A A 0.1µF 020 1 0.1µF 020 1 G Figure 11-1. Layout Example www.ti.com SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: SN74LXCH8T245

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
Texas Instruments, Semiconductor and IC Package Thermal Metrics appliction report
Texas Instruments, System Considerations for Using Bus-Hold Curcuits to Avoid Floating Inputs application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN74LXCH8T245 SCES917B – DECEMBER 2019 – REVISED MARCH 2021 www.ti.com

Product Folder Links: SN74LXCH8T245

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 74LXCH8T245RHLRG4 Active Production VQFN (RHL) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LX8T245H 74LXCH8T245RHLRG4.A Active Production VQFN (RHL) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LX8T245H SN74LXCH8T245PWR Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LXH8T245 SN74LXCH8T245PWR.A Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LXH8T245 SN74LXCH8T245PWRG4 Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LXH8T245 SN74LXCH8T245PWRG4.A Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LXH8T245 SN74LXCH8T245RHLR Active Production VQFN (RHL) | 24 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LX8T245H SN74LXCH8T245RHLR.A Active Production VQFN (RHL) | 24 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LX8T245H (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 7-Oct-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74LXCH8T245RHLRG4 VQFN RHL 24 3000 367.0 367.0 35.0 SN74LXCH8T245RHLR VQFN RHL 24 3000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 22X 0.65 7.15 24X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 7.9 7.7 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 12 13 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 12 13

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225250/B 12/2024 www.ti.com VQFN - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD RHL0024A AB PIN 1 INDEX AREA 3.6 3.4 5.6 5.4 0.08 C SEATING PLANE C1 MAX (0.1) TYP 0.05 0.00 0.05 C SYMM SYMM 1PIN 1 ID (OPTIONAL) 2.05±0.1 4.05±0.1 2X (0.55) 4.5 18X 0.5 12 13 2X 1.5 4X (0.2) 24X 0.30 0.18 24X 0.5 0.3

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225250/B 12/2024 www.ti.com VQFN - 1 mm max heightRHL0024A PLASTIC QUAD FLATPACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 18X SYMM SYMM 2X (1.5) 6X (0.67) (0.775) (5.3) (3.3) 24X (0.6) 24X (0.24) 18X (0.5) (4.05) (2.05) (R0.05) TYP 2X (1.105) 2X (0.4) SOLDER MASK OPENING METAL UNDER SOLDER MASK 4X (0.2) 2X (0.55) (Ø 0.2) VIA TYP 1 24 12 13 4.6 4.4

0.07 MAX

(PREFERRED) METAL SOLDER MASK OPENING EXPOSED METAL

0.07 MIN

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225250/B 12/2024 www.ti.com VQFN - 1 mm max heightRHL0024A PLASTIC QUAD FLATPACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED COVERAGE BY AREA SCALE: 18X SYMM SYMM 2X (1.5) (1.34) 6X (0.56) (5.3) (3.3) 24X (0.6) 24X (0.24) 18X (0.5) (2.05) (R0.05) TYP 2X (0.84) METAL TYP 4X (0.2) 2X (0.55) 1 24 12 13 4.6 4.4 SOLDER MASK EDGE TYP

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