74LV132BQ | DigiCamel IC Datasheet

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74LV132 NXP | Alldatasheet

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Technical content

General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply deﬁned, jitter-free output signals. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage V T+ and the negative voltage VT− is deﬁned as the input hysteresis voltage VH . 2. Features ■ Wide operating voltage: 1.0 V to 5.5 V ■ Optimized for low voltage applications: 1.0 V to 3.6 V ■ Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V ■ Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25°C ■ Typical HIGH-level output voltage (VOH ) undershoot: > 2 V at VCC = 3.3 V and Tamb =2 5°C ■ ESD protection: ◆ HBM JESD22-A114E exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V ■ Multiple package options ■ Speciﬁed from−40 °Ct o+ 8 5°C and from−40 °C to +125°C 3. Applications ■ Wave and pulse shapers for highly noisy environments ■ Astable multivibrators ■ Monostable multivibrators 74LV132 Quad 2-input NAND Schmitt trigger Rev. 04 — 12 November 2007 Product data sheet

6.1 Pinning

6.2 Pin description

used as a supply pin or input. Table 2. Pin description

74LV132_4 © NXP B.V. 2007. All rights reserved. [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70°C. [3] Ptot derates linearly with 8 mW/K above 70°C. [4] Ptot derates linearly with 5.5 mW/K above 60°C. [5] Ptot derates linearly with 4.5 mW/K above 60°C. Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Recommended operating conditions

VCC = 1.0 V (with input levels GND or VCC ). [1] Typical values are measured at Tamb = 25°C. Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V).

74LV132_4 © NXP B.V. 2007. All rights reserved. [1] All typical values are measured at Tamb =2 5°C. [2] tpd is the same as tPLH and tPHL . [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [4] C PD is used to determine the dynamic power dissipation (PD inµW). L × VCC 2 × fo) = sum of the outputs. Table 7. Dynamic characteristics GND = 0 V; For test circuit seeFigure7. Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load.

Transfer characteristics

Table 8. Measurement points Test data is given inTable9. T = Termination resistance should be equal to output impedance Zo of the pulse generator. C L = Load capacitance including jig and probe capacitance. Table 9. Test data Table 10. Transfer characteristics GND = 0 V; For test circuit seeFigure7.

Waveforms transfer characteristics

Table 10. Transfer characteristics …continued GND = 0 V; For test circuit seeFigure7. VT+ and VT− limits at 70 % and 20 %.

74LV132_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 12 November 2007 9 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger VCC = 1.2 V. V CC = 2.0 V. Fig 10. Typical 74LV132 transfer characteristics Fig 11. Typical 74LV132 transfer characteristics VI (V) 0 1.2 0.90.3 0.6 001aaa659 ICC (µA) VI (V) 02 1.60.8 1.20.4 001aaa660 100 ICC (µA) VCC = 3.0 V. Fig 12. Typical 74LV132 transfer characteristics VI (V) 03 2.41.2 1.80.6 001aaa661 100 200 300 I CC (µA)

74LV132_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 12 November 2007 10 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger 15. Package outline Fig 13. Package outline SOT27-1 (DIP14) UNIT A max. 1 2 (1) (1)b1 cD (1)ZEe M HL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT27-1 99-12-27 03-02-13 A min. A max. b max.wM Ee1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 7.80 10.0 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.31 0.39 050G04 MO-001 SC-501-14 M H c (e )1 M E A L seating plane w M e D A 2 Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

74LV132_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 12 November 2007 11 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger Fig 14. Package outline SOT108-1 (SO14) UNIT A max. A 1 A 2 A 3 bp cD (1) E (1) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT108-1 X w M q AA 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A y 076E06 MS-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.0410.244 0.228 0.028 0.024 0.028 0.0120.01 0.25 0.01 0.0040.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74LV132_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 12 November 2007 12 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger Fig 15. Package outline SOT337-1 (SSOP14) UNIT A 1 A 2 A 3 bp cD (1) E (1) eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 7.6 1.03 0.63 0.9 0.7 1.4 0.9 o o0.13 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT337-1 99-12-27 03-02-19 (1) w M bp D H E E Z e c v M A X A y 1 7 14 8 q AA 1 A 2 Lp Q detail X L (A )3 MO-150 pin 1 index 0 2.5 5 mm scale SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 A max.

74LV132_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 12 November 2007 13 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger Fig 16. Package outline SOT402-1 (TSSOP14) UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT402-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 14 8 q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XA y 0 2.5 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 A max. 1.1 pin 1 index

74LV132_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 12 November 2007 14 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger Fig 17. Package outline SOT762-1 (DHVQFN14) terminal 1 index area 0.51 A 1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.1 2.9 D h 1.65 1.35 2.6 2.4 1.15 0.85 20.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT762-1 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm A (1) max. A c detail X yy1 Ce L Eh D h e b 13 9 X D E C B A 02-10-17 03-01-27 terminal 1 index area AC C Bv M w M E (1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D (1)

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Section4: DHVQFN14 package added.
Section9: derating values added for DHVQFN14 package.
Section15: outline drawing added for DHVQFN14 package. 74LV132_3 20040415 Product speciﬁcation - 74LV132_2 74LV132_2 19980428 Product speciﬁcation - 74LV132_1 74LV132_1 19970204 Product speciﬁcation - -

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit:http://www.nxp.com For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 November 2007 Document identifier: 74LV132_4 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 20. Contents

Product Information

74LV132BQ specifications and overview.

Summary

Quad 2-input NAND Schmitt trigger Rev. 04-12 November 2007

Description

Quad 2-input NAND Schmitt trigger Rev. 04-12 November 2007

Source title 74LV132BQ Datasheet(PDF) - NXP Semiconductors

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