74LV123A | DigiCamel IC Datasheet

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/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00682-V to 5.5-V VCC Operation /C0068Max tpd of 11 ns at 5 V /C0068Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C /C0068Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C /C0068Support Mixed-Mode Voltage Operation on All Ports /C0068Schmitt-Trigger Circuitry on A, B, and CLR Inputs for Slow Input Transition Rates /C0068Edge Triggered From Active-High or Active-Low Gated Logic Inputs /C0068Ioff Supports Partial-Power-Down Mode Operation /C0068Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle /C0068Overriding Clear Terminates Output Pulse /C0068Glitch-Free Power-Up Reset on Outputs /C0068Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II /C0068ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54LV123A ...J O R W PACKAGE SN74LV123A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) SN54LV123A . . . FK PACKAGE (TOP VIEW) 1CLR 2C ext 2R ext/Cext GND VCC 1R ext/Cext 1C ext 2CLR 321 2 0 1 9 91 01 11 21 3 1C ext NC 2CL R 1CLR NC 2C ext NC V GND NC CC NC − No internal connection ext/Cext ext/Cext SN74LV123A . . . RGY PACKAGE (TOP VIEW) 11 6 1R ext/Cext 1C ext 2CLR 1CLR 2C ext 2R ext/Cext 2A V GND CC description/ordering information The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation. These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC . To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC . The output pulse duration also can be reduced by taking CLR low. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing. Copyright  2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0085/C0078/C0076/C0069/C0083/C0083 /C0079/C0084/C0072/C0069/C0082/C0087/C0073/C0083/C0069 /C0078/C0079/C0084/C0069/C0068 /C0116/C0104/C0105/C0115 /C0100/C0111/C0099/C0117/C0109/C0101/C0110/C0116 /C0099/C0111/C0110/C0116/C0097/C0105/C0110/C0115 /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued) During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. Pin assignments for these devices are identical to those of the ’AHC123A and ’AHCT123A devices for interchangeability, when allowed.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING QFN − RGY Reel of 1000 SN74LV123ARGYR LV123A SOIC − D Tube of 40 SN74LV123AD LV123ASOIC − D Reel of 2500 SN74LV123ADR LV123A SOP − NS Reel of 2000 SN74LV123ANSR 74LV123A −40°C to 85°C SSOP − DB Reel of 2000 SN74LV123ADBR LV123A−40 C to 85C Tube of 90 SN74LV123APW TSSOP − PW Reel of 2000 SN74LV123APWR LV123ATSSOP − PW Reel of 250 SN74LV123APWT LV123A TVSOP − DGV Reel of 2000 SN74LV123ADGVR LV123A CDIP − J Tube of 25 SNJ54LV123AJ SNJ54LV123AJ −55°C to 125°C CFP − W Tube of 150 SNJ54LV123AW SNJ54LV123AW−55 C to 125C LCCC − FK Tube of 55 SNJ54LV123AFK SNJ54LV123AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each multivibrator) INPUTS OUTPUTS CLR A B Q Q L X X L H X HX L ‡ H ‡ X XL L ‡ H ‡ H L ↑ H ↓ H ↑ L H ‡ These outputs are based on the assumption that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the setup.

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram, each multivibrator (positive logic) CLR C ext R ext/Cext R B A Q Q input/output timing diagram A B CLR Q Q tw tw tw + trr trr R ext/Cext

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage range applied to any output in the high-impedance † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5.

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 5) SN54LV123A SN74LV123A UNITMIN MAX MIN MAX UNIT VCC Supply voltage 2 5.5 2 5.5 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VVIH High-level input voltage VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 V VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VVIL Low-level input voltage VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 V VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3 VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V VCC = 2 V −50 −50 µA IOH High-level output current VCC = 2.3 V to 2.7 V −2 −2 IOH High-level output current VCC = 3 V to 3.6 V −6 −6 mA VCC = 4.5 V to 5.5 V −12 −12 mA VCC = 2 V 50 50 µA IOL Low-level output current VCC = 2.3 V to 2.7 V 2 2 IOL Low-level output current VCC = 3 V to 3.6 V 6 6 mA VCC = 4.5 V to 5.5 V 12 12 mA R ext External timing resistance VCC = 2 V 5k 5k ΩR ext External timing resistance VCC ≥ 3 V 1k 1k Ω C ext External timing capacitance No restriction No restriction pF ∆t/∆VCC Power-up ramp rate 1 1 ms/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 5: Unused R ext/Cext terminals should be left unconnected. All remaining unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. /C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC SN54LV123A SN74LV123A UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN TYP MAX UNIT IOH = −50 µA 2 V to 5.5 VVCC −0.1 VCC −0.1 VOH IOH = −2 mA 2.3 V 2 2 VVOH IOH = −6 mA 3 V 2.48 2.48 V IOH = −12 mA 4.5 V 3.8 3.8 IOL = 50 µA 2 V to 5.5 V 0.1 0.1 VOL IOL = 2 mA 2.3 V 0.4 0.4 VVOL IOL = 6 mA 3 V 0.44 0.44 V IOL = 12 mA 4.5 V 0.55 0.55 R ext/Cext† VI = 5.5 V or GND 2 V to 5.5 V ±2.5 ±2.5 II A, B, and CLRVI = 5.5 V or GND 0 ±1 ±1 µAII A, B, and CLRVI = 5.5 V or GND 0 to 5.5 V ±1 ±1 µA ICC Quiescent VI = VCC or GND, IO = 0 5.5 V 20 20 µA

2.3 V 220 220

Active state VI = VCC or GND, 3 V 280 280 AICC Active state (per circuit) VI = VCC or GND, R ext/Cext = 0.5 VCC 4.5 V 650 650 µA(per circuit) R ext/Cext = 0.5 VCC

5.5 V 975 975

Ioff VI or VO = 0 to 5.5 V 0 5 µA C i VI = VCC or GND 3.3 V 1.9 1.9 pFC i VI = VCC or GND 5 V 1.9 1.9 pF † This test is performed with the terminal in the off-state condition. timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS TA = 25°C SN54LV123A SN74LV123A UNITTEST CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT tw Pulse CLR 6 6.5 6.5 nstw Pulse duration A or B trigger 6 6.5 6.5 ns trr Pulse retrigger time R ext = 1 kΩ C ext = 100 pF ‡ 94 ‡ ‡ ns trr Pulse retrigger time R ext = 1 kΩ C ext = 0.01 /C0109F ‡ 2 ‡ ‡ /C0109s ‡ See retriggering data in the application information section. timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS TA = 25°C SN54LV123A SN74LV123A UNITTEST CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT tw Pulse CLR 5 5 5 nstw Pulse duration A or B trigger 5 5 5 ns trr Pulse retrigger time R ext = 1 kΩ C ext = 100 pF ‡ 76 ‡ ‡ ns trr Pulse retrigger time R ext = 1 kΩ C ext = 0.01 /C0109F ‡ 1.8 ‡ ‡ /C0109s ‡ See retriggering data in the application information section. /C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS TA = 25°C SN54LV123A SN74LV123A UNITTEST CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT tw Pulse CLR 5 5 5 nstw Pulse duration A or B trigger 5 5 5 ns trr Pulse retrigger time R ext = 1 kΩ C ext = 100 pF † 59 † † ns trr Pulse retrigger time R ext = 1 kΩ C ext = 0.01 /C0109F † 1.5 † † /C0109s † See retriggering data in the application information section. switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TEST TA = 25°C SN54LV123A SN74LV123A UNITPARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT A or B Q or Q 14.5* 31.4* 1* 37* 1 37 tpd CLR Q or Q C L = 15 pF 13* 25* 1* 29.5* 1 29.5 nstpd CLR trigger Q or Q C L = 15 pF ns A or B Q or Q 16.6 36 1 42 1 42 tpd CLR Q or Q C L = 50 pF 14.7 32.8 1 34.5 1 34.5 nstpd CLR trigger Q or Q C L = 50 pF 17.4 38 1 44 1 44 ns C L = 50 pF, C ext = 28 pF, R ext = 2 kΩ 197 260 320 320 ns tw ‡ Q or Q C L = 50 pF, C ext = 0.01 µF, R ext = 10 kΩ 90 100 110 90 110 90 110 /C0109s C L = 50 pF, C ext = 0.1 µF, R ext = 10 kΩ ∆tw § C L = 50 pF ±1 % * On products compliant to MIL-PRF-38535, this parameter is not production tested. ‡ tw = Duration of pulse at Q and Q outputs § ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package /C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TEST TA = 25°C SN54LV123A SN74LV123A UNITPARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT A or B Q or Q 10.2* 20.6* 1* 24* 1 24 tpd CLR Q or Q C L = 15 pF 9.3* 15.8* 1* 18.5* 1 18.5 nstpd CLR trigger Q or Q C L = 15 pF ns A or B Q or Q 11.8 24.1 1 27.5 1 27.5 tpd CLR Q or Q C L = 50 pF 10.5 19.3 1 22 1 22 nstpd CLR trigger Q or Q C L = 50 pF 12.3 25.9 1 29.5 1 29.5 ns C L = 50 pF, C ext = 28 pF, R ext = 2 kΩ 182 240 300 300 ns tw † Q or Q C L = 50 pF, C ext = 0.01 µF, R ext = 10 kΩ 90 100 110 90 110 90 110 /C0109s C L = 50 pF, C ext = 0.1 µF, R ext = 10 kΩ ∆tw ‡ C L = 50 pF ±1 % * On products compliant to MIL-PRF-38535, this parameter is not production tested. † tw = Duration of pulse at Q and Q outputs ‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TEST TA = 25°C SN54LV123A SN74LV123A UNITPARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT A or B Q or Q 7.1* 12* 1* 14* 1 14 tpd CLR Q or Q C L = 15 pF 6.5* 9.4* 1* 11* 1 11 nstpd CLR trigger Q or Q C L = 15 pF ns A or B Q or Q 8.3 14 1 16 1 16 tpd CLR Q or Q C L = 50 pF 7.4 11.4 1 13 1 13 nstpd CLR trigger Q or Q C L = 50 pF 8.7 14.9 1 17 1 17 ns C L = 50 pF, C ext = 28 pF, R ext = 2 kΩ 167 200 240 240 ns tw † Q or Q C L = 50 pF, C ext = 0.01 µF, R ext = 10 kΩ 90 100 110 90 110 90 110 /C0109s C L = 50 pF, C ext = 0.1 µF, R ext = 10 kΩ ∆tw ‡ ±1 % * On products compliant to MIL-PRF-38535, this parameter is not production tested. † tw = Duration of pulse at Q and Q outputs ‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package /C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046

3.3 V 44

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr /C00433 ns, tf /C0043 3 ns. C. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION † Figure 2 OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE 1.00E+07 tw − Output Pulse Duration − ns 1.00E+06 1.00E+05 1.00E+04 1.00E+03 1.00E+02 C T − External Timing Capacitance − pF 101 102 103 104 105 VCC = 3 V TA = 25°C R T = 1 MΩ R T = 100 kΩ R T = 10 kΩ R T = 1 kΩ Figure 3 OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE 1.00E+07 tw − Output Pulse Duration − ns 1.00E+06 1.00E+05 1.00E+04 1.00E+03 1.00E+02 C T − External Timing Capacitance − pF 101 102 103 104 105 R T = 1 MΩ R T = 100 kΩ R T = 10 kΩ R T = 1 kΩ VCC = 4.5 V TA = 25°C † Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION † Figure 6 MINIMUM TRIGGER TIME vs VCC CHARACTERISTICS R T = 1 kΩ TA = 25°C 10.00 1.00 0.10 0.01 12 3 456 C T = 0.01 µF C T = 1000 pF C T = 100 pF VCC − Supply Voltage − V Minimum Retrigger Time − µsrr − t Figure 7 1.20 1.15 1.10 1.05 1.00 0.95 0.90 R T = 10 kΩ TA = 25°C tW = K × C T × R T VCC − Supply Voltage − V OUTPUT PULSE-DURATION CONSTANT vs SUPPLY VOLTAGE Output Pulse-Duration Constant − K C T = 1000 pF C T = 0.01 µF C T = 0.1 µF Figure 8 0.00001 0.0001 0.001 TA = 25°C VCC = 5 V For Capacitor Values of 0.001 µF or Greater, K = 1.0 (K is Independent of R) Multiplier Factor − K EXTERNAL CAPACITANCE vs MULTIPLIER FACTOR CT − External Capacitor Value − µF Figure 9 tw − Output Pulse Duration Relative Frequency of Occurance DISTRIBUTION OF UNITS vs OUTPUT PULSE DURATION Mean = 856 ns Median = 856 ns Std. Dev. = 3.5 ns VCC = 5 V TA = 25°C C T = 50 pF R T = 10 k/C0087 −3 Std. Dev. +3 Std. Dev. Median 99% of Data Units † Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep the wiring between the external components and Cext and Rext/Cext terminals as short as possible. power-down considerations Large values of Cext can cause problems when powering down the ’LV123A devices because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor can discharge from V CC through the protection diodes at pin 2 or pin 14. Current through the input protection diodes must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than t = VCC × Cext/30 mA. For example, if VCC = 5 V and Cext = 15 pF, the VCC supply must turn off no faster than t = (5 V) × (15 pF)/30 mA = 2.5 ns. Usually, this is not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero occurs, the ’LV123A devices can sustain damage. To avoid this possibility, use external clamping diodes. output pulse duration The output pulse duration, tw, is determined primarily by the values of the external capacitance (CT) and timing resistance (RT). The timing components are connected as shown in Figure 10. VCC R T C T To Rext/Cext Terminal To Cext Terminal Figure 10. Timing-Component Connections

/C0083/C0078/C0053/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0044 /C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS393O − APRIL 1998 − REVISED OCTOBER 2005

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The minimum input retriggering time (tMIR ) is the minimum time required after the initial signal before retriggering the input. After tMIR , the device retriggers the output. Experimentally, it also can be shown that to retrigger the output pulse, the two adjacent input signals should be tMIR apart, where tMIR = 0.30 × tw. The retrigger pulse duration is calculated as shown in Figure 11. tMIR tRTtPLH tw Input Output tRT = tw + tPLH = (K × RT × CT) + tPLH Where: tMIR = Minimum Input Retriggering Time tPLH = Propagation Delay tRT = Retrigger Time tw = Output Pulse Duration Before Retriggering Figure 11. Retrigger Pulse Duration approximately 15 ns to ensure a retriggered output (see Figure 12). Figure 12. Input/Output Requirements

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74LV123AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ADBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ADBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV123ARGYR ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LV123ARGYRG4 ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 2

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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Product Information

74LV123A specifications and overview.

Summary

DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

Description

DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

Source title 74LV123A Datasheet(PDF) - Texas Instruments

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