74LV10 PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 74LV10 Triple 3-input NAND gate Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook
1998 Apr 20
Philips Semiconductors Product specification 74LV10Triple 3-input NAND gate
21998 Apr 20 853–1919 19256
FEATURES
- Optimized for Low Voltage applications: 1.0 to 3.6 V
- Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
- Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C.
- Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C.
- Output capability: standard
- ICC category: SSI
DESCRIPTION
The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL /tPLH Propagation delay nA, nB, nC to nY C L = 15 pF; VCC = 3.3 V 9 ns C I Input capacitance 3.5 pF C PD Power dissipation capacitance per gateSee Notes 1 and 2 12 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC 2 × fi (CL VCC 2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC 2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL –40°C to +125°C 74LV10 N 74LV10 N SOT27-1 14-Pin Plastic SO –40°C to +125°C 74LV10 D 74LV10 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +125°C 74LV10 DB 74LV10 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +125°C 74LV10 PW 74LV10PW DH SOT402-1 PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1, 3, 9 1A – 3A Data inputs 2, 4, 10 1B – 3B Data inputs
7 GND Ground (0 V)
12, 6, 8 1Y – 3Y Data outputs 13, 5, 11 1C – 3C Data inputs
14 VCC Positive supply voltage
NOTES: H = HIGH voltage level L = LOW voltage level
Philips Semiconductors Product specification 74LV10Triple 3-input NAND gate
1998 Apr 20 3
LOGIC SYMBOL (IEEE/IEC) SV00418 2 12 4 6 LOGIC SYMBOL 1B2 2B4 3B10 SV00417 121Y LOGIC DIAGRAM (ONE GATE) SV00419 A B C Y RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT VCC DC supply voltage See Note1 1.0 3.3 3.6 V VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V Tamb Operating ambient temperature range in free airSee DC and AC characteristics –40 –40 +85 +125 °C tr, tf Input rise and fall times VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V 500 200 100 ns/V NOTE:
Philips Semiconductors Product specification 74LV10Triple 3-input NAND gate
1998 Apr 20 4
ABSOLUTE MAXIMUM RATINGS 1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +4.6 V /C0034IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA /C0034IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA /C0034IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 mA /C0034IGND , /C0034ICC DC V CC or GND current for types with – standard outputs 50 mA Tstg Storage temperature range –65 to +150 °C PTOT Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS -40°C to +85°C -40°C to +125°C UNIT MIN TYP 1 MAX MIN MAX HIGH l l I t VCC = 1.2 V 0.9 0.9 VIH HIGH level Input voltage VCC = 2.0 V 1.4 1.4 Vvoltage VCC = 2.7 to 3.6 V 2.0 2.0 LOW l l I t VCC = 1.2 V 0.3 0.3 VIL LOW level Input voltage VCC = 2.0 V 0.6 0.6 Vvoltage VCC = 2.7 to 3.6 V 0.8 0.8 VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA 1.2 VO HIGH level output VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VVOH voltage; all outputsVCC = 2.7 V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 V VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VOH HIGH level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 V VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 0 VO LOW level output VCC = 2.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VVOL voltage; all outputsVCC = 2.7 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 V VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VOL LOW level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 V II Input leakage current VCC = 3.6 V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; SSI VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 40 µA
1998 Apr 20 5
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
- All typical values are measured at Tamb = 25°C.
- Unless otherwise stated, all typical values are measured at Tamb = 25°C.
- Typical values are measured at VCC = 3.3 V.
Figure 1. Input (nA, nB, nC) to output (nY) propagation delays. R T = Termination resistance should be equal to ZOUT of pulse generators. Figure 2. Load circuitry for switching times.
Philips Semiconductors Product specification 74LV10Triple 3-input NAND gate
1998 Apr 20 6
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
Philips Semiconductors Product specification 74LV10Triple 3-input NAND gate
1998 Apr 20 7
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Philips Semiconductors Product specification 74LV10Triple 3-input NAND gate
1998 Apr 20 8
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
Philips Semiconductors Product specification 74LV10Triple 3-input NAND gate
1998 Apr 20 9
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
Philips Semiconductors Product specification 74LV10Triple 3-input NAND gate
1998 Apr 20 10
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: 05-96 Document order number: 9397-750-04407 /C0109 /C0110 /C0114