7496 ETC | Alldatasheet
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Signetics 7496, 1S96 Shift Registers 5-Bit Shift Register Product Specification Logic Products FEATURES . TYPE TYPICAL PROPAGATION TYPICAL SUPPLY CURRENT © 5-bit parallel-to-serial or serial-to- DELAY (TOTAL) fevnchronous on ee # Asynchronous ones transfer semeerone © Buffered positive-triggered clock © Buttered active LOW Clear ORDERING CODE (Master Reset) COMMERCIAL RANGE Voc =5V #5%; Ta=0°C to +70°C DESCRIPTION a The '96 is a 5-bit shift register with both yore; serial and parallel (ones transfer) data For information regarding devices processed to Military Specifications, see the Signetics Military Products entry. Since the '96 has the output of Data Manual each stage available as well as a D-type seta! nat and ones transfor inputs on INPUT AND OUTPUT LOADING AND FAN-OUT TABLE cecuingstemeunasnsthcwat (png | esneron [| | to-parallel, serial-to-serial and some par- alle-o-serial data operations [ Preset enabie | imps | sat Tes | ‘The '96 is five master/slave tip-ops | Aemer | mous | tt Ts flops change state on the LOW-to-HIGH Nore: transition of the clock. The Serial (S) A 74 unitloac (ui understood o be 40uA ly and —1.6MA ha, and 74LS unit oad (LSU) 6 Z0UA and input is edge-triggered and must be -04™A h. stable only one setup time before the LOW-to-HIGH clock transition. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) e2seer ce GY [ig 1 ‘SRa5] eranet a0] fo, por reser» [7] Fa og vA ec Oe ETS Fy reser © [2] Fra oc o—s Vee GF] [7a] ano u is 6 1—pe z reser 0 [5] Fill ap pneser € [7] Fao —d an 3 1 wun nw >-—]# Veo =P 5 Ship =P 2 December 4, 1985 5-163 859.0577 81502
allowing them to be independently set HIGH. IK lk IT I if inputs will set the associated flipflops HIGH. Figure 1. Typical Master Reset, Shift, Proset, And Shift Sequences
Signetics Logic Products. Product Specification Shift Registers 7496, 1S96 eee ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature range unless otherwise noted.) ee NT RECOMMENDED OPERATING CONDITIONS a [a How maveiae eo Te | | Se [ce roi any erate oe [To Mati! capa omen Pf a ee [Nig tei odo cwes Pe Pe [oh oowing feos enpeaie PT Pe] | DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) tear CONDITIONS* a ee sere Cee edd Vox LoWiovel ouput votage | Vou [in-max ——| oz [ow | | ozs | os | v | ve=max [insaracas | | | | [oas| o« | v | [iat camp we [veer miei || sf fe [wesw |] fe fo eee one Ce [ome wpa] [fff on [ma | Peoew Pee er sotto wu con | Vege Foowrneae| fw FPP Vie 27V [ween eT tte [rere [fpf [|e fm | We tomo oa Meera W240 oper eps [f= [08 [mn | ee [iss Spy covet tod [Voor Pe Lm [me | Perse wn os Kw poe an td vt pig sn ep
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Signetics Logic Products Product Specification eee Pr duCt Specification Shift Registers 7496, LS96 oe eSSSSSSSSSSSSSSSSSssssse AC ELECTRICAL CHARACTERISTICS 1, = 25°C, Voc = 5.0V Pom as | TEST CONDITIONS [as Masnick easy Wawom tf vo [tas fe] pees me ey | te, Clock to output Pre ion delay te Atego wame | wens | Ts | [= | = | jo ieee [wens [Os [fats | NOTE: Pr industry convention, fax 1s the worst case value of the maximum device operating frequency with no constraints on ts, pulse width or duy cycle. AC SET-UP REQUIREMENTS 1, = 25°C, Voc = 5.0V Free | rare Fo [isk ple wats COW wae es a] [tH pee we, tow Wanton feo [a0] [ttl Proto eet eae pave wah HGH Wawoma [wo [ | 0} | [4 soup ines Pwr a | af | Se AC WAVEFORMS hax. PEPe YM 7 \\ vu f}-—w— oP ua Vu vu a L. tw wm vw va teat ‘mol ° Oe Youn tee ewes 0, Vu M Waveform 1. Clock, To Output Waveform 2. Parallel Load And Parallel Data To Output Delays And Clock Pulse Width Delays And Master Reset To Output Delay th Fetgt tn=0 tn=0 cP vu VM a A For all waveforms, Vu = 1.5V for 74 and 74S; Vy = 1. for 74LS. The shaded areas inccate when the input is peritied to change tor presctabe ouput perormance. ‘The number of Clock Pulses requied Betweon the Inui aed oe. measUremonts can be determined Yom te approseale Tah Tab. Waveform 3. Data Set-up And Hold Time December 4, 1985 5-166
Signetics Logic Products Product Specification series ee mons i Staten Shift Registers 7496, S96 Summer TEST CIRCUITS AND WAVEFORMS 90% w 90% amp) Yee veo negative | kY™ vu; 7" PULSE 10% 10%; w ~ Ue ae S110 sm sum ¥ tTLtte ATHLIt- I I 9 cr “en spe s+ F = PULSE Vie vw roms 10" tw 10% ov Test Circuit For 74 Totem-Pole Outputs Input Pulse Definition DENTON ccumurenercs wel pumy | _BME POSE neaunEWOR | - to Voc; see ue.) FAMILY SCI Se a ep soos [nae | ae wi [| eel far = Terminaton rosistance should be equal 10 Zour [74 | sov | iwriz |" soons | 7s | 7ne_| i = Diodes are NOTE. 1N06, oF equivalent. [ras | sov [7 imrtz | s00ns | 16ne | ens | 5 trun trae Values should be less than or equal to the table nom [soy [wre [s00ne [ans [ns | December 4, 1985 5-167