7495A ETC1 | Alldatasheet

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__ S@LS/74LS95B ot be 4-BIT RIGHT/LEFT SHIFT REGISTER > [z] Fi3] 0 GB) men ef fia] Oz [5] 110] Os ve [5] og ano [7] Oba DESCRIPTION — The '95 is a 4-bit shift register with serial and parallel syn- chronous operating modes. The serial shift right and paraile! load are acti- vated by separate clock inputs which are selected by a mode control input. The data is transferred from the serial or parallel D inputs to the Q outputs synchronous with the HIGH-to-L OW transition of theappropriateciock input. | LOGIC SYMBOL ® SYNCHRONOUS, EXPANDABLE SHIFT RIGHT ® SYNCHRONOUS SHIFT LEFT CAPABILITY ® SYNCHRONOUS PARALLEL LOAD 623668 ® SEPARATE SHIFT AND LOAD CLOCK INPUTS PE RP Py Pe PS ORDERING CODE: See Section 9 ocr: s—ojcr, COMMERCIAL GRADE MILITARY GRADE 1 Ds PKGS Voc = +5.0 V +5%, Veo = +5.0 V 10%, Oo 0) 2 Ta =0°C to +70°C Ta = -55°C to +125°C Plastic m3 12 «6 eri a | 7495ADC, 74LS95BDC |5495ADM, 54LS95BDM | ea | Veo = Pin 14 GND = Pin7 Fietoak a | 7495AFC, 74LS95BFC | 5495AFM, 54LS958FM a | INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions 54/74 (U.L.) 54/T4LS (U.L.) PIN NAMES DESCRIPTION HIGH/LOW HIGH/LOW cP; Serial Clock Input (Active Falling Edge) 1.0/1.0 0.8/0.25 CPe Parallel Clock Input (Active Falling Edge) 1.0/1.0 0.5/0.25 Ds Serial Data Input 1.0/1.0 0.5/0,.25 Po — Ps Parallel Data inputs 1.0/1.0 0.5/0.25 PE Parailel Enable Input (Active HiGH) 2.0/2.0 1.0/0.5 Qo — Qs Parallel Outputs 20/10 10/5.0 (2.5) 4-126

FUNCTIONAL DESCRIPTION — The '95 is a 4-bit shift register with serial and parallel synchronous operating ‘modes. It has a Serial (Ds) and four Parallel (Pp — Ps) Data inputs and four Parallel Data outputs (Qo — Q3). The serial or parallel mode of operation is controlled by a Parallel Enable input (PE) and two Clock inputs, CP; and Pe. The serial (right-shitt) or parallel data transfers occur synchronous with the HIGH-to-L OW transition of the selected clock input. When PE is HIGH, CP2 is enabled. A HIGH-to-L OW transition on enabled GP2 transfers parallel data from the Po — Ps inputs to the Qo — Qs outputs. When PE is LOW, GP; isenabled, AHIGH-to-L OW transition on enabled CP; transfers the data from Serial input (Ds) to Qo and shifts the data in Qo to Q1, Q1 to Qz, and Qe to Ga respectively (right-shift). A left-shift is accomplished by externally connecting Qa to Pz, Qe to P1, and Qi to Po, and operating the ‘95 in the parallel mode (PE = HIGH). For normal operation, PE should only change states when both Clock inputs are LOW. However, changing PE trom LOW to HIGH while CP is HIGH, or changing PE from HIGH to LOW while GP; is HIGH and CP2 is LOW will not cause any changes on the register outputs. MODE SELECT TABLE OPERATING _ INPUTS OUTPUTS MODE | PE CP; CP2 Ds Pn| Qo Qi @ a | bot x ot KIL g@ a @ LoL xX h X}|H gw a a pp Pe Lot ob xX X | No Change Soe L XX | No Change LoH L XX | No Change Mode Change}J 4 & XX | Undetermined Lt oH X= X | Undetermined Fou H XX | No Change Lo oH =H X= X | Undetermined JH =H X_=X | No Change 1= LOW Vottage Level one set-up time prior to the HIGH-to-LOW clock transition, n= HIGH Voltage Level one set-up time prior to the HIGH-to-LOW clock transition Bn = Lower case letters indicate the state of the referenced input or output one set-up time prior to the HIGH-to-LOW clock transition, H= HIGH Voltage Level L = LOW Voltage Level X= Immaterial LOGIC DIAGRAM P ° » Ps . 3d 66 gb pt . ‘| J 00 ye Vv UV | > o D Hy ; +H | i V V V V ls | o o a cy 4-127

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specitied SYMBOL PARAMETER ae CoNorTIONs leo Power Supply Current [3] a1 [_ ma_| vcc=Max AC CHARACTERISTICS: Vc = +5.0 V, Ta = +25°C (See Section 3 for waveforms and load configurations) sai74_ | S4/7aLS SYMBOL CL =15pF|C.=15pF| UNITS CONDITONS Ru = 4000 tH Propagation Delay 27 27 ; ’ tere GP: or CP2 to On 32 27 Figs. 3-1, 3-9 AC OPERATING REQUIREMENTS: Voc = +5.0 V, Ta = +25°C er [ramen Tafa wv cows tiH) Setup Time HIGH or LOW 15 Fig. 87 x) Ds or Pn to CPn 15 19 tH) Hold Time HIGH or LOW Fig. 3-7 thi Ds or Pr to CPn o> tw (H) GP, Pulse Width HIGH [2 [a | ns | Fig 39 Enable Time LOW , fen PE to CPi ls [= | om | Fig Inhibit Time HIGH ' ton a Co ee Fig Enable Time HIGH : Inhibit Time LOW ; fon PE to CP lo [= | | Fig. ve vn --~ wen of ve tet tet om ve 18v (0a vFoRts) Fig. a 4-128