7490A ETC | Alldatasheet

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DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divide- by-five counter. It can be connected to operate with a conventional BCD out­ put pattern or it can be connected to provide a 50% duty cycle output. In the BCD mode, HIGH signals on the Master Set (MS) inputs set the outputs to BCD nine. HIGH signals on the Master Reset (MR) inputs force all outputs LOW. For a similar counter with corner power pins, see the ’LS290; for dual versions, see the ’LS390 and ’LS490. ORDERING CODE: See Section 9 PIN OUT COMMERCIAL GRADE MILITARY GRADE PKG TYPEPKGS Vcc = +5.0 V ±5%, T a = 0°C to +70°C Vcc = +5.0 V ±10%, TA = -55° C to +125° C Plastic DIP (P) A 7490APC, 74LS90PC 9A Ceramic DIP (D) A 7490ADC, 74LS90DC 5490ADM, 54LS90DM 6A Flatpak (F) A 7490AFC, 74LS90FC 5490AFM, 54LS90FM 3I CONNECTION DIAGRAM PINOUT A LOGIC SYMBOL 6 7 Vcc = Pin 5 GND = Pin 10 NC = Pins 4,13 INPUT LOADING/FAN-OUT: See Section 3 for U.L. defintions PIN NAMES DESCRIPTION 54/74 (U.L.) HIGH/LOW 54/74LS (U.L.) HIGH/LOW CPo +2 Section Clock Input (Active Falling Edge) 2.0/2.0 0.125/1.5 CPi -H5 Section Clock Input (Active Falling Edge) 3.0/3.0 0.250/2.0 MRi, MR2 Asynchronous Master Reset Inputs (Active HIGH) 1.0/1.0 0.5/0.25 MSi , MS2 Asynchronous Master Set (Preset 9) Inputs (Active HIGH) 1.0/1.0 0.5/0.25 Qo -j-2 Section Output* 20/10 10/5.0 (2.5) 0 00 o -^-5 Section Outputs 20/10 10/5.0 (2.5) *The Qo output is guaranteed to drive the full rated fan-out plus the CPi input.

FUNCTIONAL DESCRIPTION — The ’90 is a 4-bit ripple type decade counter. It consists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not beused forelocks or strobes. The Qo output of each device is designed and specified to drive the rated fan-out plus the CPi input. A gated AND asynchronous Master Reset (MRi, MR 2) is provided which overrides the clocks and resets (clears) all the flip-flops. A gated AN D asynchronous Master Set (MS 1, MS2) is provided which overrides the clocks and the MR inputs and sets the outputs to nine (HLLH). Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes.: A. BCD Decade (8421) Counter —The CP 1 input must be externally connected to the Qo output. The CPo input receives the incoming count and a BCD count sequence is produced. B. Symmetrical Bi-quinary Divide-By-Ten Counter —The Q 3 output must be externally connected to the CPo input. The input count is then applied to the CP 1 input and a divide-by-ten square wave is obtained at output Qo. C. Divide-By-Two and Divide-By-Five Counter —No external interconnections are required. The first flip-flop is used as a binary element for the divide-by-two function (CPo as the input and Qo as the output). The CP1 input is used to obtain binary divide-by-five operation at the Q 3 output. MODE SELECTION RESET/SET INPUTS OUTPUTS MR1 MR2 MS1 MS2 Qo Q1 Q3 Q 3 H H L X L L L L H H X L L L L L X X H H H L L H L X L X Count X L X L Count L X X L Count X L L X Count H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial BCD COUNT SEQUENCE COUNT OUTPUTS Qo Q1 Q2 Q*3

0 L L L L

1 H L L L

2 L H L L

3 H H L L

4 L L H L

5 H L H L

6 L H H L

7 H H H L

8 L L L H

9 H L L H

NOTE: Output Qo is connected to Input CP1 for BCD count. LOGIC DIAGRAM MR1 MR2 CPo CP1 MR1 MR2 Qo Q1 Q2 Q3

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONS Min Max IlH Input HIGH Current, CPo 1.0 0.2 mA Vcc = Max, Vin = 5.5 V hH Input HIGH Current CPi 1.0 0.4 mA Vcc = Max, Vin = 5.5 V lee Power Supply Current 42 15 mA Vcc - Max AC CHARACTERISTICS: Vcc = +5.0 V, Ta = +25°C (See Section 3 for waveforms and load configurations) SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONSCl = 15 pF Rl = 400 ft Cl = 15 pF Min Max Min Max fmax Maximum Count Frequency, CPo 32 32 MHz Figs. 3-1, 3-9 fmax Maximum Count Frequency, CPi 16 16 MHz Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPo to Qo 18 ns Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPo to Q3 50 ns Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPi to Qi 21 ns Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPi to Q 2 35 ns Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPi to Q 3 35 ns Figs. 3-1, 3-9 tPLH Propagation Delay MS to Qo and Q 3 30 30 ns Figs. 3-1, 3-17 tPHL Propagation Delay MS to Q1 and Q 3 40 40 ns Figs. 3-1, 3-17 tPHL Propagation Delay MR to Qn 40 40 ns Figs. 3-1, 3-17 AC OPERATING REQUIREMENTS: Vcc = +5.0 V, Ta = +25°C SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONS Min Max Min Max tw (H) CPo Pulse Width HIGH 15 15 ns Fig. 3-9 tw (H) CPi Pulse Width HIGH 30 30 ns Fig. 3-9 tw (H) MS Pulse Width HIGH 15 15 ns Fig. 3-17 tw (H) MR Pulse Width HIGH 15 15 ns Fig. 3-17 tree Recovery Time, MS to CP 25 25 ns Fig. 3-17 tree Recovery Time, MR to CP 25 25 ns Fig. 3-17