SN54LS73A MOTOROLA | Alldatasheet
Document overview
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Technical content
The SN54LS/74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will per- form according to the truth table as long as minimum set-up times are ob- served. Input data is transferred to the outputs on the negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) Q K 13 (8) 3 (10) Q 12 (9) CLEAR 2 (6) J 14 (7) 1 (15) CLOCK (CP ) MODE SELECT — TRUTH TABLE OPERATING MODE INPUTS OUTPUTS OPERATING MODE C D J K Q Q Reset (Clear) Toggle Load “0” (Reset) Load “1” (Set) Hold L H H H H X h l h l X h h l l L q L H q H q H L q H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time l, h (q) = prior to the HIGH to LOW clock transition. SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 N SUFFIX PLASTIC CASE 646-06
ORDERING INFORMATION
VCC = PIN 4 GND = PIN 11 J Q CP K QC D