74LS363 ETC1 | Alldatasheet
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Octal Transparent Latch With 3-State Outputs Product Specification Logic Products FEATURES TYPICAL PROPAGATION | TYP! ee = “Darter wos compatible output ["yacsoeg [tens ema ‘Common Latch Enable input with hyst ORDERING CODE Common 3-state Output Enable COMMERCIAL RANGE control Veo = BV £5%; Ta=0°C to +70°C * Independent latch and 3-state butter operation Nove For information regarding dovices processed to Miltary Specifications, see the Signatcs Miltary Products Data Manual
DESCRIPTION
The '363 is an octal transparent latch INPUT AND OUTPUT LOADING AND FAN-OUT TABLE coupled to eight 3-state output butfers. The two sections of the device aro [__ PINS | Descniprion, [aus Conleddopondonty by tn ex) [ws | ae ans aa Ere CB ons [ ig [os | cs | gates. NOTE: The data on the D inputs is transferred A 7ALS unt load (LSU) # 20UA Ing and ~0.4mA ty. to the Latch outputs when the Latch ; - Enable (E) input is HIGH. The latch Present one set-up time before the built in to help minimize problems that remains transparent to the Data inputs HIGH-to-LOW enable transition. The en- signal and ground noise can cause on while E is HIGH, and stores the data ab! gatehas about 400mV of hysteresis the latching operation. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) us a enol [29) Yeo 0» fa 0, \\ 2 2 es =m re ee fo > 9 o Fal 0, a le f2) os Tote oo 0; 04 &% & . n oo oo a, 03 fH = Pee awww oo a a G] [2) oy owe “ ri 5 ono a] Fe of} Yoo = Pn 20 GzP 90 a December 4, 1985 5-512 853-0478 81500
Signetics Logic Products Product Specification Latch 74LS363 The 3-state output buffers are designed to feature makes these devices ideal for driving latch operation. When OE is LOW, the drive heavily loaded 3-stato buses, MOS MOS memories or microprocessors with latched or transparent data appears at the Put HIGH level differs from the normal 3-state ns the HIGH impedance “off state, which buter by driving the output about 1V closer to 7Pe, tive LOW Output Enable (OE) controls means they will nether chive nor load the bus. Voc, OF to over 3.5V at minimum Voc. This ‘a! butlers indeper LOGIC DIAGRAM ° > 9, % 5 % > aS oJ my o " on oo an) ct) £—Do V7 7 4 v 7 4 V7 7 a_plit [7 [¥ [7 [y fF —F eo oO Oo cn % Os Oe or Yoo = Pin 20, Sb = Pn 10 MODE SELECT— FUNCTION TABLE orsnaing moose aoe INTERNAL REGISTER ae L L L L L L L L a 11 = HIGH vollage level h = HIGH voltage level ono sot-up time prior to the HIGH-to-LOW enable tansiion = LOW voltage level {| LOW voltage level one setup time prior to the HIGH-to-LOW enable transition (2) =HIGH impedance “off” state ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature range unless otherwise noted.) a Ym et vote [eee [vt [iu etewetSSSCSCSSC~dS we December 4, 1985 5-513
Signetics Logic Products Product Specification Latch 74LS363 RECOMMENDED OPERATING CONDITIONS Se [4 twee apt vrage in HIGH ut wage ee a Ts Opening toa orprtre i DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) TEST CONDITIONS | raseea | [ox Hiiiowd eupa coon | Var=MRL Vn= Wi Va=MARTw=wAK ses || |v _| Vox LOW:eve! ouput voltage Voo= MIN Viw= man, [lus wax [oss [os |v | [oc tost camp vowed vee=m em v Off-state output current, ' - - [om ert is |emoe vera voraein ||| | Off-state output current, - - . co te me [veri wrt vorowr | | Input current at maximum . - [femme NY [oecnmeweror To | [in Woon! nt anon | Vorcuac vive | [a Lowi! put arent | veo wax Vinay em] [ios Storreat ovout non [vec=ax da | =00 | [lez Say owen tou [Voor uax Caan —SSSCSC~S~sSi PO | NOTES: 1.For conditions shown as MIN or MAX, use the appropriate value specied under recommended operating conditions for the applicable type. 2. All typical values are at Voc = SV, Ta = 28°C. 3. log 1s tested with Vour = +0.5V and Voc = Voc MAX + 0.5V. Not more than one output should be shorted at a time and duration of the short circuit should not ‘exc90d one second AC ELECTRICAL CHARACTERISTICS Tx = 25°C, Voc = 5.0V Pu Propagation delay tPHL Latch enable to output teu Propagation delay 23 tea Data to output 27 toro wre HGH ve | Wawa? | Pe [ten Enslo uno 10 LOW ov | Wavwtoma ———— aee [ine Debi ino om HGH iv | Waveom-a, Gonape@ [Pas | [ten Osebietve tom LOW mot | Waveioms. nse |) ase December 4, 1985 5-514
Signetics Logic Products Product Specification Latch 74LS363 AC SET-UP REQUIREMENTS 1, = 25°C, Voc = 5.0V S| = eel] [tw Latch enable pulse wiatn | Wavotorm i |S [4 Setup time, data to latch enable | Wavetorm 5 TOT | [ie Hoid timo, data to fateh enable | Wavetorm 5 [vo] AC WAVEFORMS ee Se ae . ‘ ‘ Mu | = bey ‘ewe"| osv oo vr ° ve atv ° ‘a Vu wees Waveform 1. Latch Enable To Output i Waveform 2. 3-State Enable Time To High Delays And Latch Enable Pulse Width Level And Disable Time From High Level ‘ezi~| be hess on a Fee cates enaile, Time To Low Waveform 4. Propagation Delay Data To Q Outputs —D Wy My “— of The shused avons neste hw woul pareate changer V2 une Waveform 5. Data Set-up And Hold Times. December 4, 1985 5-516
Signetics Logic Products Product Specification eee a leu Latch 74LS363 SSS TEST CIRCUITS AND WAVEFORMS Veo Yoo rors we oN in weaanive | YH vw PULSE 10% 10%; w vy Me /* ES 4 rat runt q a y srt crm y 90% 90%" amp ii Positive =F F FF PULSE, ve vw oe —_ Vue 1.3 for TALS: Ve 1.5 for al othr TTL tion Test Circult For 3-State Outputs Input Pulse Definition SWITCH POSITION [test | swiren's[swren 2] ram INPUT PULSE REQUIREMENTS ta ae en [su | tm | ee owe Open | Amptude [Rep ate | Pues wth | tun | ta ae ee [vas | sov [swe | s00ne | 15ns | one | DEFINITIONS een to Voc a AC CHARACTERISTICS fr [|sov [mie | soons [2s] 26ns | valve. C= Load capacitance includes jig and probe capacitance;
800 AC CHARACTERISTICS for value,
Ry = Termination resistance should be equal to Zour of Pulse Generators. D= Diodes are 1N916, 1N3064, oF equivalont. Rx = 1k for 74, 74S, Rx = 5kQ for 74LS. tru try. Values should bo less than ot equal to the table enttos. December 4, 1985 5-516