74LS283 ETC | Alldatasheet

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4-Bit Full Adder With Fast Carry Product Specification Logic Products FEATURES TYPICAL PROPAGATION | TYPICAL SUPPLY CURRENT ‘© High-speed 4-bit binary addition DELAY (TOTAL) S Gzscaable in @-it Increments | aausees [tan Tom ‘© Fast internal carry lookahead DESCRIPTION ORDERING CODE The '283 adds two 4-bit binary words (A, COMMERCIAL RANGE plus 8,) plus the incoming carry. The Voc = SV #5%; Ta=O0°C to +70°C binary sum appears on the Sum outputs (21-2 4) and the outgoing carry (Cour) focoring fo the enuson Gin + (Ay + By) + 2(Az + Ba) NOTE: stay 6, Mi +4 (Ag + Bg) + 8(Ag + By) Fat flomaton rung dovens recessed o Many Specicatos, sete Sac Mia rode = 2442024409 +824 + 16Cour Where (+) = plus. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE Due othe smmaty fre tiny aa [rms [—besonnon a function, the '283 can be used with 3 either all active HIGH operands (positive |___— © 8 | mmuts Tats | foi) oral acto LOW operands rogae [ ow | mt Oe TOW oerante the recane, LAH [twats sus of all active LOW operands the results E4-24and Cour should be interpreted NOTE: it ‘ a se ae astve COW. With active HIGH 71S Unt load (LSU is 20AA ty and -D4MA I inputs, Cjy cannot be left open; it must intended. interchanging inputs of equal thus Cy, Ay, 8; can arbitrarily be as- be held LOW when no "‘carry in” is weight does not affect the operation, signed to pins 5, 6, 7, etc. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 2G 1) vee Se azmiwad s[oy ® Gy [3 05 Fry ° — a ‘Ar By Az B2 Ay 03 Ay By 2d, + yo [a rs 71cm Cour}— * «|, | 7 a fa Ae £402 EaZa 21"), sfc iG fe a], ow OF fia) Ey an ano (] [3) Cour a ct co] Voc ° in 16 ohn 8 / December 4, 1985 5-475 859-0472 81500

Signetics Logic Products Product Specification Adder 7ALS283 LOGIC DIAGRAM Cu i Be Ay Ma tl = th | | YUU UO ro Ie a see ee | qt at SH | | TT TF a | a ee a | Sby bbb bbb by Ot

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Voc = Pin 16 —_ FUNCTION TABLE [pins [cm [As [Aa [As [Ae 8 [ee | es [oe [Es [Ee [5 | Fe [Cour] Eames | tooeteves [ete lefetatatetetatatafetet eh] so [ acwo nigh | o fo | + foft+{sfofols{r{sfolfo] : | 10 ey [acwovcow [i [sr fofsfofo[s{sfofofofr] i] o | ere ei em ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature range unless otherwise noted.) [ anaeve Tm] ie ret oe December 4, 1985 5-476

Signetics Logic Products Product Specification Adder 74LS283 RECOMMENDED OPERATING CONDITIONS “ere eed aa Vee Supaly votage [ 47 | so | sas |v | Ys (OW! wp vag re i ot acer er tx (OW pat erat ee Th Opi teva rps es DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) ‘TEST CONDITIONS’ Vou HIGH-evel output voltage Voo= MIN, Vin=MIN, Vi=MAX. lon=Max | 27 [| 94 [| ov | Voo= Min, Vw= Min, [loo=Max || as | os |v | Vo. — LOW-level output voltage Vix Input clamp vatage LL ca Input current at maximum ABinmus [ff 02 | ma | iT Voc = MAX, Vi=7.0V [AB inoue | tne MGHove put cures — | Voce max vez | %E a [enon | |] | oe] [asm [| -08 | ma _| tw LOW-ovel input current Voo = MAX, Vi = 0.4V a eS le Sip caer go SS NOTES: 1. For conditions shown ae MIN of MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All ypicsl values are at Voc ™ BV, Ta = 25°C. 3. log if tested with Vour = +0.5V and Voc = Voc MAX + 0.8V. Not more than one output should bo shorted at a time and duration of the short ccuit should not exceed one second. 4. lac should be measured with all outputs open and the following conditions: Condition 1: All inputs grounded Condition 2: All B inputs LOW, other inputs at 4.5V Condition 3: Al inputs at 48 AC WAVEFORMS Vuc* 1.20 for TALS, Vig= 1.5V forall otter TTL tam tes V2 10 for TALS, Vig= 1.5V for ll otter TTL lai. Wayetorm 1. Waveform For Inverting Outputs Waveform 2. Waveform For Non-Inverting Outputs December 4, 1985 5-477

Signetics Logic Products Product Specification Adder 7ALS283 AC ELECTRICAL CHARACTERISTICS 1, = 25°C, Voc =5.0V mus cova on tour Propagation delay See eee [a | ‘eux Propagation delay ae wee OE = | ten Propagation delay te Cin to E 3 te.n Propagation delay ton Cw to Ea PUM Propagation delay ns fon __Ai or BV: to Ey ten Propagation delay 7 tea Cin to Cour 22 ten Propagation delay 7 ten. Ay or 8 to Cour Wavetorms 1 & 2 17 TEST CIRCUITS AND WAVEFORMS = Aw. a AMP vee Wee weoarve |v vm Pus “. 10% 10% ow vor iad [achtton aot trate mut: ¥ rustle rH. m0 | _ = ame (wv) y Posinive tid lift PULSE vw vw i vemos 10%, ww 10% ay V2 12V for 7ALS; Vu = 150 forall hor TTL tain Test Circuit For 74 Totem-Pole Outputs Input Pulse Definition | A= Loud restr to Voc; #80 AC CHARACTERISTICS fr va INPUT PULSE REQUIREMENTS | \\.~ Load resistor to Voc: see value! FAMILY | i ond capstan rao jg ard be caps | Amptde [Rep Rate] Pane with | tun | tm || see AC CHARACTERISTICS tor value | fy = Termnaton resistance should be equal 10 Zour [7% | sov | saz | soons { 7ns | zoe | | of Pulse Generators

0 Ciodee are INETG, IN8064, or equalot [zs |_aov [wee | soons [608 ens |

tro tra Valse shoud be less than or equal Yo the table December 4, 1985 5-478