74LS221N

SN54LS221 MOTOROLA | Alldatasheet

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Technical content

(TOP VIEW) positive logic: Low input to clear resets Q low and positive logic: Q high regardless of dc levels at A positive logic: or B inputs. /C0049/C0052/C0049/C0051 /C0049/C0050 /C0049/C0049 /C0049/C0048 /C0057 /C0049 /C0050 /C0051 /C0052 /C0053 /C0054/C0055 /C0049/C0054 /C0049/C0053 /C0056 /C0086/C0067/C0067 /C0049/C0065 /C0049 /C0082/C0101/C0120/C0116/C0047 /C0067/C0101/C0120/C0116 /C0049 /C0067/C0101/C0120/C0116/C0049/C0081 /C0050/C0081/C0050/C0066 /C0050 /C0067/C0076/C0082/C0050/C0065 /C0049/C0066 /C0049 /C0067/C0076/C0082 /C0049/C0081/C0050/C0081 /C0050 /C0067/C0101/C0120/C0116 /C0050 /C0082/C0101/C0120/C0116/C0047 /C0067/C0101/C0120/C0116 /C0071/C0078/C0068 /C0081 /C0081 /C0067/C0076/C0082 /C0081 /C0081 /C0067/C0076/C0082 /C0043 /C0086/C0067/C0067 /C0082/C0101/C0120/C0116 /C0082/C0047/C0067/C0067/C0101/C0120/C0116 *See operational notes — Pulse Trigger Modes 5-380 FAST AND LS TTL DATA DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS Each multivibrator of the LS221 features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt/second, providing the circuit with excellent noise immunity. A high immunity to VCC noise is also provided by internal latching circuitry. Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of any duration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With Rext = 2.0 kΩ and Cext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 µF), and greater than one decade of timing resistance (2.0 to 70 kΩ for the SN54LS221, and 2.0 to 100 kΩ for the SN74LS221). Pulse width is defined by the relationship: tw (out) = CextR ext ln 2.0 ≈/n6368617200000000000000000.7 Cext Rext; where tW is in ns if Cext is in pF and Rext is in kΩ . If pulse cutoff is not critical, capacitance up to 1000 µF and resistance as low as 1.4 kΩ may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature.

• SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot
• Overriding Clear Terminates Output Pulse
• Pin Out is Identical to SN54/74LS123 FUNCTION TABLE (EACH MONOSTABLE) INPUTS OUTPUTS CLEAR A B Q Q L X X L H X H X L H X X L L H H L /C0176 H /C0177H */C0176 L H TYPE TYPICAL POWER MAXIMUM OUTPUT PULSE DISSIPATION LENGTH SN54LS221 23 mW 49 s SN74LS221 23 mW 70 s SN54/74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 N SUFFIX PLASTIC CASE 648-08

ORDERING INFORMATION

Once in the pulse trigger mode, the output pulse width is determined by tW = RextC extIn2, as long as Rext and Cext are within their minimum and maximum valves and the duty cycle is less than 50%. This pulse width is essentially independent of VCC and temperature variations. Output pulse widths varies typically no more than ±0.5% from device to device. tW T If the duty cycle, defined as being 100• where T is the inputperiod of the input pulse, rises above 50%, the output pulse width will become shorter. If the duty cycle varies between low and high valves, this causes the output pulse width to vary in length, or jitter. To reduce jitter to a minimum, Rext should be as large as possible. (Jitter is independent of Cext). With Rext = 100K, jitter is not appreciable until the duty cycle approaches 90%. Although the LS221 is pin-for-pin compatible with the LS123, it should be remembered that they are not functionally identical. The LS123 is retriggerable so that the output is dependent upon the input transitions once it is high. This is not the case for the LS221. Also note that it is recommended to externally ground the LS123 Cext pin. However, this cannot be done on the LS221. The SN54LS/74LS221 is a dual, monolithic, non-retrigger- able, high-stability one shot. The output pulse width, tW can be varied over 9 decades of timing by proper selection of the external timing components, Rext and Cext. Pulse triggering occurs at a voltage level and is, therefore, independent of the input slew rate. Although all three inputs have this Schmitt-trigger effect, only the B input should be used for very long transition triggers (≥1.0 µV/s). High immunity to VCC noise (typically 1.5 V) is achieved by internal latching circuitry. However, standard VCC bypassing is strongly recommended. The LS221 has four basic modes of operation. Clear Mode: If the clear input is held low, irregardless of the previous output state and other input states, the Q output is low. Inhibit Mode: If either the A input is high or the B input is low, once the Q output goes low, it cannot be retriggered by other inputs. Pulse Trigger Mode: A transition of the A or B inputs as indicated in the functional truth table will trigger the Q output to go high for a duration determined by the tW equation described above; Q will go low for a corresponding length of time. The Clear input may also be used to trigger an output pulse, but special logic precondi- tioning on the A or B inputs must be done as follows: Following any output triggering action using the A or B inputs, the A input must be set high OR the B input must be set low to allow Clear to be used as a trigger. Inputs should then be set up per the truth table (without triggering the output) to allow Clear to be used a trigger for the output pulse. If the Clear pin is routinely being used to trigger the output pulse, the A or B inputs must be toggled as described above before and between each Clear trigger event. Once triggered, as long as the output remains high, all input transitions (except overriding Clear) are ignored. Overriding Clear Mode: If the Q output is high, it may be forced low by bringing the clear input low.

GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient T emperature Range 54 –55 125 IOH Output Current — High 54, 74 –0.4 mA IOL Output Current — Low 54 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions VT+ Positive-Going Threshold Voltage at C Input 1.0 2.0 V VCC = MIN VT– Negative-Going Threshold Voltage at C Input 54 0.7 0.8 V VCC = MINVT– Negative-Going Threshold Voltage at C Input 74 0.7 0.8 V VCC = MIN VT+ Positive-Going Threshold Voltage at B Input 1.0 2.0 V VCC = MIN VT– Negative-Going Threshold Voltage at B Input 54 0.7 0.9 V VCC = MINVT– Negative-Going Threshold Voltage at B Input 74 0.8 0.9 V VCC = MIN VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for A Input VIL Input LOW Voltage 54 0.7 V Guaranteed Input LOW Voltage for A InputVIL Input LOW Voltage 74 0.8 V Guaranteed Input LOW Voltage for A Input VIK Input Clamp Voltage –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 54 2.5 3.4 V VCC = MIN, IOH = MAXVOH Output HIGH Voltage 74 2.7 3.4 V VCC = MIN, IOH = MAX VOL Output LOW Voltage 54 0.25 0.4 V IOL = 4.0 mA VCC = MINVOL Output LOW Voltage 74 0.35 0.5 V IOL = 8.0 mA VCC = MIN IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH Current 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current Input A Input B Clear –0.4 –0.8 –0.8 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current Quiescent 4.7 11 mA VCC = MAXICC Triggered 19 27 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C) Symbol From (Input) To (Output) Limits Unit Test ConditionsSymbol From (Input) To (Output) Min Typ Max Unit Test Conditions tPLH A Q 45 70 ns C L = 15 pF , See Figure 1 C ext = 80 pF , Rext = 2.0 Ω tPLH B Q 35 55 ns C L = 15 pF , See Figure 1 C ext = 80 pF , Rext = 2.0 ΩtPHL A Q 50 80 ns C L = 15 pF , See Figure 1 C ext = 80 pF , Rext = 2.0 ΩtPHL B Q 40 65 ns C L = 15 pF , See Figure 1 C ext = 80 pF , Rext = 2.0 Ω tPHL Clear Q 35 55 ns C L = 15 pF , See Figure 1tPLH Clear Q 44 65 ns C L = 15 pF , See Figure 1 tW(out) A or B Q or Q 70 120 150 ns C ext = 80 pF , Rext = 2.0 Ω tW(out) A or B Q or Q 20 47 70 ns C ext = 0, Rext = 2.0 kΩ tW(out) A or B Q or Q 600 670 750 C ext = 100 pF , Rext = 10 kΩ 6.0 6.9 7.5 ms C ext = 1.0 µF, Rext = 10 kΩ AC SETUP REQUIREMENTS (VCC = 5.0 V, TA = 25°C) Symbol Parameter Limits UnitSymbol Parameter Min Typ Max Unit dv/dt Rate of Rise or Fall of Input Pulse dv/dt Schmitt, B 1.0 V/sdv/dt Logic Input, A 1.0 V/µs tW Input Pulse Width tW A or B, tW(in) 40 nstW Clear, tW (clear) 40 ts Clear-Inactive-State Setup Time 15 ns R ext External Timing Resistance 54 1.4 70 kΩR ext External Timing Resistance 74 1.4 100 kΩ C ext External Timing Capacitance 0 1000 µF Output Duty Cycle RT = 2.0 kΩ 50 % R T = MAX Rext 90

/C0066 /C0073/C0078/C0080/C0085/C0084 /C0067/C0076/C0069/C0065/C0082 /C0081 /C0079/C0085/C0084/C0080/C0085/C0084 /C0081 /C0079/C0085/C0084/C0080/C0085/C0084 /C0065 /C0073/C0078/C0080/C0085/C0084 /C0073/C0083 /C0076/C0079/C0087/C0046 /C0066 /C0073/C0078/C0080/C0085/C0084 /C0067/C0076/C0069/C0065/C0082 /C0081 /C0079/C0085/C0084/C0080/C0085/C0084 /C0065 /C0073/C0078/C0080/C0085/C0084 /C0073/C0083 /C0076/C0079/C0087/C0046 /C0066 /C0073/C0078/C0080/C0085/C0084 /C0067/C0076/C0069/C0065/C0082 /C0081 /C0079/C0085/C0084/C0080/C0085/C0084 /C0065 /C0073/C0078/C0080/C0085/C0084 /C0073/C0083 /C0076/C0079/C0087/C0046 /C0116/C0087/C0040/C0105/C0110/C0041 ≥/C0054/C0048 /C0110/C0115 /C0116/C0080/C0076/C0072 /C0116/C0080/C0072/C0076/C0116/C0080/C0076/C0072 /C0116/C0080/C0072/C0076 /C0049/C0046/C0051 /C0086 /C0051 /C0086 /C0048 /C0086 /C0051 /C0086 /C0048 /C0086 /C0086/C0079/C0072 /C0086/C0079/C0076 /C0086/C0079/C0072 /C0086/C0079/C0076 ≥ /C0054/C0048 /C0110/C0115 /C0049/C0046/C0051 /C0086 /C0049/C0046/C0051 /C0086 /C0051 /C0086 /C0048 /C0086 /C0051 /C0086 /C0048 /C0086 /C0086/C0079/C0072 /C0086/C0079/C0076 ≥/n636861720000000000000000/C0053/C0048 /C0110/C0115≥/n636861720000000000000000/C0048 /C0116/C0115 /C0051 /C0086 /C0048 /C0086 /C0051 /C0086 /C0048 /C0086 /C0086/C0079/C0072 /C0086/C0079/C0076 /C0051 /C0086 /C0048 /C0086 /C0051 /C0086 /C0048 /C0086 /C0086/C0079/C0072 /C0086/C0079/C0076 /C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0078/C0079/C0084 /C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 ≥ /C0053/C0048 /C0110/C0115≥ /C0053/C0048 /C0110/C0115 /C0066 /C0073/C0078/C0080/C0085/C0084 /C0067/C0076/C0069/C0065/C0082 /C0081 /C0079/C0085/C0084/C0080/C0085/C0084 /C0065 /C0073/C0078/C0080/C0085/C0084 /C0073/C0083 /C0076/C0079/C0087/C0046 /C0116/C0087/C0040/C0111/C0117/C0116/C0041 TRIGGER FROM B, THEN CLEAR — CONDITION 1 TRIGGER FROM B, THEN CLEAR — CONDITION 2 CLEAR OVERRIDING B, THEN TRIGGER FROM B TRIGGERING FROM POSITIVE TRANSITION OF CLEAR Figure 1

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