SN54LS196 MOTOROLA | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 6
Technical content
The SN54/74LS196 decade counter is partitioned into divide-by-two and di- vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output. The SN54/74LS197 contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter. Low Power Schottky technology is used to achieve typical count rates of 70 MHz and power dis- sipation of only 80 mW. Both circuit types have a Master Reset (MR ) input which overrides all other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL) overrides clocked operations and asynchronously loads the data on the Par- allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits usable as programmable counters. The circuits can also be used as 4-bit latches, loading data from the Parallel Data inputs when PL is LOW and stor- ing the data when PL is HIGH.
- Low Power Consumption — Typically 80 mW
- High Counting Rates — Typically 70 MHz
- Choice of Counting Modes — BCD, Bi-Quinary, Binary
- Asynchronous Presettable
- Asynchronous Master Reset
- Easy Multistage Cascading
- Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) 14 13 12 11 10 9 123456 VCC MR Q 3 P3 P1 Q 1 CP 0 PL Q 2 P2 P0 Q 0 CP 1 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.PIN NAMES LOADING (Note a) HIGH LOW Input to Divide-by-Two Section Input to Divide-by-Five Section Input to Divide-by-Eight Section NOTES: b. Temperature Ranges. c. In addition to loading shown, Q0 can also drive CP SN54/74LS196 SN54/74LS197 4-STAGE PRESETTABLE RIPPLE COUNTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 N SUFFIX PLASTIC CASE 646-06
ORDERING INFORMATION
VCC = PIN 14 GND = PIN 7
SN54/74LS196 • SN54/74LS197 LOGIC DIAGRAM LS196 LS197 MR PL CP 0 CP 1 P0 P1 P2 P3 Q 0 Q 1 Q 2 Q 3 J SD Q K C D Q 5 9 1013 J SD Q K C D Q J SD Q K C D Q J SD Q K C D Q VCC = PIN 14 GND = PIN 7 = PIN NUMBERS MR PL CP 0 CP 1 P0 P1 P2 P3 Q 0 Q 1 Q 2 Q 3 J SD Q K C D Q 5 9 1013 J SD Q K C D Q J SD Q K C D Q J SD Q K C D Q
of the interstage gating delay within the divide-by-five section. Figure 2. LS196 COUNT SEQUENCES
0 L L L L 0 L L L L
1 L LL H 1 L LL H
2 L LHL 2 L LH L
3 L LH H 3 L LH H
4 L HLL 4 L HL L
5 L HLH 5 H LL L
6 L HHL 6 H LL H
7 L HHH 7 H LH L
8 H LLL 8 H LH H
9 H L L H 9 H H L L
- Signal applied to CP0, Q0 connected to CP1.
- Signal applied to CP1, Q3 connected to CP0.
SN54/74LS196 • SN54/74LS197 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 –55 125 IOH Output Current — High 54, 74 –0.4 mA IOL Output Current — Low 54 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Sb l P Limits Ui T C di iSymbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 V Guaranteed Input LOW Voltage forVIL Input LOW Voltage 74 0.8 V pg All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIHVOH O utput HIGH Voltage 74 2.7 3.5 V CC , OH , IN IH or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, VIN =V ILor VIHVOL O utput LOW Voltage 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current Data, PL MR , CP0 (LS196) MR , CP0, CP1 (LS197) CP 1 (LS196) µA VCC = MAX, VIN = 2.7 V IIH Data, PL MR , CP0 (LS196) MR , CP0, CP1 (LS197) CP 1 (LS196) 0.1 0.2 0.2 0.4 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current Data, PL MR CP 0 CP 1 (LS196) CP 1 (LS197) –0.4 –0.8 –2.4 –2.8 –1.3 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current 27 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
SN54/74LS196 • SN54/74LS197 AC CHARACTERISTICS (TA = 25°C) Sb l P Limits Ui T C di iSb l P LS196 LS197 Ui T C di iSymbol Parameter Min Typ Max Min Typ Max Unit Test Conditions fMAX Maximum Clock Frequency 30 40 30 40 MHz V5 0 V tPLH tPHL CP 0 Input to Q 0 Output 8.0 8.0 ns V5 0 V tPLH tPHL CP 1 Input to Q 1 Output ns V5 0 V tPLH tPHL CP 1 Input to Q 2 Output ns VCC = 5.0 V tPLH tPHL CP 1 Input to Q 3 Output ns CC C L = 15 pF tPLH tPHL Data to Output 20 ns tPLH tPHL PL Input to Any Output ns tPHL MR Input to Any Output 34 51 34 51 ns AC SETUP REQUIREMENTS (TA = 25°C) Sb l P Limits Ui T C di iSb l P LS196 LS197 Ui T C di iSymbol Parameter Min Typ Max Min Typ Max Unit Test Conditions tW CP 0 Pulse Width 20 20 ns V5 0 V tW CP 1 Pulse Width 30 30 ns V5 0 V tW PL Pulse Width 20 20 ns V5 0 V tW MR Pulse Width 15 15 ns V5 0 Vts Data Input Setup Time — HIGH 10 10 ns VCC = 5.0 V ts Data Input Setup Time — LOW 15 15 ns th Data Hold Time — HIGH 10 10 ns th Data Hold Time — LOW 10 10 ns trec Recovery Time 30 30 ns DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH to LOW in order to be recog- nized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recog- nition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH to LOW and still be recognized. RECOVERY TIME (t rec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH to LOW in order to recognize and transfer LOW Data to the Q outputs.
SN54/74LS196 • SN54/74LS197 AC WAVEFORMS Pn tW tPHLtPLH 1.3 V
1.3 VPL
1.3 V 1.3 V 1.3 V trec PL OR MR CP Q CP 1.3 V 1.3 V 1.3 V 1.3 V tPHL tPLH tW(H) Q Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 1.3 V 1.3 V 1.3 V tPHL tPLH Pn Q n NOTE: PL = LOW 1.3 V 1.3 V 1.3 V1.3 V Pn* PL Q n* ts(H) ts(L) th(H) th(L) * The shaded areas indicate when the input is permitted * to change for predictable output performance Q = P Q = P