74LS181

DM74LS181 FAIRCHILD | Alldatasheet

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Technical content

Features

■ Provides 16 arithmetic operations: add, subtract, com- pare, double, plus twelve other arithmetic operations ■ Provides all 16 logic operations of two variables: exclusive-OR, compare, AND, NAND, OR, NOR, plus ten other logic operations ■ Full lookahead for high speed arithmetic operation on long words Ordering Code: Logic Symbols Active High Operands Active Low Operands VCC = Pin 24 GND = Pin 12 Connection Diagram Pin Descriptions Order Number Package Number Package Description DM74LS181N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Pin Names Description A0–A3 Operand Inputs (Active LOW) B0–B3 Operand Inputs (Active LOW) S0–S3 Function Select Inputs M Mode Control Input C n Carry Input F0–F3 Function Outputs (Active LOW) A = B Comparator Output G Carry Generate Output (Active LOW) P Carry Propagate Output (Active LOW) C n+4 Carry Output

www.fairchildsemi.com 2 DM74LS181 Functional Description The DM74LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0–S3) and the Mode Control input (M), it can per- form all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW oper- ands. The Function Table lists these operations When the Mode Control input (M) is HIGH, all internal car- ries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device per- forms arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and pro- vides for either ripple carry between devices using the C n+4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the ADD mode, P indicates that F is 15 or more, while G indi- cates that F is 16 or more. In the SUBTRACT mode, P indi- cates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output n+4) signal to the Carry input (Cn) of the next unit. For high speed operation the device is used in conjunction with the 9342 or 93S42 carry lookahead circuit. One carry loo- kahead package is required for each group of four DM74LS181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode. The A = B output is open-collector and can be wired- AND with other A = B outputs to give a comparison for more than four bits. The A = B signal can also be used with the C n+4 signal to indicate A > B and A < B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complemen- tary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indi- cated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the oper- ands labeled inside the logic symbol. Function Table Note 1: Each bit is shifted to the next most significant position. Note 2: Arithmetic operations expressed in 2s complement notation. Mode Select Active LOW Operands Active HIGH Operands Inputs & F n Outputs & F n Outputs Logic Arithmetic (Note 2) Logic Arithmetic (Note 2) S3 S2 S1 S0 (M = H) (M = L) (Cn = L) (M = H) (M = L) (Cn = H) LLLL A A minus 1 A A LLLH A B AB minus 1 A + B A + B LLHL A + B AB minus 1 A BA + B L L H H Logic 1 minus 1 Logic 0 minus 1 LHLL A + B A plus (A + B)A B A plus AB LHLH B AB plus (A + B)B (A + B) plus AB LHHL A ⊕ B A minus B minus 1 A ⊕ B A minus B minus 1 LHHH A + B A + B AB AB minus 1 HLLL A B A plus (A + B) A + B A plus AB HLLH A ⊕ B A plus B A ⊕ B A plus B HLHL B A B plus (A + B) B (A + B) plus AB HLHH A + BA + B AB AB minus 1 H H L L Logic 0 A plus A (Note 1) Logic 1 A plus A (Note 1) HHLH A B AB plus A A + B (A + B) plus A H H H L AB AB minus A A + B( A + B) plus A H H H H AA AA m i n u s 1

3 www.fairchildsemi.com DM74LS181 Logic Diagram

www.fairchildsemi.com 4 DM74LS181 Absolute Maximum Ratings(Note 3) Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Note 4: All typicals are at VCC = 5V, TA = 25°C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units V CC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA TA Free Air Operating Temperature 0 70 °C Symbol Parameter Conditions Min Typ Max Units (Note 4) VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level V CC = Min, IOH = Max, 2.7 V Output Voltage V IL = Max VOL LOW Level V CC = Min, IOL = Max, 0.35 0.5 VOutput Voltage V IH = Min IOL = 4 mA, VCC = Min 0.25 0.4 II Input Current @ Max V CC = Max, VI = 7V M input 0.1 Input Voltage A n, Bn 0.3 mA Sn 0.4 C n 0.5 IIH HIGH Level V CC = Max, VI = 2.7V M input 20 Input Current A n, Bn 60 µA Sn 80 C n 100 IIL LOW Level V CC = Max, VI = 0.4V M input −0.4 Input Current A n, Bn −1.2 mA Sn −1.6 C n −2.0 IOS Short Circuit V CC = Max −20 −100 mA Output Current (Note 5) ICC Supply Current V CC = Max, Bn, Cn = GND 37 mA Sn, M, An = 4.5V

5 www.fairchildsemi.com DM74LS181 Switching Characteristics VCC = 5V, TA = 25°C Sum Mode Test Table 1 Function Inputs S0 = S3 = 4.5V, S1 = S2 = M = 0V Symbol Parameter Conditions C L = 15 pF Units Min Max tPLH Propagation Delay M = GND 27 ns tPHL C n to Cn+4 20 tPLH Propagation Delay M = GND 26 ns tPHL C n to F 20 tPLH Propagation Delay M, S 1, S2 = GND; 29 ns tPHL A or B to G (Sum) S 1, S3 = 4.5V 23 tPLH Propagation Delay M, S 0, S3 = GND; 32 ns tPHL A or B to G (Diff) S 1, S2 = 4.5V 26 tPLH Propagation Delay M, S 1, S2 = GND; 30 ns tPHL A or B to P (Sum) S 0, S3 = 4.5V 30 tPLH Propagation Delay M, S 0, S3 = GND; 30 ns tPHL A or B to P (Diff) S 1, S2 = 4.5V 33 tPLH Propagation Delay M, S 1, S2 = GND; 32 ns tPHL Ai or Bi to Fi(Sum) S 0, S3 = 4.5V 25 tPLH Propagation Delay M, S 0, S3 = GND; 32 ns tPHL Ai or Bi to Fi(Diff) S 1, S2 = 4.5V 33 tPLH Propagation Delay M = 4.5V 33 ns tPHL A or B to F (Logic) 29 tPLH Propagation Delay M, S 1, S2 = GND; 38 ns tPHL A or B to Cn+4 (Sum) S 0, S3 = 4.5V 38 tPLH Propagation Delay M, S 0, S3 = GND; 41 ns tPHL A or B to Cn+4 (Diff) S 1, S2 = 4.5V 41 tPLH Propagation Delay M, S 0, S3 = GND; 50 ns tPHL A or B to A = BS 1, S2 = 4.5V; 62 R L = 2 kΩ to 5.0V Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND tPLH Ai Bi None Remaining C n Fi tPHL A and B tPLH Bi Ai None Remaining C n Fi tPHL A and B tPLH A B None None Remaining P tPHL A and B, Cn tPLH B A None None Remaining P tPHL A and B, Cn tPLH A None B Remaining Remaining G tPHL B A, Cn tPLH B None A Remaining Remaining G tPHL B A, Cn tPLH A None B Remaining Remaining C n+4 tPHL B A, Cn tPLH B None A Remaining Remaining C n+4 tPHL B A, Cn tPLH C n None None All All Any F tPHL A B or Cn+4

www.fairchildsemi.com 6 DM74LS181 Diff Mode Test Table 2 Function Inputs S1 = S2 = 4.5V, S0 = S3 = M = 0V Logic Mode Test Table 3 Function Inputs S1 = S2 = M = 4.5V, S0 = S3 = 0V Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND tPLH A None B Remaining Remaining F i tPHL A B, Cn tPLH B A None Remaining Remaining F i tPHL A B, Cn tPLH A None B None Remaining P tPHL A and B, Cn tPLH B A None None Remaining P tPHL A and B, Cn tPLH A B None None Remaining G tPHL A and B, Cn tPLH B None A None Remaining G tPHL A and B, Cn tPLH A None B Remaining Remaining A = B tPHL A B, Cn tPLH B A None Remaining Remaining A = B tPHL A B, Cn tPLH A B None None Remaining C n+4 tPHL A and B, Cn tPLH B None A None Remaining C n+4 tPHL A and B, Cn tPLH C n None None All None C n+4 tPHL A and B Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND tPLH A B None None Remaining Any F tPHL A and B, Cn tPLH B A None None Remaining Any F tPHL A and B, Cn

7 www.fairchildsemi.com DM74LS181 4-Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N24A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com