SN54LS174 MOTOROLA | Alldatasheet

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Technical content

The LSTTL /MSI SN54 /74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. The LS174 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.

  • Edge-Triggered D-Type Inputs
  • Buffered-Positive Edge-Triggered Clock
  • Asynchronous Common Reset
  • Input Clamp Diodes Limit High Speed T ermination Effects NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. CONNECTION DIAGRAM DIP (TOP VIEW) 14 13 12 11 10 9 1 2 3 4 5 6 7 16 15 VCC MR Q 5 D 5 D 4 Q 4 Q 3D 3 CP Q 0 D 0 D 1 Q 1 D 2 Q 2 GND PIN NAMES LOADING (Note a) HIGH LOW D 0–D 5 CP MR Q 0–Q 5 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. NOTES: b. Temperature Ranges. LOGIC DIAGRAM D Q CPC D Q 5 Q 4 Q 3 Q 2 Q 1 Q 0 CP D 5 D 4 D 3 D 2 D 1 D 0MR 9 11 12 10 D Q CPC D D Q CPC D D Q CPC D D Q CPC D D Q CPC D VCC = PIN 16 GND = PIN 8 = PIN NUMBERS SN54/74LS174 HEX D FLIP-FLOP LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 N SUFFIX PLASTIC CASE 648-08

ORDERING INFORMATION

VCC = PIN 16 GND = PIN 8 D 5D 4D 3D 2D 1D 0 3 4 6 11 13 14 CP MR Q 2Q 1Q 0 Q 3 Q 4 Q 5 2 5 7 10 12 15

The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip- flop’s output following the LOW to HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LS174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. TRUTH TABLE Inputs (t = n, MR = H) Outputs (t = n+1) Note 1 D Q H H L L Note 1: t = n + 1 indicates conditions after next clock. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient T emperature Range 54 –55 125 IOH Output Current — High 54, 74 –0.4 mA IOL Output Current — Low 54 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 V Guaranteed Input LOW Voltage for All InputsVIL Input LOW Voltage 74 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth TableVOH Output HIGH Voltage 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VOL Output LOW Voltage 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH Current 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current 26 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.