74LS168

74LS168 NSC | Alldatasheet

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54LS168 Synchronous Bi-Directional BCD Decade Counter June 1989 54LS168 Synchronous Bi-Directional BCD Decade Counter General Description The 54LS168 is a fully synchronous 4-state up/down coun- ter featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to con- trol the direction of counting. It counts in the BCD (8421) sequence and all state changes, whether in counting or par- allel loading, are initiated by the LOW-to-HIGH transition of the clock. Connection Diagram Dual-In-Line Package TL/F/10207–1 Order Number 54LS168DMQB, 54LS168FMQB or 54LS168LMQB See NS Package Number E20A, J16A or W16A Logic Symbol TL/F/10207–2 VCC e Pin 16 GND e Pin 8 Pin Names Description CEP Count Enable Parallel Input (Active LOW) CET Count Enable Trickle Input (Active LOW) CP Clock Pulse Input (Active Rising Edge) P0–P3 Parallel Data Inputs PE Parallel Enable Input (Active LOW) U/D Up-Down Count Control Input Q0–Q3 Flip-Flop Outputs TC Terminal Count Output (Active LOW) C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range 54LS b55§Ct o a125§C Storage Temperature Range b65§Ct o a150§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter 54LS168 Units Min Nom Max VCC Supply Voltage 4.5 5 5.5 V VIH High Level Input Voltage 2 V VIL Low Level Input Voltage 0.7 V IOH High Level Output Current b0.4 mA IOL Low Level Output Current 4 mA TA Free Air Operating Temperature b55 125 §C ts (H) Setup Time HIGH or LOW 15 nsts (L) P n, CEP or CET to CP 15 th (H) Hold Time HIGH or LOW 5 nsth (L) P n, CEP or CET to CP 5 ts (H) Setup Time HIGH or LOW 20 nsts (L) PE to CP 20 th (H) Hold Time HIGH or LOW 0 nsth (L) PE to CP 0 ts (H) Setup Time HIGH or LOW 25 nsts (L) U/D to CP 25 th (H) Hold Time HIGH or LOW 0 nsth (L) U/D to CP 0 tw (H) CP Pulse Width HIGH or LOW 20 nstw (L) 20

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units(Note 1) VI Input Clamp Voltage V CC e Min, I I eb 18 mA b1.5 V VOH High Level Output Voltage V CC e Min, I OH e Max, 2.5 VVIL e Max, V IH e Min VOL Low Level Output Voltage V CC e Min, I OL e Max, 0.4 VVIH e Min, V IL e Max II Input Current @ Max V CC e Max, V I e 10.0V 0.1 mAInput Voltage IIH High Level Input Current V CC e Max, V I e 2.7V Inputs 20 mA CET 40 IIL Low Level Input Current V CC e Max, V I e 0.5V Data b0.5 b400 CP, PE , U/D , CEP b30 b400 mA CET b60 b800 IOS Short Circuit Output Current V CC e Max (Note 2) b20 b100 mA ICC Supply Current V CC e Max (Note 3) 34 mA Note 1: All typicals are at V CC e 5V, T A e 25§C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open and all inputs grounded. Switching Characteristics VCC ea 5.0V, T A ea 25§C (See Section 1 for test waveforms and output load) 54LS168 Symbol Parameter C L e 15 pF Units Min Max fMax Maximum Clock Frequency 25 MHz tPLH Propagation Delay 20 nstPHL CP to Q n 20 tPLH Propagation Delay 30 nstPHL CP to TC 30 tPLH Propagation Delay 15 nstPHL CET to TC 20 tPLH Propagation Delay 25 nstPHL U/D to TC 25

The ’LS168 uses edge-triggered D-type flip-flops and has no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load opera- tion takes precedence over the other operations, as indicat- ed in the Mode Select Table. When PE is LOW, the data on the P0–P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH. The U/D input then determines the direction of counting. The Termi- nal Count (TC ) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the COUNT DOWN mode or reaches 9 in the COUNT UP mode. The TC output state is not a function of the Count Enable Parallel (CEP ) input level. The TC output of the ’LS168 decade counter can also be LOW in the illegal states 11, 13 and 15, which can occur when power is turned on or via parallel loading. If an illegal state occurs, the ’LS168 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip- flop states, there exists the possibility of decoding spikes on TC . For this reason the use of TC as a clock signal is not recommended (see logic equation below). 1. Count Enable e CEP # CET # PE 2. Up: TC e Q0 # Q3 # (U/D) # CET 3. Down: TC e Q0 # Q1 # Q2 # Q3 # (U/D) # CET ’LS168 Mode Select Table PE CEP CET U/D Action on Rising Clock Edge L X X X Load (P nxQn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial State Diagram TL/F/10207–3 Logic Diagram TL/F/10207–4

Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS168LMQB 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS168DMQB

54LS168 Synchronous Bi-Directional BCD Decade Counter Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS168FMQB LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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