SN74LS122 ONSEMI | Alldatasheet
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Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6
1 Publication Order Number:
/C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0050/C0050 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0050/C0051 /C0082/C0101/C0116/C0114/C0105/C0103/C0103/C0101/C0114/C0097/C0098/C0108/C0101 /C0077/C0111/C0110/C0111/C0115/C0116/C0097/C0098/C0108/C0101 /C0077/C0117/C0108/C0116/C0105/C0118/C0105/C0098/C0114/C0097/C0116/C0111/C0114/C0115 These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear.
- Overriding Clear Terminates Output Pulse
- Compensated for VCC and Temperature Variations
- DC Triggered from Active-High or Active-Low Gated Logic Inputs
- Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
- Internal Timing Resistors on LS122 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.75 5.0 5.25 V TA Operating Ambient Temperature Range 0 25 70 °C IOH Output Current – High –0.4 mA IOL Output Current – Low 8.0 mA R ext External Timing Resistance5.0 260 k/C0087 C ext External Capacitance No Restriction R ext/Cext Wiring Capacitance at R ext/Cext Terminal 50 pF LOW POWER SCHOTTKY Device Package Shipping
ORDERING INFORMATION
http://onsemi.com PLASTIC N SUFFIX CASE 646 SOIC D SUFFIX CASE 751B PLASTIC N SUFFIX CASE 648 SN74LS122N 14 Pin DIP 2000 Units/Box SN74LS122D 14 Pin 2500/Tape & Reel
2000 Units/Box
2500/Tape & Reel
http://onsemi.com SN74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4) SN74LS123 (TOP VIEW) (SEE NOTES 1 THRU 4) NOTES: 1. An external timing capacitor may be connected between Cext and Rext/Cext (positive). 2. To use the internal timing resistor of the LS122, connect Rint to VCC. 3. For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited. 4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC. 14 13 12 11 10 9 123456 V CC Rext/ Cext NC C ext NC R int Q A1 A2 B1 B2 CLR Q GND CLR Q Q Rint Rext/ Cext Cext 1R ext/ Cext 14 13 12 11 10 9 12345 6 7 16 15 VCC 1Q 2Q 2B CLR 2A 1B 1 CLR 1Q 2Q 2 Cext GND Q Q Q Q CLR CLR NC — NO INTERNAL CONNECTION.
http://onsemi.com LS122 FUNCTIONAL TABLE INPUTS OUTPUTS CLEAR A1 A2 B1 B2 Q Q L X X X X L H X H HXX L H X X XLX L H X X XXL L H H L X ↑ H H L XH ↑ H X L ↑ H H X LH ↑ H H ↓ HH H ↓ ↓ HH H ↓ HHH ↑ L XHH ↑ X L H H LS123 FUNCTIONAL TABLE INPUTS OUTPUTS CLEAR A B Q Q L X X L H X H XL H X X LL H H L ↑ H ↓ H ↑ L H TYPICAL APPLICATION DATA The output pulse tW is a function of the external components, Cext and Rext or Cext and Rint on the LS122. For values of Cext ≥ 1000 pF, the output pulse at VCC = 5.0 V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by tW = K Rext Cext where K is nominally 0.45 If Cext is on pF and Rext is in kΩ then tW is in nanoseconds. The Cext terminal of the LS122 and LS123 is an internal connection to ground, however for the best system performance C ext should be hard-wired to ground. Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of inductance between the R ext/Cext junction and the Rext/Cext pin. Good groundplane and adequate bypassing should be designed into the system for optimum performance to ensure that no false triggering occurs. It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123, but not on the LS221. Therefore, if C ext is hard-wired externally to ground, substitution of a LS221 onto a LS123 socket will cause the LS221 to become non-functional. The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123. To find the value of K for C ext ≥ 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value of K to change, as can the temperature of the LS123, LS122. Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC and VRC . If VCC is tied to VRC , Figure 7 shows how K will vary with VCC and temperature. Remember, the changes in R ext and C ext with temperature are not calculated and included in the graph. As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K, the change in K with respect to Rext is negligible. If Cext ≤ 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. Figure 9 shows how K will change for C ext ≤ 1000 pF if VCC and VRC are connected to the same power supply. The pulse width tW in nanoseconds is approximated by tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ ) Cext + 11.6 Rext In order to trim the output pulse width, it is necessary to include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept as close to the monostable as possible. Retriggering of the part, as shown in Figure 3, must not occur before Cext is discharged or the retrigger pulse will not have any effect. The discharge time of Cext in nanoseconds is guaranteed to be less than 0.22 Cext (pF) and is typically 0.05 Cext (pF). For the smallest possible deviation in output pulse widths from various devices, it is suggested that Cext be kept ≥ 1000 pF.
http://onsemi.com WAVEFORMS EXTENDING PULSE WIDTH OVERRIDING THE OUTPUT PULSE B INPUT Q OUTPUT B INPUT CLEAR INPUT CLEAR PULSE Q OUTPUT OUTPUT WITHOUT CLEAR PULSE RETRIGGER PULSE (See Application Data) OUTPUT WITHOUT RETRIGGERtW
http://onsemi.com DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VO Output LOW Voltage 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, VIN =V ILor VIHVOL O utput LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table I Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V IIH Input HIGH C urrent 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current LS122 11 mA VCC = MAXICC Pow er Supply C urrent LS123 20 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions tPLH Propagation Delay, A to Q 23 33 nsPLH tPHL gy Propagation Delay, A to Q 32 45 ns C ext = 0 tPLH Propagation Delay, B to Q 23 44 ns ext C L = 15 pF PLH tPHL gy Propagation Delay, B to Q 34 56 ns R ext = 5.0 kΩ tPLH Propagation Delay, Clear to Q 28 45 ns ext R L = 2.0 kΩ PLH tPHL gy Propagation Delay, Clear to Q 20 27 ns tWm i n A or B to Q 116 200 ns C ext = 1000 pF, Rext = 10 kΩ , tW Q A to B to Q 4.0 4.5 5.0 µs ext ext C L = 15 pF, RL = 2.0 kΩ AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions tW Pulse Width 40 ns
http://onsemi.com PACKAGE DIMENSIONS 14 8 B A DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.715 0.770 18.16 18.80 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L N 0.015 0.039 0.38 1.01 /C0095/C0095 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. F HG D K C SEATING PLANE N –T– 14 PL M0.13 (0.005) L M J 0.290 0.310 7.37 7.87 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– –B– G P 7 PL 14 8 M0.25 (0.010) B M SBM0.25 (0.010) A ST –T– FR X 45 SEATING PLANE D 14 PL K C JM /C0095 DIM MIN MAX MIN MAX INCHESMILLIMETERS A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F N SUFFIX PLASTIC PACKAGE CASE 646–06 ISSUE M
http://onsemi.com PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– B F C S H G D J L M 16 PL SEATING 916 K PLANE–T– MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 /C0095/C0095/C0095/C0095 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45/C0095 G
8 PLP–B–
–A– M0.25 (0.010) B S –T– D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095
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