74LS00N | DigiCamel IC Datasheet

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/C0083/C0078/C0053/C0052/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0083/C0048/C0048 /C0083/C0078/C0055/C0052/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0083/C0048/C0048 /C0081/C0085/C0065/C0068/C0082/C0085/C0080/C0076/C0069 /C0050/C0262/C0073/C0078/C0080/C0085/C0084 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0078/C0065/C0078/C0068 /C0071/C0065/C0084/C0069/C0083 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Package Options Include Plastic Small-Outline (D, NS, PS), Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs /C0068Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package SN5400 ...J PACKAGE SN54LS00, SN54S00 ...J O R W PACKAGE SN7400, SN74S00 . . . D, N, OR NS PACKAGE SN74LS00 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) GND V CC SN5400 ...W PACKAGE (TOP VIEW) V CC GND SN74LS00, SN74S00 ...P S PACKAGE (TOP VIEW) VCC GND 32 1 2 0 1 9 91 01 11 21 3 NC NC NC NC NC V GND NC SN54LS00, SN54S00 . . . FK PACKAGE (TOP VIEW) CC NC − No internal connection description/ordering information These devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A • B or Y = A + B in positive logic. Copyright  2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0078/C0053/C0052/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0083/C0048/C0048 /C0083/C0078/C0055/C0052/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0083/C0048/C0048 /C0081/C0085/C0065/C0068/C0082/C0085/C0080/C0076/C0069 /C0050/C0262/C0073/C0078/C0080/C0085/C0084 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0078/C0065/C0078/C0068 /C0071/C0065/C0084/C0069/C0083 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING SN7400N SN7400N PDIP − N Tube SN74LS00N SN74LS00NPDIP − N Tube SN74S00N SN74S00N Tube SN7400D 7400Tape and reel SN7400DR 7400 SOIC − D Tube SN74LS00D LS00SOIC − D Tape and reel SN74LS00DR LS00 0°C to 70°C Tube SN74S00D S00

0 C to 70C

Tape and reel SN74S00DR S00 SN7400NSR SN7400 SOP − NS Tape and reel SN74LS00NSR 74LS00SOP − NS Tape and reel SN74S00NSR 74S00 SOP − PS Tape and reel SN74LS00PSR LS00 SOP − PS Tape and reel SN74S00PSR S00 SSOP − DB Tape and reel SN74LS00DBR LS00 SNJ5400J SNJ5400J CDIP − J Tube SNJ54LS00J SNJ54LS00JCDIP − J Tube SNJ54S00J SNJ54S00J −55°C to 125°C SNJ5400W SNJ5400W −55°C to 125°C CFP − W Tube SNJ54LS00W SNJ54LS00WCFP − W Tube SNJ54S00W SNJ54S00W LCCC − FK Tube SNJ54LS00FK SNJ54LS00FK LCCC − FK Tube SNJ54S00FK SNJ54S00FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS OUTPUT A B OUTPUT Y H H L L XH X L H logic diagram, each gate (positive logic) A B Y

/C0083/C0078/C0053/C0052/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0083/C0048/C0048 /C0083/C0078/C0055/C0052/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0083/C0048/C0048 /C0081/C0085/C0065/C0068/C0082/C0085/C0080/C0076/C0069 /C0050/C0262/C0073/C0078/C0080/C0085/C0084 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0078/C0065/C0078/C0068 /C0071/C0065/C0084/C0069/C0083 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematic ’00 GND Y 130 Ω VCC 4 kΩ A 1.6 kΩ 1 kΩ B VCC Resistor values shown are nominal. Y GND 3 kΩ 4 kΩ 120 Ω8 kΩ20 kΩ 1.5 kΩ 12 kΩ A B 2.8 kΩ 900 Ω B A 500 Ω 250 Ω 3.5 kΩ ’LS00 ’S00 VCC Y GND 50 Ω

/C0083/C0078/C0053/C0052/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0083/C0048/C0048 /C0083/C0078/C0055/C0052/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0083/C0048/C0048 /C0081/C0085/C0065/C0068/C0082/C0085/C0080/C0076/C0069 /C0050/C0262/C0073/C0078/C0080/C0085/C0084 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0078/C0065/C0078/C0068 /C0071/C0065/C0084/C0069/C0083 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package termal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN5400 SN7400 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 16 16 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ SN5400 SN7400 UNITPARAMETER TEST CONDITIONS ‡ MIN TYP § MAX MIN TYP § MAX UNIT VIK VCC = MIN, II = −12 mA −1.5 −1.5 V VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V II VCC = MAX, VI = 5.5 V 1 1 mA IIH VCC = MAX, VI = 2.4 V 40 40 µA IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA IOS ¶ VCC = MAX −20 −55 −18 −55 mA ICCH VCC = MAX, VI = 0 V 4 8 4 8 mA ICCL VCC = MAX, VI = 4.5 V 12 22 12 22 mA ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § All typical values are at VCC = 5 V, TA = 25°C. ¶ Not more than one output should be shorted at a time.

/C0083/C0078/C0053/C0052/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0083/C0048/C0048 /C0083/C0078/C0055/C0052/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0083/C0048/C0048 /C0081/C0085/C0065/C0068/C0082/C0085/C0080/C0076/C0069 /C0050/C0262/C0073/C0078/C0080/C0085/C0084 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0078/C0065/C0078/C0068 /C0071/C0065/C0084/C0069/C0083 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS SN5400 SN7400 UNITPARAMETER (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT(INPUT) (OUTPUT) MIN TYP MAX tPLH A or B Y R L = 400 Ω, C L = 15 pF 11 22 ns tPHL A or B Y R L = 400 Ω, C L = 15 pF 7 15 ns recommended operating conditions (see Note 4) SN54LS00 SN74LS00 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 4 8 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † SN54LS00 SN74LS00 UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIK VCC = MIN, II = −18 mA −1.5 −1.5 V VOL VCC = MIN, VIH = 2 V IOL = 4 mA 0.25 0.4 0.25 0.4 VVOL VCC = MIN, VIH = 2 V IOL = 8mA 0.35 0.5 V II VCC = MAX, VI = 7 V 0.1 0.1 mA IIH VCC = MAX, VI = 2.7V 20 20 µA IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA IOS § VCC = MAX −20 −100 −20 −100 mA ICCH VCC = MAX, VI = 0 V 0.8 1.6 0.8 1.6 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS SN54LS00 SN74LS00 UNITPARAMETER (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT(INPUT) (OUTPUT) MIN TYP MAX tPLH A or B Y R L = 2 kΩ, C L = 15 pF 9 15 ns tPHL A or B Y R L = 2 kΩ, C L = 15 pF 10 15 ns

/C0083/C0078/C0053/C0052/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0053/C0052/C0083/C0048/C0048 /C0083/C0078/C0055/C0052/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0048/C0048/C0044 /C0083/C0078/C0055/C0052/C0083/C0048/C0048 /C0081/C0085/C0065/C0068/C0082/C0085/C0080/C0076/C0069 /C0050/C0262/C0073/C0078/C0080/C0085/C0084 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0078/C0065/C0078/C0068 /C0071/C0065/C0084/C0069/C0083 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 5) SN54S00 SN74S00 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −1 −1 mA IOL Low-level output current 20 20 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † SN54S00 SN74S00 UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIK VCC = MIN, II = −18 mA −1.2 −1.2 V VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V II VCC = MAX, VI = 5.5 V 1 1 mA IIH VCC = MAX, VI = 2.7 V 50 50 µA IIL VCC = MAX, VI = 0.5V −2 −2 mA IOS § VCC = MAX −40 −100 −40 −100 mA ICCH VCC = MAX, VI = 0 V 10 16 10 16 mA ICCL VCC = MAX, VI = 4.5 V 20 36 20 36 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS SN54S00 SN74S00 UNITPARAMETER (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT(INPUT) (OUTPUT) MIN TYP MAX tPLH A or B Y R L = 280 Ω, C L = 15 pF 3 4.5 ns tPHL A or B Y R L = 280 Ω, C L = 15 pF 3 5 ns tPLH A or B Y R L = 280 Ω, C L = 50 pF 4.5 ns tPHL A or B Y R L = 280 Ω, C L = 50 pF ns

NOTES: A. C L includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH , tPHL , tPHZ , and tPLZ ; S1 is open and S2 is closed for tPZH ; S1 is closed and S2 is open for tPZL . 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) JM38510/00104BCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC JM38510/00104BDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC JM38510/07001BCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC JM38510/07001BDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC JM38510/30001B2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC JM38510/30001BCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC JM38510/30001BDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC JM38510/30001SCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC JM38510/30001SDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC SN5400J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SN54LS00J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SN54S00J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SN7400D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN7400DR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN7400N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN7400N3 OBSOLETE PDIP N 14 None Call TI Call TI SN7400NSR ACTIVE SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74LS00D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74LS00DBLE OBSOLETE SSOP DB 14 None Call TI Call TI SN74LS00DBR ACTIVE SSOP DB 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74LS00DR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74LS00J OBSOLETE CDIP J 14 None Call TI Call TI SN74LS00N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74LS00NSR ACTIVE SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74LS00PSR ACTIVE SO PS 8 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74S00D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74S00DR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74S00N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74S00N3 OBSOLETE PDIP N 14 None Call TI Call TI SN74S00NSR ACTIVE SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74S00PSR ACTIVE SO PS 8 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SNJ5400J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SNJ5400W ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC SNJ5400WA OBSOLETE CFP WA 14 None Call TI Level-NC-NC-NC SNJ54LS00FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54LS00J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SNJ54LS00W ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC SNJ54S00FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54S00J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SNJ54S00W ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 2

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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Product Information

74LS00N specifications and overview.

Summary

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

Description

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

Source title 74LS00N Datasheet(PDF) - Texas Instruments

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