74LS

SN54-74LS669 ONSEMI | Alldatasheet

Document overview

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Technical content

The SN54/74LS669 is a synchronous 4-bit up/down counter. The LS669 is a 4-bit binary counter. For high speed counting applications, this presettable counter features an internal carry lookahead for cascading purposes. By clocking all flip-flops simultaneously so the outputs change coincident with each other (when instructed to do so by the count enable inputs and internal gating) synchronous operation is provided. This helps to eliminate output counting spikes, normally associated with asynchronous (ripple-clock) count- ers. The four master-slave flip-flops are triggered on the rising (positive-going) edge of the clock waveform by a buffered clock input. Circuitry of the load inputs allows loading with the carry-enable output of the cascaded counters. Because loading is synchronous, disabling of the counter by setting up a low level on the load input will cause the outputs to agree with the data inputs after the next clock pulse. Cascading counters for N-bit synchronous applications are provided by the carry look-ahead circuitry, without additional gating. Two count-enable inputs and a carry output help accomplish this function. Count-enable inputs (P and T) must both be low to count. The level of the up-down input determines the direction of the count. When the input level is low, the counter counts down, and when the input is high, the count is up. Input T is fed forward to enable the carry output. The carry output will now produce a low level output pulse with a duration ≈ equal to the high portion of the QA output when counting up and when counting down ≈ equal to the low portion of the QA output. This low level carry pulse may be utilized to enable successive cascaded stages. Regard- less of the level of the clock input, transitions at the P or T inputs are allowed. By diode-clamping all inputs, transmission line effects are minimized which allows simplification of system design. Any changes at control inputs (ENABLE P , ENABLE T, LOAD, UP/DOWN) will have no effect on the operating mode until clocking occurs because of the fully independant clock circuits. Whether enabled, disabled, loading or count- ing, the function of the counter is dictated entirely by the conditions meeting the stable setup and hold times.

• Programmable Look-Ahead Up/Down Binary/Decade Counters
• Fully Synchronous Operation for Counting and Programming
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading
• Fully Independent Clock Circuit
• Buffered Outputs CONNECTION DIAGRAM (TOP VIEW) 14 13 12 11 10 9 12345 6 7 16 15 VCC U/D RIPPLE CARRY OUTPUT Q A Q B Q C ENABLE TQ D LOAD CK A B C D ENABLE P GND UP/DOWN OUTPUTS CK A B C D ENABLE P LOAD ENABLE T RIPPLE CARRY OUTPUT Q A Q B Q C Q D DATA INPUTS SN54/74LS669 SYNCHRONOUS 4-BIT UP/DOWN COUNTER LOW POWER SCHOTTKY

ORDERING INFORMATION

(9) (7) (10) (1) (2) LOAD ENP ENT U/D CP DATA DATA DATA DATA RCO Q A Q B Q C Q D (15) P3P2P1P0 (3) (4) (5) (6) (RIPPLE CARRY OUTPUT) CP D CP D CP D CP D GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 –55 125 IOH Output Current — High 54, 74 –0.4 mA IOL Output Current — Low 54 4.0 8.0 mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Sb l P Limits Ui T C di iSymbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 V Guaranteed Input LOW Voltage forVIL Input LOW Voltage 74 0.8 V pg All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIHVOH O utput HIGH Voltage 74 2.7 3.5 V CC , OH , IN IH or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, VIN =V ILor VIHVOL O utput LOW Voltage 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table I I HIGH C Others 20 µA VCC = MAX V IN =27V IIH Input HIGH Current Enable T 40 µA VCC = MAX , VIN = 2.7 V IIH Input HIGH C urrent Others 0.1 mA VCC = MAX V IN =70V Enable T 0.2 mA VCC = MAX , VIN = 7.0 V IIL Input LOW Current Others –0.4 mA VCC = MAX V IN =04VIIL Input LOW C urrent Enable T –0.8 mA VCC = MAX , VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current 34 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Sb l P Limits Ui T C di iSymbol Parameter Min Typ Max Unit Test Conditions fMAX Maximum Clock Frequency 25 32 MHz C1 5 F tPLH tPHL Propagation Delay, Clock to RCO ns C1 5 F tPLH tPHL Propagation Delay, Clock to Any Q ns C L = 15 pF tPLH tPHL Enable to RCO 11 ns tPLH tPHL U/D to RCO 22 ns AC SETUP REQUIREMENTS (TA = 25°C) Sb l P Limits Ui T C di iSymbol Parameter Min Typ Max Unit Test Conditions tW Clock Pulse Width 20 ns V5 0 V ts Data Setup Time 20 ns V5 0 V ts Enable Setup Time 35 ns VCC =50V ts Load Setup Time 25 ns VCC = 5.0 V ts U/D Setup Time 30 ns th Hold Time, Any Input 0 ns

1.3 V1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 3 V 3 V 3 V 3 V 3 V 0 V 0 V 0 V 0 V 0 V th th th CLOCK INPUT LOAD INPUT A,B,C, and D ENABLE P or ENABLE T UP/DOWN INPUT DATA INPUTS 3 V 0 V 1.3 V VOL 1.3 V 1.3 V

1.3 VENABLE T

PARAMETER MEASUREMENT INFORMATION VOLTAGE WAVEFORMS ts ts ts ts ts ts th th tw(clock) tw(clock) tPHL tPLH VOH