74LCX112

74LCX112 ONSEMI | Alldatasheet

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© 2001 Fairchild Semiconductor Corporation DS012424 www.fairchildsemi.com June 1998 Revised February 2001 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description The LCX112 is a dual J-K flip-flop. Each flip-flop has inde- pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accom- plished by a low logic level on the corresponding input. LCX devices are designed for low voltage (3.3V or 2.5) operation with the added capability of interfacing to a 5V signal environment. The 74LCX112 is fabricated with advanced CMOS technol- ogy to achieve high speed operation while maintaining CMOS low power dissipation.

Features

■ 5V tolerant inputs ■ 2.3V–3.6V VCC specifications provided ■ 7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max ■ Power down high impedance inputs and outputs ■ ±24 mA output drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 2000V Ordering Code: Devices also available in T ape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Order Number Package Number Package Description 74LCX112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74LCX112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description J1, J2, K1, K2 Data Inputs CP 1, CP2 Clock Pulse Inputs (Active Falling Edge) C D1 , CD2 Direct Clear Inputs (Active LOW) SD1 , SD2 Direct Set Inputs (Active LOW) Q 1, Q2, Q1, Q2 Outputs

www.fairchildsemi.com 2 74LCX112 Truth Table (Each half) H(h) = HIGH Voltage Level L(l) = LOW Voltage Level X = Immaterial /c16 = HIGH-to-LOW Clock Transition Q O (Q O ) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram Inputs Outputs SD C D CP JKQ Q LHXXXHL HLXXXLH LLXXXHH HH /c16 hh Q O Q O HH /c16 lh L H HH /c16 hlH L HH /c16 ll Q O Q O HHHXX Q O Q O

3 www.fairchildsemi.com 74LCX112 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 3) Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom- mended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum rating must be observed. Note 3: Unused Inputs must be held HIGH or LOW. They may not float. Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +7.0 V VI DC Input Voltage −0.5 to +7.0 V VO DC Output Voltage −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 2) V IIK DC Input Diode Current −50 V I < GND mA IOK DC Output Diode Current −50 V O < GND mA+50 V O > VCC IO DC Output Source/Sink Current ±50 mA ICC DC Supple Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to 150 °C Symbol Parameter Min Max Units VCC Supply Voltage Operating 2.0 3.6 VData Retention 1.5 3.6 VI Input Voltage 05 .5V VO Output Voltage HIGH or LOW State 0 V CC V IOH /IOL Output Current VCC = 3.0V − 3.6V ±24 mAVCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 TA Free-Air Operating Temperature −40 85 °C ∆t/∆V Input Edge Rate, V IN = 0.8V−2.0V, VCC = 3.0V 0 10 ns/V Symbol Parameter Conditions VCC TA = 40°C to +85°C Units (V) Min Max VIH HIGH Level Input Voltage 2.3 − 2.7 1.7 V 2.7 − 3.6 2.0 VIL LOW Level Input Voltage 2.3 − 2.7 0.7 V 2.7 − 3.6 0.8 VOH HIGH Level Output Voltage I OH = −100µA2 .3 − 3.6 V CC - 0.2 0.7 V IOH = -8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 VOL LOW Level Output Voltage I OL = 100µA2 .3 − 3.6 0.6 IOL = 8mA 2.3 0.2 IOL = 12 mA 2.7 0.4 V IOL = 16 mA 3.0 0.4 IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ II ≤ 5.5V 2.3 − 3.6 ±5.0 µA IOFF Power-Off Leakage Current V I or VO = 5.5V 0 10 µA ICC Quiescent Supply Current V I = VCC or GND 2.3 − 3.6 10 µA 3.6V ≤ VI ≤ 5.5V 2.3 − 3.6 ±10 µA ∆ICC Increase in ICC per Input V IH = VCC −0.6V 2.3 − 3.6 500 µA

www.fairchildsemi.com 4 74LCX112 Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL ), or LOW-to-HIGH (tOSLH ). Dynamic Switching Characteristics Capacitance Symbol Parameters TA = 40°C to 85°C, RL = 500Ω Units C L=50 pF C L = 50 pF C L=30 pF Min Max Min Max Min Max fMAX Maximum Clock Frequency 150 150 150 MHz ns tPLH CP ns tS Setup Time 2.5 2.5 4.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width CP 3.3 3.3 4.0 ns tW Pulse Width (CD , SD ) 3.3 3.3 4.0 ns tREC Recovery Time 2.0 2.5 4.5 ns tOSHL Output to Output Skew 1.0 ns tOSLH (Note 4) 1.0 Symbol Parameter Conditions VCC TA = 25°C Units (V) Typical VOLP Quiet Output Dynamic Peak VOL C L = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V C L = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6 VOLV Quiet Output Dynamic Valley VOL C L = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 V C L = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6 Symbol Parameter Conditions Typical Units C IN Input Capacitance V CC = Open, VI = 0V or VCC 7p F C OUT Output Capacitance V CC = 3.3V, VI = 0V or VCC 8p F C PD Power Dissipation Capacitance V CC = 3.3V, VI = 0V or VCC , f = 10 MHz 25 pF

www.fairchildsemi.com 6 74LCX112 Schematic Diagram Generic for LCX Family

7 www.fairchildsemi.com 74LCX112 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

www.fairchildsemi.com 8 74LCX112 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

9 www.fairchildsemi.com 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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