74LCX00 STM | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 16

Technical content

Datasheet sections

  • 1 Logic symbols and I/O equivalent circuit
  • 2 Pin settings
  • 2.1 Pin connections
  • 2.2 Pin description
  • 2.3 Truth table
  • 3 Maximum ratings
  • 4 Electrical characteristics
  • 5 Test circuit
  • 6 Waveforms
  • 7 Package mechanical data
  • 8 Revision history

Features

■ 5 V tolerant inputs ■ High speed –t PD = 4.3 ns (max.) at VCC = 3 V ■ Power-down protection on inputs and outputs ■ Symmetrical output impedance –| I OH| = IOL = 24 mA (min.) at V CC = 3 V ■ PCI bus levels guaranteed at 24 mA ■ Balanced propagation delay –t PLH ≅ tPHL ■ Operating voltage range –V CC (opr.) = 2.0 V to 3.6 V ■ Pin and function compatible with 74 series 00 ■ Latch-up performance exceeds 500 mA (JESD 17) ■ ESD performance – HBM: 2000 V (MIL STD 883 method 3015) – MM: 200 V – CDM: 1000 V

Applications

■ Automotive ■ Industrial ■ Computer ■ Consumer

Description

The 74LCX00 device is a low-voltage CMOS quad dual input NAND gate manufactured with sub-micron silicon gate and double layer metal wiring C 2MOS technology. It is ideal for low-power and high-speed 3.3 V applications and can be interfaced to a 5 V signal environment for inputs. It has the same speed performance at 3.3 V as the 5 V AC/ACT family, combined with lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2 kV ESD immunity and transient excess voltage. SO-14TSSOP14 Table 1. Device summary

  1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC

Q001 and Q002 or equivalent.

1 Logic symbols and I/O equivalent circuit

Figure 1. IEC logic symbols Figure 2. Input and output equivalent circuit

2 Pin settings

2.1 Pin connections

Figure 3. Pin connections (top through view)

2.2 Pin description

2.3 Truth table

Table 2. Pin description

7 GND Ground (0 V)

14 V CC Positive supply voltage

Table 3. Truth table

3 Maximum ratings

rating conditions for extended periods may affect device reliability. Table 4. Absolute maximum ratings

  1. I O absolute maximum rating must be observed.

Table 5. Recommended operating conditions

  1. Truth table guaranteed: 1.5 V to 3.6 V.

4 Electrical characteristics

Table 6. DC specifications Table 7. Dynamic switching characteristics

  1. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to

HIGH. The remaining output is measured in the LOW state.

Table 8. AC electrical characteristics

  1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
  2. Parameter guaranteed by design.

Table 9. Capacitive characteristics

  1. C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the

can be obtained by the following equation. I CC(opr) = CPD x VCC x fIN + ICC/4 (per gate).

5 Test circuit

Figure 4. Test circuit RT = ZOUT of pulse generator (typically 50 Ω ).

6 Waveforms

Figure 5. Waveform - propagation delay (f = 1 MHz; 50% duty cycle)

Package mechanical data 74LCX00 10/16 Doc ID 4972 Rev 7

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Figure 6. SO-14 package outline Table 10. SO-14 package mechanical data

Figure 7. TSSOP14 package outline Table 11. TSSOP14 package mechanical data

Figure 8. Tape and reel SO-14 outline Table 12. Tape and reel SO-14 mechanical data

Figure 9. Tape and reel TSSOP14 outline Table 13. Tape and reel TSSOP14 mechanical data

8 Revision history

Table 14. Document revision history Updated Section 3: Maximum ratings (added cross-references). Removed “Operating temperature” from Table 5. Reformatted Section 7: Package mechanical data. Minor corrections throughout document.