DM54L74 NSC | Alldatasheet

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DM54L74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs June 1989 DM54L74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig- gered D flip-flops with complementary outputs. The informa- tion on the D input is accepted by the flip-flops on the posi- tive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is low or high without af- fecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Connection Diagram Dual-In-Line Package TL/F/6631–1 Order Number DM54L74J or DM54L74W See NS Package Number J14A or W14B Function Table Inputs Outputs PR CLR CLK D Q Q LH X X H L HL X X L H LL X X H * H* HH u HH L HH u LL H HH L X Q O QO H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level u e Positive-going transition. QO e The output logic level of Q before the indicated input conditions were established. * e This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs returned to their inactive (high) level. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 8V Input Voltage 5.5V Operating Free Air Temperature Range DM54L b55§Ct o a125§C Storage Temperature Range b65§Ct o a150§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter DM54L74 Units Min Nom Max VCC Supply Voltage 4.5 5 5.5 V VIH High Level Input Voltage 2 V VIL Low Level Input Voltage 0.7 V IOH High Level Output Current b0.2 mA IOL Low Level Output Current 2 mA fCLK Clock Frequency (Note 2) 0 6 MHz tW Pulse Width (Note 2) Clock High 75 Clock Low 75 ns Preset Low 75 Clear Low 75 tSU Input Setup Time (Note s1&2 ) 5 0 u ns tH Input Hold Time (Note s1&2 ) 1 5 u ns TA Free Air Operating Temperature b55 125 §C Note 1: The symbol ( u) indicates the rising edge of the clock pulse is used for reference. Note 2: TA e 25§C and V CC e 5V.

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units(Note 1) VOH High Level Output V CC e Min, I OH e Max 2.4 3.3 VVoltage V IL e Max, V IH e Min VOL Low Level Output V CC e Min, I OL e Max 0.15 0.3 VVoltage V IL e Max, V IH e Min II Input Current @ Max V CC e Max D 100 Input Voltage V I e 5.5V Clear 300 mA Preset 200 Clock 200 IIH High Level Input V CC e Max D 10 Current V I e 2.4V Clear 30 mA Preset 20 Clock 20 IIL Low Level Input V CC e Max D b0.18 Current V I e 0.3V Clear b0.36 mA Preset b0.18 Clock b0.36 IOS Short Circuit V CC e Max b3 b15 mAOutput Current ICC Supply Current V CC e Max (Note 2) 1.6 3 mA Note 1: All typicals are at V CC e 5V, T A e 25§C. Note 2: With all outputs open, I CC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded. Switching Characteristics at V CC e 5V and T A e 25§C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) RL e 4k X,C L e 50 pF UnitsTo (Output) Min Max fMAX Maximum Clock Frequency 6 MHz tPLH Propagation Delay Time Preset 60 nsLow to High Level Output to Q tPHL Propagation Delay Time Preset 120 nsHigh to Low Level Output to Q tPLH Propagation Delay Time Clear 60 nsLow to High Level Output to Q tPHL Propagation Delay Time Clear 120 nsHigh to Low Level Output to Q tPLH Propagation Delay Time Clock to 10 90 nsLow to High Level Output Q or Q tPHL Propagation Delay Time Clock to 10 120 nsHigh to Low Level Output Q or Q

DM54L74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs Physical Dimensions inches (millimeters) 14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54L74J 14-Lead Ceramic Flat Package (W) Order Number DM54L74W LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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