74L05

MAX191 MAXIM | Alldatasheet

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Technical content

The MAX191 is a monolithic, CMOS, 12-bit analog-to- digital converter (ADC) featuring differential inputs, track/hold (T/H), internal voltage reference, internal or external clock, and parallel or serial µP interface. The MAX191 has a 7.5µs conversion time, a 2µs acquisition time, and a guaranteed 100ksps sample rate. The MAX191 operates from a single +5V supply or from dual ±5V supplies, allowing ground-referenced bipolar input signals. The device features a logic power-down input, which reduces the 3mA V DD supply current to 50µA max, including the internal-reference current. Decoupling capacitors are the only external compo- nents needed for the power supply and reference. This ADC operates with either an external reference, or an internal reference that features an adjustment input for trimming system gain errors. The MAX191 provides three interface modes: two 8-bit parallel modes, and a serial interface mode that is com- patible with SPI TM, QSPITM, and MICROWIRE TM serial- interface standards. Battery-Powered Data Logging PC Pen Digitizers High-Accuracy Process Control Electromechanical Systems Data-Acquisition Boards for PCs Automatic Testing Systems Telecommunications Digital Signal Processing (DSP) ' 12-Bit Resolution, 1/2LSB Linearity ' +5V or ±5V Operation ' Built-In Track/Hold ' Internal Reference with Adjustment Capability ' Low Power: 3mA Operating Mode 20µA Power-Down Mode ' 100ksps Tested Sampling Rate ' Serial and 8-Bit Parallel µP Interface ' 24-Pin Narrow DIP and Wide SO Packages MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down VDD CLK/SCLK PAR HBENAIN- AIN+ VSS PD TOP VIEW CS RD D7/DOUT D6/SCLKOUTBIP AGND REFADJ VREF D5/SSTRB D3/D11 D2/D10DGND D1/D9 D0/D8 BUSY DIP/SO MAX191 Pin Configuration 2.46V REF IN REF OUT 12-BIT SAR ADC OSC CONTROL LOGIC 3-STATE OUTPUT 8-BIT BUS AND SERIAL I/O D7/DOUT D6/SCLKOUT D5/SSTRB D3/D11 D2/D10 D1/D9 D0/D8 CS RD BUSY HBEN REFADJ VREF AIN + AIN - 24 23 VDD CLK/SCLK 71 2 PD 1 22 8 AGND DGND PAR BIP MAX191 VSS Functional Diagram 19-4506; Rev 4; 2/97 PART TEMP. RANGE PIN-PACKAGE MAX191ACNG 0°C to +70°C

24 Narrow Plastic DIP

24 Wide SO

±1/2 ±1/2 ERROR (LSB) 0°C to +70°C 0°C to +70°C MAX191BCWG 0°C to +70°C 24 Wide SO ±1 MAX191BC/D Dice* ±10°C to +70°C MAX191AENG -40°C to +85°C 24 Narrow Plastic DIP±1/2 MAX191BENG -40°C to +85°C 24 Narrow Plastic DIP ±1 MAX191AEWG -40°C to +85°C 24 Wide SO ±1/2 MAX191AMRG 24 Narrow CERDIP±1/2 MAX191BMRG 24 Narrow CERDIP ±1 -55°C to +125°C -55°C to +125°C MAX191BEWG -40°C to +85°C 24 Wide SO ±1 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. EVALUATION KIT MANUAL FOLLOWS DATA SHEET * Dice are specified at TA = +25°C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883.

Ordering Information

Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode—external, synchronous operation, Figure 6, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Continuous Power Dissipation (TA = +70° C) Operating Temperature Ranges PARAMETER CONDITIONS MIN TYP MAX UNITS Offset Error MAX191B ±2 LSB MAX191A ±1 Differential Nonlinearity No missing codes over temperature ±1 LSB Integral Nonlinearity MAX191B ±1 LSB MAX191A ±2 Gain Error (Note 3) MAX191B ±3 LSB Resolution 12 Bits MAX191A ±1/2 Gain-Error Tempco (Note 4) Excludes internal-reference drift ±0.2 ppm/° C 1kHz input signal, TA = +25° C 70 dB 1kHz input signal, TA = +25° C -80 dB Spurious-Free Dynamic Range 1kHz input signal, TA = +25° C 80 dB Synchronous CLK (12 to 13 CLKs)Conversion Time (Note 5) Internal CLK, CL = 120pF 6 12 18 µs Track/Hold Acquisition Time 2 µs Aperture Delay 25 ns Aperture Jitter 50 ps 0.1 1.6 MHz Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion (up to the 5th Harmonic) External Clock Frequency Range (Note 6) SYMBOL DNL INL SINAD SFDR THD tCONV fCLK 7.50 8.125 DC ACCURACY (Note 2) DYNAMIC ACCURACY (sample rate = 100kHz, VIN = 4Vp-p) CONVERSION RATE

Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode—external, synchronous operation, Figure 6, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PD External Leakage for Float State (Note 12) VFLT V2.8Reference compensation mode—externalPD Floating-State Voltage nA±100Maximum current allowed for “floating state” IIN µA±20PD = 0V to VDD (Note 11)PD Input Current ±200PD = high/floatIIN µA±0.1PD = low Input Current CLK CIN pF10Input Capacitance (Note 6) VIL V0.5PD Input Low Voltage VIH V4.5PD Input High Voltage IIN µA±10VIN = 0V to VDDInput Current VIH V2.4CS, RD, CLK, HBEN, PAR, BIPInput High Voltage VIL V0.8CS, RD, CLK, HBEN, PAR, BIPInput Low Voltage kΩ5 10External-reference modeInput Resistance mA1External-reference = 5VInput Current REFADJ Input Adjustment Range (Note 10) V2.5 5.0External-reference modeInput Voltage Range µA60REFADJ = 5VREFADJ Input Current V2.4REFADJ Output Voltage V4.5REFADJ Disable Threshold mV-60 30 µV±300VDD = ±5%, VSS = ±5%Power-Supply Rejection µF4.7Reference compensation mode—externalCapacitive Load Required mA18Output Short-Circuit Current mV4TA = +25° C, IOUT = 0mA to 2mALoad Regulation SYMBOL UNITSMIN TYP MAXCONDITIONSPARAMETER Input Voltage Range (Note 7) VVSS VDD Input Capacitance (Note 6) pF45 80 Input Leakage Current µA±10VIN = VSS to VDD 50MAX191_C VREF Output Voltage V4.076 4.096 4.116TA = +25° C Small-Signal Bandwidth MHz2 60MAX191_E Output Current Capability (Note 9) mA2TA = +25° C VREF Output Tempco (Note 8) ppm/° C 80MAX191_M ANALOG INPUT INTERNAL REFERENCE REFERENCE INPUT LOGIC INPUTS

Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode—external, synchronous operation, Figure 6, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER RD Pulse Width CONDITIONS 150 UNITSMAX191C/E MIN TYP MAX 150 ns 140 140 MAX191M MIN TYP MAX 150 160 160 CL = 100pF 120 ns 80 100 ns120t8 110 120100 nst7 100 12080 nst6 0 0CS to RD Hold Time 0 nst5 SYMBOL RD to BUSY Delay CS to RD Setup Time 0 ns CL = 50pF 120 ns TIMING CHARACTERISTICS (Figures 6–10) (VDD =5V ±5%, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14) Aperture Delay Jitter < 50ps 25 nst12 2 22 200 200200 nst10 HBEN to RD Hold Time 0 0 ns0t9 Data Access Time (Note 15) Data Setup Time After BUSY (Note 15) Bus-Relinquish Time (Note 16) HBEN to RD Setup Time Delay Between Read Operations (Note 6) 200 230 ns260t13CLK to BUSY Delay (Note 6) 100 130 ns150t14 SCLKOUT to SSTRB Rise Delay SCLKOUT to SSTRB Fall Delay 100 130 ns150t15 TA = +25°C MIN TYP MAX µst11Delay Between Conversions VSS V-5.25 0Negative Supply Voltage IDD VDD VOL VOH COUT IL µA20 50 V0.4IOUT = 1.6mA mA3 5 V4.75 5.25Positive Supply Voltage Output Low Voltage SYMBOL PD = low PD = high/float PD = low LSB±1/2FS change, VSS = -5V ±5%Negative Supply Rejection (Note 13) LSB±1/2FS change, VDD = 5V ±5%Positive Supply Rejection (Note 13) ISS µA V pF 4.0IOUT = -200µAOutput High Voltage 1 20 CS = RD = VDD, AIN = 5V, D0/D8–D7/ DOUT = 0V or VDD, HBEN = PAR = BIP = 0V or V DD Positive Supply Current PD = high/float Three-State Output Capacitance (Note 6) 20 100 µA Negative Supply Current UNITS ±10D0/D8-D7/DOUT MIN TYP MAXCONDITIONS Three-State Leakage Current PARAMETER LOGIC OUTPUTS POWER REQUIREMENTS

Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down PARAMETER SCLK to SCLKOUT Delay CONDITIONS 160 UNITS ns CS to DOUT Three-State 100 ns SYMBOL CS or RD Setup Time CS or RD Hold Time ns 150 ns t20 t19 t17 t16 TIMING CHARACTERISTICS (Figures 6–10) (continued) (VDD =5V ±5%, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14) MAX191C/E MIN TYP MAX 180 110 150 MAX191M MIN TYP MAX 200 120 150 310 350SCLK to SSTRB Delay 260 nst23 260 280SCLK to DOUT Delay 240 nst22 130SCLKOUT to DOUT Delay 100 nst21 150 Note 1: Performance at power-supply tolerance limits guaranteed by power-supply rejection test. Note 2: VDD = 5V, VSS = 0V, FS = VREF. Note 3: FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB. Note 4: Gain-Error Tempco = ∆GE is the gain-error change from TA = +25° C to TMIN or TMAX. Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. Note 6: Guaranteed by design, not production tested. Note 7: AIN+, AIN- must not exceed supplies for specified accuracy. Note 8: VREF TC = ∆T, where ∆VREF is reference-voltage change from TA = +25° C to TMIN or TMAX. Note 9: Output current should not change during conversion. This current is in addition to the current required by the internal DAC. Note 10: REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V. This will typically result in a 1.7 times larger change in the REF output (Figure 19a). Note 11: This current is included in the PD supply current specification. Note 12: Floating the PD pin guarantees external compensation mode. Note 13: VREF = 4.096V, external reference. Note 14: All input control signals are specified with tr = tf = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Note 15: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 16: t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. TA = +25°C MIN TYP MAX

Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 0.01 0.1 10 CLOCK FREQUENCY vs. TIMING CAPACITOR 0.1 TIMING CAPACITOR (nF) CLOCK FREQUENCY (MHz) SEE FIGURE 5 TA = +25˚C GR191-A -60 150 TEMPERATURE (°C) SUPPLY CURRENT (µA) 120 0 60 -30 30 90 VDD = +5V VSS = -5V PD = 0V ISS IDD POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE GR191-B -60 150 TEMPERATURE (°C) ISS (µA) 120 0 60 -30 30 90 NEGATIVE SUPPLY CURRENT vs. TEMPERATURE GR191-C 3.5 0.5 -60 -30 30 60 1.0 2.0 TEMPERATURE (°C) IDD (mA) 1.5 90 120 150 2.5 3.0 POSITIVE SUPPLY CURRENT vs. TEMPERATURE GR191-D -140 0 2 6 1kHz FFT PLOT -100 -40 GR191-E FREQUENCY (kHz) SIGNAL AMPLITUDE (dB) -80 1 3 5 -120 -60 -20 fIN = 1kHz fS = 100kHz SNR = 72dB T A = +25˚C -94.3dB -96.1dB-98.0dB -93.8dB -140 0 10 30 40 10kHz FFT PLOT -100 -60 GR191-F FREQUENCY (kHz) SIGNAL AMPLITUDE (dB) -80 -120 -40 -20 fIN = 10kHz fS = 100kHz SNR = 71.2dB T A = +25˚C 5 20 25 35 -86.0dB -90.8dB

Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Pin Description Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal oscillator. High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs onto the data bus. In serial mode, HBEN = low enables SCLK OUT to operate during the conversion only, HBEN = high enables SCLKOUT to operate continuously, provided CS is low. Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLKOUT, SSTRB, and DOUT into a high-impedance state. Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLKOUT and SSTRB when CS is low. RD = high forces SCLKOUT and SSTRB into a high-impedance state. D6/SCLKOUT

7 Analog GroundAGND

24 Positive Supply, +5V ±5%VDD

23 CLK/SCLK

22 Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode.PAR

21 HBEN

18 Three-State Data Output/Data Output in serial modeD7/DOUT

13 Three-State Data OutputsD2/D10

14 Three-State Data Outputs: MSB = D11D3/D11

15 Three-State Data OutputD4

16 Three-State Data Output/Serial Strobe Output in serial modeD5/SSTRB

17 Three-State Data Output/Serial Clock Output in serial mode

10 Three-State Data Outputs: LSB = D0D0/D8

11 Three-State Data OutputsD1/D9

12 Digital GroundDGND

Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic high selects normal operation, internal-reference compensation mode. An open-circuit condition selects normal operation, external-reference compensation mode. PIN BUSY Output is low during a conversion.BUSY BIP = low selects unipolar mode BIP = high selects bipolar mode (see Gain and Offset Adjustment section)BIP Reference Adjust. Connect to VDD to use an extended reference at VREF.REFADJ Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to V DD.VREF Analog Input Return. Pseudo-differential (see Gain and Offset Adjustment section).AIN- Sampled Analog InputAIN+ Negative Supply, 0V to -5.25VVSS PD FUNCTIONNAME

Figure 9. ROM Mode Timing, Reading Data without Starting a Conversion

12 SCLK CYCLES

Figure 10. Serial-Interface Mode Timing Diagram (RD = low)

Table 1. Data-Bus Output, CS = RD = Low Note: D7/DOUT–D0/D8 are the ADC data output pins. D11–D0 are the 12-bit conversion results. D11 is the MSB. DOUT = Three-state data output. Data output in serial mode. OUT = Three-state data output. Clock output in serial mode. SSTRB = Three-state data output. Strobe output in serial mode. Table 2. Slow-Memory Mode, 2-Byte Read Data-Bus Status Table 3. ROM Mode, 2-Byte Read Data-Bus Status Table 4. ROM Mode, 2-Byte Read Data-Bus Status without Starting a Conversion Cycle

NOTE: USE SSTRB TO GATE PARALLEL DATA TRANSFER FROM SHIFT REGISTER, OR TO CLEAR SHIFT REGISTERS IF DESIRED. Figure 11. Simple Serial-to-Parallel Interface

0.01µF and 10 µF bypass capacitors. Minimize capaci - tor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10 Ω resistor can be connected as a lowpass filter to filter out supply noise (Figure 23). High-speed sampling capability and throughput make the MAX191 ideal for wideband signal processing. To support these and other related applications, Fast Fourier Transform (FFT) test techniques guarantee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this involves applying a low-distortion sine wave to the ADC input and recording the digital conversion results for a speci - fied time. The data is then analyzed using an FFT algo - rithm, which determines its spectral content. Conversion errors are then seen as spectral elements outside the fundamental input frequency. FFT plots are shown in the Typical Operating Characteristics. ADCs have traditionally been evaluated by specifica - tions such as zero and full-scale error, integral nonlin - earity (INL), and differential nonlinearity (DNL). Such parameters are widely accepted for specifying perfor - mance with DC and slowly varying signals, but are less useful in signal-processing applications where the ADC’s impact on the system transfer function is the main concern. The significance of various DC errors does not translate well to the dynamic case, so different tests are required. Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other A/D output signals, except signal harmonics. Signal-to-Noise + Distortion ratio (SINAD) is the same as the SNR, but includes sig - nal harmonics. The theoretical minimum A/D noise is caused by quan - tization error and is a direct result of the ADC’s resolu - tion: SNR = (6.02n + 1.76) dB, where n is the number of bits of resolution. 74dB is the SNR of a perfect 12-bit ADC. By transposing the equation that converts resolution to SNR we can compute the effective resolution or the “effective number of bits” the ADC provides from the measured SNR: Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequen - cy band above DC and below one-half the sample rate) to the fundamental itself. This expressed as: THD = 20log where V1 is the fundamental RMS amplitude and V 2 to Vn are the amplitudes of the 2nd through nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range is the ratio of the funda - mental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually this peak occurs at some harmonic of the input fre - quency. But if the ADC is exceptionally linear, it can occur at a random peak in the ADC’s noise floor. Opto-Isolated A/D Interface Many industrial applications require isolation to prevent excessive current flow where ground disparities exist between the ADC and the rest of the system. In Figure 24, a MAX250 and four 6N136 opto-couplers create an Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down

Figure 24. Isolated Data-Acquisition Circuit

Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down HBEN BIP VREF REFADJ AGND 0.198" (5.0292mm) 0.142" (3.6065mm) BUSY D0/D8 D1/D9 DGND D3/D11 D5/SSTRB D2/D10 CS RD D7/DOUT D6/SCLK OUT AIN- AIN+ AGND PD VDD CLK/SCLK PAR SUBSTRATE CONNECTED TO VDD PDIPN.EPS