SN74HSTL16918_08 TI1 | Alldatasheet
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9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Member of the Texas Instruments Widebus Family /C0068Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) /C0068Latch-Up Performance Exceeds 250 mA Per JESD 17 /C0068Packaged in Plastic Thin Shrink Small-Outline Package
description
This 9-bit to 18-bit D-type latch is designed for 3.15-V to 3.45-V V CC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels. The SN74HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE ) input. Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is low, the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken high, the Q outputs are latched at the levels set up at the D inputs. The SN74HSTL16918 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUT LE D Q L H H L LL H X Q 0† † Output level before the indicated steady-state input conditions were established Copyright 1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. DGG PACKAGE (TOP VIEW) 2Q1 1Q1 GND V CC GND 1LE GND VREF GND 2LE GND V CC GND 2Q9 1Q9 V CC VCC 1Q2 2Q2 GND 1Q3 2Q3 V CC 1Q4 2Q4 GND 1Q5 2Q5 GND 1Q6 2Q6 V CC 1Q7 2Q7 GND 1Q8 2Q8 V CC VCC
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999
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logic diagram (positive logic) 1Q1 2Q1 1LE 2LE To Eight Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC . 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) MIN NOM MAX UNIT VCC Supply voltage 3.15 3.45 V VREF Reference voltage 0.68 0.75 0.9 V VI Input voltage 0 1.5 V VIH AC high-level input voltage All inputs VREF +200 mV V VIL AC low-level input voltage All inputs VREF –200 mV V VIH DC high-level input voltage All inputs VREF +100 mV V VIL DC low-level input voltage All inputs VREF –100 mV V IOH High-level output current –24 mA IOL Low-level output current 24 mA TA Operating free-air temperature 0 70 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 3.15 V, II = –18 mA –1.2 V VOH VCC = 3.15 V, IOH = –24 mA 2.4 V VOL VCC = 3.15 V, IOL = 24 mA 0.5 V Control inputs VI = 0 or 1.5 V ±5 II Data inputs VCC = 3.45 V VI = 0 or 1.5 V ±5 µA VREF VREF = 0.68 V or 0.9 V 90 ICC VCC = 3.45 V, VI = 0 or 1.5 V 50 100 mA C i Control inputs VCC = 0 or 3.3 V, VI = 0 or 3.3 V 2 pFC i Data inputs VCC = 0 or 3.3 V, VI = 0 or 3.3 V 2.5 pF C o Outputs VCC = 0, VO = 0 4 pF † All typical values are at VCC = 3.3 V, TA = 25°C. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.15 V UNIT MIN MAX tw Pulse duration, LE low 3 ns tsu Setup time, D before LE↑ 2 ns th Hold time D after LE↑ 1 ns tldr‡ Data race condition time D after LE↓ 0 ns ‡ This is the maximum time after LE switches low that the data input can return to the latched state from the opposite state without producing a glitch on the output. switching characteristics over recommended operating free-air temperature range, VREF = 0.75 V PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.15 V UNIT(INPUT) (OUTPUT) MIN MAX t d D Q 1.9 3.4 nstpd LE Q 1.9 4.2 ns simultaneous switching characteristics over recommended operating free-air temperature range, VREF = 0.75 V§ PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.15 V UNIT(INPUT) (OUTPUT) MIN MAX t d D Q 1.9 4.4 nstpd LE Q 1.9 5.2 ns § All outputs switching
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NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 1 ns, tf ≤ 1 ns. C. The outputs are measured one at a time with one transition per measurement. D. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74HSTL16918DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HSTL16918DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HSTL16918DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97
48 PINS SHOWN
0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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