74HC595 NEXPERIA | Alldatasheet

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74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 11 — 10 September 2021 Product data sheet 1. General description The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • 8-bit serial input
  • 8-bit serial or parallel output
  • Storage register with 3-state outputs
  • Shift register with direct clear
  • 100 MHz (typical) shift out frequency
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
  • JESD8C (2.7 V to 3.6 V)
  • JESD7A (2.0 V to 6.0 V)
  • Input levels:
  • For 74HC595: CMOS level
  • For 74HCT595: TTL level
  • ESD protection:
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Applications
  • Serial-to-parallel data conversion
  • Remote control holding register

Table 1. Ordering information

13 EN3

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state STAGE 0 STAGES 1 TO 6 STAGE 7 FF0 D CP Q R LATCH D CP Q FF7 D CP Q R LATCH D CP Q mna555 D Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7S DS STCP SHCP OE MR Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 74HC595 74HCT595 Q1 VCC Q2 Q0 Q3 DS Q4 OE Q5 STCP Q6 SHCP Q7 MR GND Q7S 001aao242 Fig. 5. Pin configuration for SOT109-1 (SO16) and SOT403-1 (TSSOP16) 001aao243 74HC595 74HCT595 Q7 MR Q6 SHCP Q5 STCP Q4 OE Q3 DS Q2 Q0 GND Q7S VCC Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area GND(1) (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Fig. 6. Pin configuration for SOT763-1 (DHVQFN16) 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 3 / 21

the solder land should remain floating or connected to GND. Table 2. Pin description

Table 3. Function table X = don’t care; NC = no change; Z = high-impedance OFF-state. (internal Q6S) appears on the serial output (Q7S).

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C.

  1. Recommended operating conditions

Table 5. Recommended operating conditions

Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions Min Typ Max Min Max Unit 74HCT595 VIH HIGH-level input voltage VIL LOW-level input voltage VI = VIH or VIL; VCC = 4.5 V all outputs IO = -20 μA 4.4 4.5 - 4.4 - V Q7S output IO = -4 mA 3.84 4.32 - 3.7 - V Qn bus driver outputs VOH HIGH-level output voltage IO = -6 mA 3.7 4.32 - 3.7 - V VI = VIH or VIL; VCC = 4.5 V all outputs IO = 20 μA - 0 0.1 - 0.1 V Q7S output IO = 4.0 mA - 0.15 0.33 - 0.4 V Qn bus driver outputs VOL LOW-level output voltage IO = 6.0 mA - 0.16 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 - ±1.0 μA IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND - - ±5.0 - ±10 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80 - 160 μA per input pin; other inputs at VCC or GND; IO = 0 A; VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V pins MR, SHCP, STCP, OE - 150 675 - 735 μA ΔICC additional supply current pin DS - 25 113 - 123 μA CI input capacitance - 3.5 - - - pF 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 8 / 21

Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 14.

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 25 °C -40 °C to +85 °C -40 °C to +125 °C Symbol Parameter Conditions Min Typ[1] Max Min Max Min Max Unit DS to SHCP; see Fig. 11 VCC = 2 V 50 11 - 65 - 75 - ns VCC = 4.5 V 10 4 - 13 - 15 - ns VCC = 6 V 9 3 - 11 - 13 - ns SHCP to STCP; see Fig. 11 VCC = 2 V 75 22 - 95 - 110 - ns VCC = 4.5 V 15 8 - 19 - 22 - ns tsu set-up time VCC = 6 V 13 7 - 16 - 19 - ns DS to SHCP; see Fig. 11 VCC = 2 V 3 -6 - 3 - 3 - ns VCC = 4.5 V 3 -2 - 3 - 3 - ns th hold time VCC = 6 V 3 -2 - 3 - 3 - ns MR to SHCP; see Fig. 12 VCC = 2 V 50 -19 - 65 - 75 - ns VCC = 4.5 V 10 -7 - 13 - 15 - ns trec recovery time VCC = 6 V 9 -6 - 11 - 13 - ns SHCP or STCP; see Fig. 9 and Fig. 10 VCC = 2 V 9 30 - 4.8 - 4 - MHz VCC = 4.5 V 30 91 - 24 - 20 - MHz fmax maximum frequency VCC = 6 V 35 108 - 28 - 24 - MHz CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC [5] [6] - 115 - - - - - pF 74HCT595; VCC = 4.5 V to 5.5 V SHCP to Q7S; see Fig. 9 [2] - 25 42 - 53 - 63 nstpd propagation delay STCP to Qn; see Fig. 10 [2] - 24 40 - 50 - 60 ns tPHL HIGH to LOW propagation delay MR to Q7S; see Fig. 12 - 23 40 - 50 - 60 ns ten enable time OE to Qn; see Fig. 13 [3] - 21 35 - 44 - 53 ns tdis disable time OE to Qn; see Fig. 13 [4] - 18 30 - 38 - 45 ns SHCP HIGH or LOW; see Fig. 9 16 6 - 20 - 24 - ns STCP HIGH or LOW; see Fig. 10 16 5 - 20 - 24 - ns tW pulse width MR LOW; see Fig. 12 20 8 - 25 - 30 - ns DS to SHCP; see Fig. 11 16 5 - 20 - 24 - nstsu set-up time SHCP to STCP; see Fig. 11 16 8 - 20 - 24 - ns 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 10 / 21

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 25 °C -40 °C to +85 °C -40 °C to +125 °C Symbol Parameter Conditions Min Typ[1] Max Min Max Min Max Unit th hold time DS to SHCP; see Fig. 11 3 -2 - 3 - 3 - ns trec recovery time MR to SHCP; see Fig. 12 10 -7 - 13 - 15 - ns fmax maximum frequency SHCP and STCP; see Fig. 9 and Fig. 10 30 52 - 24 - 20 - MHz CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC - 1.5 V [5] [6] - 130 - - - - - pF [1] Typical values are measured at nominal supply voltage. [2] tpd is the same as tPHL and tPLH. [3] ten is the same as tPZL and tPZH. [4] tdis is the same as tPLZ and tPHZ. [5] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC 2 × fi + Σ(CL × VCC 2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; Σ(CL × VCC 2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. [6] All 9 outputs switching. 11.1. Waveforms and test circuit mna557 SHCP input Q7S output tPLH tPHL tW 1/fmax VM VOH VI GND VOL VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 9. Shift clock pulse, maximum frequency and input to output propagation delays 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 11 / 21

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state mna558 STCP input Qn output tPLH tPHL tW tsu 1/fmax VM VOH VI GND VOL VM SHCP input VI GND VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. Storage clock to output propagation delays mna560 GND GND th tsu th tsu VM VM VM VI VOH VOL VI Q7S output SHCP input DS input Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 11. Data set-up and hold times mna561 MR input SHCP input Q7S output tPHL tW trec VM VOH VOL VI GND VI GND VM VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 12. Master reset to output propagation delays 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 12 / 21

Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Table 8. Measurement points

Test data is given in Table 9. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Table 9. Test data

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 12. Package outline X w M θ A A 1 A 2 b p D H E L p Q detail X E Z e c L v M A (A ) 3 A y pin 1 index UNIT A max. A 1 A 2 A 3 b p c D (1) E (1) (1) e H E L L p Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT109-1 99-12-27 03-02-19 076E07 MS-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 Fig. 15. Package outline SOT109-1 (SO16) 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 15 / 21

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state UNIT A 1 A 2 A 3 b p c D (1) E (2) (1) e H E L L p Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 o o 0.13 0.1 0.2 1 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M b p D Z e 0.25 1 8 16 9 θ A A 1 A 2 L p Q detail X L (A ) 3 H E E c v M A X A y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index Fig. 16. Package outline SOT403-1 (TSSOP16) 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 16 / 21

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state terminal 1 index area 0.5 1 A1 Eh b UNIT y e 0.2 c REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.6 3.4 Dh 2.15 1.85 2.6 2.4 1.15 0.85 2.5 0.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT763-1 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm A(1) max. A c detail X y y1 C e L Eh Dh e b 2 7 15 10 8 1 X D E C B A terminal 1 index area A C C B v M w M E (1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D (1) 02-10-17 03-01-27 Fig. 17. Package outline SOT763-1 (DHVQFN16) 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 17 / 21

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT8016-1 sot8016-1_po Dimensions (mm are the original dimensions) DHXQFN16: plastic, leadless dual in-line compatible thermal enhanced extreme thin quad flat package; no leads; 16 terminals; 0.4 mm pitch; body 2 mm x 2.4 mm x 0.48 mm SOT8016-1 pin1 I.D. 2 mm0 scale 20-09-18 20-09-22 pin 1 index area 15 10 2 7 16 9 D1 AC Bw M AC Bu M Cv M e (12x) L (16x) AD B Epin 1 index area C C z z X A C Cy1 C detail X seating plane y Unit mm max nom min 0.48 0.45 0.42 0.23 0.18 0.13 2.4 1.40 1.35 1.30 0.4 0.35 0.30 0.250.2 A 0.05 0.02 0.00 A1 A3 b D D1 0.1 w 0.05 v 0.1 u 0.15 (typ) keE 2.0 1.00 0.95 0.90 L y1 0.05 y 0.05 z 0.05 b (16x) Fig. 18. Package outline SOT8016-1 (DHXQFN16) 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 18 / 21

Table 10. Abbreviations Table 11. Revision history Modifications: • Type numbers 74HC595DB and 74HCT595DB (SOT338-1/SSOP16) removed.

  • Section 2updated. 74HC_HCT595 v.10 20210429 Product data sheet - 74HC_HCT595 v.9 Modifications: • Type number 74HC595BZ (SOT8016-1 / DHXQFN16) added.
  • Table 4: Derating values for Ptot total power dissipation updated. 74HC_HCT595 v.9 20170228 Product data sheet - 74HC_HCT595 v.8 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia.
  • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT595 v.8 20160225 Product data sheet - 74HC_HCT595 v.7 Modifications: • Type numbers 74HC595N and 74HCT595N (SOT38-4) removed. 74HC_HCT595 v.7 20150126 Product data sheet - 74HC_HCT595 v.6 Modifications: • Table 7: Power dissipation capacitance condition for 74HCT595 is corrected. 74HC_HCT595 v.6 20111212 Product data sheet - 74HC_HCT595 v.5 Modifications: • Legal pages updated. 74HC_HCT595 v.5 20110628 Product data sheet - 74HC_HCT595 v.4 74HC_HCT595 v.4 20030604 Product specification - 74HC_HCT595_CNV v.3 74HC_HCT595_CNV v.3 19980604 Product specification - - 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 19 / 21

Nexperia 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 — 10 September 2021 20 / 21