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Technical content
- General description The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE ) is LOW. 2. Features and benefits 8-bit serial input 8-bit serial or parallel output Storage register with 3-state outputs Shift register with direct clear 100 MHz (typical) shift out frequency ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Applications Serial-to-parallel data conversion Remote control holding register 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 6 — 12 December 2011 Product data sheet
Table 1. Ordering information
Product data sheet Rev. 6 — 12 December 2011 3 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 2. Logic symbol Fig 3. IEC logic symbol OEMR 13 10 11 12 mna552 Q7S DS STCPSHCP mna553 1D 2D C1/ C212
13 EN3
Fig 4. Logic diagram STAGE 0 STAGES 1 TO 6 STAGE 7 FF0 D CP Q R LATCH D CP Q FF7 D CP Q R LATCH D CP Q mna555 DQ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7S DS STCP SHCP OE MR
Product data sheet Rev. 6 — 12 December 2011 4 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 6. Pinning information
6.1 Pinning
Fig 5. Pin configuration DIP16, SO16 Fig 6. Pin configuration SSOP16, TSSOP16 74HC595 74HCT595 Q1 VCC Q2 Q0 Q3 DS Q4 OE Q5 STCP Q6 SHCP Q7 MR GND Q7S 001aao241 74HC595 74HCT595 Q1 VCC Q2 Q0 Q3 DS Q4 OE Q5 STCP Q6 SHCP Q7 MR GND Q7S 001aao242 (1) This is not a supply pin, the substrat e is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to GND. Fig 7. Pin configuration for DHVQFN16 001aao243 74HC595 74HCT595 Q7 MR Q6 SHCP Q5 STCP Q4 OE Q3 DS Q2 Q0 GND Q7S VCC Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area GND(1)
6.2 Pin description
Z = high-impedance OFF-state. Table 2. Pin description Table 3. Function table [1] (internal Q6S) appears on the serial output (Q7S).
[1] For DIP16 package: P tot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: P tot derates linearly with 8 mW/K above 70 C. [3] For SSOP16 and TSSOP16 packages: P tot derates linearly with 5.5 mW/K above 60 C. [4] For DHVQFN16 package: P tot derates linearly with 4.5 mW/K above 60 C. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
- Recommended operating conditions
Table 5. Recommended operating conditions Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
2.1 V; other inputs at VCC or GND;
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
[1] Typical values are measured at nominal supply voltage. [2] t pd is the same as tPHL and tPLH. [3] t pd is the same as tPHL only. [4] t en is the same as tPZL and tPZH. [5] t dis is the same as tPLZ and tPHZ. [6] C PD is used to determine the dynamic power dissipation (PD in W). [7] All 9 outputs switching. Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14. Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load.
Product data sheet Rev. 6 — 12 December 2011 13 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Storage clock to output propagation delays mna558 STCP input Qn output tPLH tPHL tW tsu 1/fmax VM VOH VI GND VOL VM SHCP input VI GND VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Data set-up and hold times mna560 GND GND th tsu th tsu VM VM VM VI VOH VOL VI Q7S output SHCP input DS input
Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Table 8. Measurement points
Test data is given in Table 9. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Table 9. Test data
Product data sheet Rev. 6 — 12 December 2011 16 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 13. Package outline Fig 15. Package outline SOT38-4 (DIP16) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT38-4 95-01-14 03-02-13 MH c (e )1 ME A L seating plane w M e D Z E pin 1 index b 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. UNIT A max. 12 b1 (1) (1) (1) b2 cD E e M ZHL mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) A min. A max. b max.wMEe1 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 7.80 10.0 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.31 0.39 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
Product data sheet Rev. 6 — 12 December 2011 17 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 16. Package outline SOT109-1 (SO16) X w M θ AA1 bp D HE Lp Q detail X E Z e c L v M A (A )3 A y pin 1 index UNIT A max. A1 A2 A3 bp cD (1) E(1) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT109-1 99-12-27 03-02-19 076E07 MS-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.0410.244 0.228 0.028 0.020 0.028 0.0120.01 0.25 0.01 0.0040.039 0.016 0 2.5 5 mm scale SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Product data sheet Rev. 6 — 12 December 2011 18 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 17. Package outline SOT338-1 (SSOP16) UNIT A1 A2 A3 bp cD (1) E (1) eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.257.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 o o0.130.2 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT338-1 99-12-27 03-02-19 (1) w M bp D HE E Z e c v M A X A y 1 8 16 9 θ AA1 Lp Q detail X L (A )3 MO-150 pin 1 index 0 2.5 5 mm scale SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 A max.
Product data sheet Rev. 6 — 12 December 2011 19 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 18. Package outline SOT403-1 (TSSOP16) UNIT A1 A2 A3 bp cD (1) E (2) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 16 9 θ AA1 Lp Q detail X L (A )3 HE E c v M A XA y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index
Product data sheet Rev. 6 — 12 December 2011 20 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 19. Package outline SOT763-1 (DHVQFN16) terminal 1 index area 0.51 A1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.6 3.4 Dh 2.15 1.85 2.6 2.4 1.15 0.85 2.50.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT763-1 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm A(1) max. A c detail X yy1 Ce L Eh Dh e b 15 10 X D E C B A terminal 1 index area A C C Bv M w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1) 02-10-17 03-01-27
Table 10. Abbreviations Table 11. Revision history
- Legal pages updated. 74HC_HCT595 v.5 20110628 Product data sheet - 74HC_HCT595 v.4 74HC_HCT595 v.4 20030604 Product s pecification - 74HC_HCT595_CNV v.3 74HC_HCT595_CNV v.3 19980604 Product specification - -
Product data sheet Rev. 6 — 12 December 2011 22 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 6 — 12 December 2011 23 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 December 2011 Document identifier: 74HC_HCT595 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents