74HC595

74HC595 WINGS | Alldatasheet

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Technical content

8-Bit Shift Registers W ith Latched 3-State Output GENERAL DESCRIPTION 74HC595 is fabricated with high-speed silicon gate CMOS technology. It contains an 8-bit serial-in, serial or parallel-out shift register an d an 8-bit D-type storage register with parallel 3-state outputs. The shift and storage register have independent clock inputs. Both the shift register clock (SRCK) and storage register clock (RCK) are positive-edge triggered. The shift register has a direct overriding clear input (SRCL), serial data input (SER), and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

FEATURES

• 8-bit serial-in, parallel-out shift register with storage
• Shift register has direct clear
• 8-bit D-type storage register with parallel 3-sta te outputs
• Two independent clocks for shift and storage regi ster
• Wide operating power supply voltage 2-6V
• Low input current < 1 µA
• Low power consumption, Max. 80 µA (74HC595)
• Output driving capacity ± 6 mA at 5V
• Typical propagation delay 13nS LOGIC DIAGRAM R R Q8’ Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 15 1 2 3 4 5 6 7 SRCK SER SRCL OE RCK R R R R R R

1. Truth Table Inputs Function SER SRCK SRCL RCK OE X X X X H Outputs Q1-Q8 are disabled. X X X X L Outputs Q1-Q8 are enabled. X X L X X Shift register is cleared. L ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored in the latch. H = High Level (steady state). L= Low Level (steady state) X = Irrelevant (don’t care) ↑= Transition from low to high level. 2. Logic Waveform Note: implies that the outputs are in 3-state mode. SRCK SER RCK SRCL OE Q8'

DC supply voltage Vcc - 0.5 ~ + 7.0 V DC input clamp current Iik (Vi<0 or Vi>Vcc) ±20 mA DC output clamp current Iok (Vo<0 or Vo>Vcc) ±20 mA DC Current Drain per pin, any output (Iout) ±35 mA DC supply Current, Vcc or GND (Icc) ±70 mA Storage Temperature( TSTG) -65 ~ +150 ℃ Lead Temperature(TL) (Soldering, 10seconds) 260 ℃ Note: 1. Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. RECOMMENDED OPERATING CONDITONS Parameter Min. Normal Max. Unit Power Supply V oltage (Vcc) 2 5 6 V VCC=2.0V 1.5 VIH High-level input voltage VCC=4.5V 3.15 V VCC=6.0V 4.2 VCC=2.0V 0.5 V IL Low-level Input Voltage VCC=4.5V 1.35 V VCC=6.0V 1.8 VI Input V oltage 0 Vcc V VO Output V oltage 0 Vcc V 74HC595 -40 85 ℃ Operating Temperature (TA) Input Rise/Fall Times (tr, tf) VCC=2.0V 1000 VCC=4.5V 500 VCC=6.0V 400 ns Note: 2. All unused inputs of the device must be held at Vcc or GND to ensure proper device operation. 3. If this device is used in the threshold region (from V ILmax = 0.5 V to V IHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. O perating with the inputs at tt = 1000 ns and Vcc = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

DC ELECTRICAL CHARACTERISTICS (Apply across temperature range unless otherwise sp ecified) TA = 25℃ 54HC595 74HC595 PARAMETER TEST CONDITIONS Vcc MIN TYP MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 IOH = -20uA 4.5V 4.4 4.499 4.4 VOH VI= VIH or VIL 6 V 5.9 5.999 5.9 V IOH = -6 mA 4.5V 3.98 4.3 3.84 IOH = -7.8mA 6 V 5.48 5.8 5.34 2 V 0.0020.1 0.1 IOL =20uA 4.5V 0.0010.1 0.1 VOL VI= VIH or VIL 6 V 0.0010.1 0.1 V IOL = 6mA 4.5V 0.170.26 0.33 IOL =7.8mA 6 V 0.15 0.26 0.33 II VI = Vcc or 0 6 V ±0.1 ±100 ±1000 nA IOZ VO = Vcc or 0, Q1-Q8 6 V ±0.01 ±0.5 ±5 uA Icc VI = Vcc or 0 IO = 0 6 V 8 80 uA Ci 2V ~ 6V 310 10 pF TIMING REQUREMENTS OVER RECOMMENED OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise noted) Parameter Symbol Unit Guaranteed Limit Test Condition TA=25℃ -40~+85 Clock frequency fclock MHz 6 5 Vcc=2.0V 31 25 Vcc=4.5V 36 29 Vcc=6.0V Pulse duration t w ns 80 100 Vcc=2.0V SRCK or LCK high or low 16 20 Vcc=4.5V 14 17 Vcc=6.0V 80 100 Vcc=2.0V 16 20 Vcc=4.5V 14 17 Vcc=6.0V SRCL low 100 125 Vcc=2.0V 20 25 Vcc=4.5V SER before SRCK↑ 17 21 Vcc=6.0V 75 94 Vcc=2.0V 15 19 Vcc=4.5V SRCK↑ before LCK↑ Setup time tsu ns 13 16 Vcc=6.0V (Note 4) 50 65 Vcc=2.0V 10 13 Vcc=4.5V SRCL low before RCK↑ 9 11 Vcc=6.0V 50 60 Vcc=2.0V 10 12 Vcc=4.5V SRCL high(inactive) 9 11 Vcc=6.0V before SRCK↑ Hold time, t h ns 0 0 Vcc=2~6V SER after SRCK↑ Note: . 4. This setup time allows the latch to receive stable data from the shift register. The clock can be connected together, in this case the shift register is one clock pulse ahead of the latch.

AC ELECTRICAL CHARACTERISTICS (unless otherwise noted) Parameter Symbol From To Unit Vcc Ta = 25℃ 74HC595 Parameter (Input) (Output) Min Typ Max Min Max Maximum 2V 6 26 5 clock 4.5V 31 38 25 CL=50pF frequency fmax MHz 6V 36 42 29 2V 50 160 200 SRCK Q 8' 4.5V 17 32 40 ns 6V 14 27 34 CL=50pF Maximum 2V 50 150 187 Propagation LCK Q 1-Q8 4.5V 17 30 37 Delay ns 6V 14 26 32 (Clock to Q) 2V 60 200 250 LCK Q 1-Q8 4.5V 22 40 50 CL=150pF tpd ns 6V 19 34 43 2V 51 175 219 SRCL QH' 4.5V 18 35 44 CL=50pF Maximum Propagation Delay (SRCL to Q8' tPHL ns 6V 15 30 37 2V 40 150 187 4.5V 15 30 37 CL=50pF 6V 13 26 32 ten OE Q 1-Q8 ns 2V 70 200 250 4.5V 23 40 50 CL=150pF 6V 19 34 43 Maximum Propagation Delay (OE to Q) 2V 42 200 250 tdis OE Q 1-Q8 ns 4.5V 23 40 50 CL=50pF 6V 20 34 43 2V 28 60 75 Q 1-Q8 4.5V 8 12 15 Maximum 6V 6 10 13 Output 2V 28 75 95 CL=50pF Rising and t t Q 8' ns 4.5V 8 15 19 Falling Time 6V 6 13 16 2V 45 210 265 Q 1-Q8 4.5V 17 42 53 CL=150pF 6V 13 36 45 Power Dissipation Capacitance CPD pF 400 – PARAMETER MEASUREMENT INFORMATION CL From Output Under Test Vcc RL Test Point PARAMETER RL CL S1 S2 tPZH 1 kΩ Open Closed ten tPZL 50 pF or 150 pF Closed Open tPHZ Open Closed tdis tPLZ 1kΩ 50 pF Closed Open tpd or tt - 50 pF or 150 pF Open Open

AC SWITCHING WAVEFORM AND AC TEST CIRCUIT Voltage Waveforms 1. Propagation Delay and Output Transition Times V oltage waveforms 2. Enable And Disable Times For 3-State Outputs Voltage waveforms 3. Setup And Hold and Input Rise And Fall Times 50% 50% 50% 90% 50% 10% tPZL tPLZ tPHZ Vcc 0 V ≈Vcc VOL VOH ≈0 V tPZH ≈Vcc Output Control (Low-Level Enabling) Output Waveform1 Output Waveform tPLH tr tPHL tf tf tr tPHL tPLH 50% 50% 50% 10% 90% 90% 50% 10% 90% 50% 10% 90%50% 10% Input In-Phase Output Out-of-Phase Output Vcc 0 V VOH VOL VOH VOL tr 50% 10% 90% 90% 50% 10% tf Vcc 0 V Input 0 V Input 50% tsu Vcc th Reference Data

Voltage waveforms 4. Pulse Durations Note: 5. CL includes probe and test-fixture capacitance. 6. Phase relationships between waveforms were chosen arbitraril y. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. 7. For clock inputs, fmax is measured when the input duty cycle is 50%. 8. The outputs are measured one at a time, with one input transition per measurement. 9. tPLZ and tPHZ are the same as tdis. 10. tPZL and tPZH are the same as ten. 11. tPLH and tPHL are the same as tpd. PIN DESCRIPTION PIN NO. SYMBOL DESCRIPTION 11, 12 Q1 – Q 8 Q8’ SRCL SRCK, RCK OE SER GND VCC Parallel data outputs Serial data output Shift register reset input (active low) Shift and storage register clock inputs (triggered at positive edge) Output enable input (active low) Serial data input Ground (0V) Positive power supply SER OE RCK Vcc SRCK GND SRCL Q8’ SER OE RCK SRCK SRCL Q8’ 10 13 Pin Configuration Logic Symbol tw 50% 50% 50% 50%Low-Level Pulse Vcc Vcc High-Level Pulse

The Coordinate of Each Pad Note: Substrate should be connected to Vcc or left it open. SRCK Pad Size = 90 um X 90 um 74HC595 Die Size = 57 mil X 74 mil Q8 GND Q8’ SRCL RCK SER OE VCC