74HC595

M54HC595 STMICROELECTRONICS | Alldatasheet

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Technical content

8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)

(Plastic Package) ORDER CODES : M54HC595F1R M74HC595M1R M74HC595B1R M74HC595C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connecti on .HIGH SPEED fMAX = 55 MHz (TYP.) AT VCC =5V .LOW POWER DISSIPATION ICC =4 µA (MAX.) AT TA =2 5°C .HIGH NOISE IMMUNITY VNIH =V NIL =2 8%V CC (MIN.) .OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS FOR QA TO QH

10 LSTTL LOADS FOR QH’

.SYMMETRICAL OUTPUT IMPEDANCE OH |=IOL = 6 mA (MIN.) FOR QA TO QH |IOH |=IOL = 4 mA (MIN.) FOR QH’ .BALANCED PROPAGATION DELAYS tPLH =tPHL .WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V .PIN AND FUNCTION COMPATIBLE WITH LSTTL 54/74LS5 95

DESCRIPTION

The M54/74HC595 is a high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (3- STATE) fabricated in silicon C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage reg- ister. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift reg- ister and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascad- ing. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will al- ways be one clock pulse ahead of the storage reg- ister. All inputs are equipped with protection circuits against static discharge and transient excess volt- age.

INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS OUTPUT SI SCK SCLR RCK G X X X X H QA THRU QH OUTPUTS DISABLE X X X X L QA THRU QH OUTPUTS ENABLE X X L X X SHIFT REGISTER IS CLEARED LH X X FIRST STAGE OF S.R. BECOMES ”L” OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY HH X X FIRST STAGE OF S.R. BECOMES ”H” OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY X H X X STATE OF S.R IS NOT CHANGED X X X X S.R. DATA IS STORED INTO STORAGE REGISTER X X X X STORAGE REGISTER STATE IS NOT CHANGED X: DON’T CARE LOGIC DIAGRAM M54/M74HC595

Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Input Voltage -0.5 to V CC + 0.5 V VO DC Output Voltage -0.5 to V CC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current Per Output Pin QA-QH ± 35 mA IO DC Output Current Per Output Pin QH’ ± 25 mA ICC or IGND DC V CC or Ground Current ± 70 mA P D Power Dissipation 500 (*) mW Tstg Storage Temperature -65 to +150 oC TL Lead Temperature (10 sec) 300 oC Absolute MaximumRatings are those values beyond whichdamage tothe device may occu r. Functional operation under these condition isnotimplied. (*) 500 mW:≅ 65 oC derate to 300 mW by 10mW/oC: 65oCt o 8 5oC RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Supply Voltage 2 to 6 V VI Input Voltage 0 to V CC V VO Output Voltage 0 to V CC V Top Operating Temperature:M54HC Series M74HC Series -55 to +125 -40 to +85 oC oC tr,tf Input Rise and Fall Time V CC = 2 V 0 to 1000 ns VCC = 4.5 V 0 to 500 VCC = 6 V 0 to 400 PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 2, 3, 4, 5, 6, 7, 15 QA to QH Data Outputs

9 QH’ Serial Data Outputs

10 SCLR Shift Register Clear

11 SCK Shift Register Clock

13 G Output Enable Input

14 SI Serial Data Input

12 RCK Storage Register Clock

8 GND Ground (0V)

16 V CC Positive Supply Voltage

(V) TA =2 5oC 54HC and 74HC -40 to 85oC 74HC -55 to 125oC 54HC VIH High Level Input Voltage 2.0 1.5 1.5 1.5 V4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 V IL Low Level Input Voltage 2.0 0.5 0.5 0.5 V4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 V OH High Level Output Voltage (for QH’ output) 2.0 V I = VIH or V IL IO =-20µA 1.9 2.0 1.9 1.9 V V OH High Level Output Voltage (for QA to QH outputs)

2.0 VI =

IO =-20µA 1.9 2.0 1.9 1.9 V VOL Low Level Output Voltage (for QH’ output) 2.0 V I = VIH or V IL IO =2 0µA 0.0 0.1 0.1 0.1 V 4.5 I VOL Low Level Output Voltage (for QA to QH outputs) 2.0 V I = VIH or V IL IO =2 0µA 0.0 0.1 0.1 0.1 V 4.5 I II Input Leakage Current 6.0 VI =V CC or GND ±0.1 ±1 ±1 µA IOZ 3 State Output Off State Current6.0 VI =V IH or VIL VO =V CC or GND ±0.5 ±5 ±10 µA ICC Quiescent Supply Current

6.0 V I =V CC or GND 4 40 80 µA

AC ELECTRICAL CHARACTERISTICS (CL =5 0p F ,I n p u ttr =t f =6n s ) Symbol Parameter Test Conditions Value UnitVCC (V) C L (pF) TA =2 5oC 54HC and 74HC -40 to 85oC 74HC -55 to 125oC 54HC tTLH tTHL Output Transition Time (Qn) 2.0 25 60 75 90 ns4 . 5 7 1 21 51 8 6 . 0 6 1 01 31 5 tTLH tTHL Output Transition Time (QH’) 2.0 30 75 95 115 ns4 . 5 8 1 51 92 3 6 . 0 7 1 31 62 0 tPLH tPHL Propagation Delay Time (SCK - QH’) 2.0 45 125 155 190 ns4.5 15 25 31 38 6.0 13 21 26 32 t PLH tPHL Propagation Delay Time (SCLR - QH’) 2.0 60 175 220 265 ns4.5 18 35 44 53 6.0 15 30 37 45 tPLH tPHL Propagation Delay Time (RCK - Qn) 2.0 60 150 190 225 ns4.5 20 30 38 45 6.0 17 26 32 38 2.0 150 75 190 240 285 ns4.5 25 38 48 57 6.0 22 32 41 48 t PZL tPZH

3 State Output

2.0

50 R L =1K Ω

ns4.5 15 27 34 41 6.0 13 23 29 35 2.0

150 R L =1K Ω

ns4.5 20 35 44 53 6.0 17 30 37 45 tPLZ tPHZ 2.0 ns4.5 15 30 38 45 6.0 14 26 32 38 fMAX Maximum Clock Frequency 2.0 6.0 17 4.8 4 ns4.5 30 50 24 20 6.0 35 59 28 24 2.0 150 5.2 14 4.2 3.4 ns4.5 26 40 21 17 6.0 31 45 25 20 t W(H) Minimum Pulse Width (SCK, RCK) 2.0 17 75 95 110 ns4 . 5 6 1 51 92 2 6 . 0 6 1 31 61 9 t W(L) Minimum Pulse Width (SCLR) 2.0 20 75 95 110 ns4 . 5 6 1 51 92 2 6 . 0 6 1 31 61 9 t s Minimum Set-up Time (SI - CCK) 2.0 25 50 65 75 ns4 . 5 5 1 01 31 5 6.0 4 9 11 13 M54/M74HC595

AC ELECTRICAL CHARACTERISTICS (CL =5 0p F ,I n p u ttr =t f =6n s ) Symbol Parameter Test Conditions Value UnitVCC (V) C L (pF) TA =2 5oC 54HC and 74HC -40 to 85oC 74HC -55 to 125oC 54HC ts Minimum Set-up Time (SCK - RCK) 2.0 35 75 95 110 ns4 . 5 8 1 51 92 2 6 . 0 6 1 31 61 9 ts Minimum Set-up Time (SCRL - RCK) 2.0 40 100 125 145 ns4.5 10 20 25 29 6 . 0 7 1 72 12 5 t h Minimum Hold Time 2.0 000 ns4.5 0 0 0 6.0 0 0 0 tREM Minimum Clear Remuval Time 2.0 15 50 65 75 ns4 . 5 3 1 01 31 5 6.0 3 9 11 13 C IN Input Capacitance 5 10 10 10 pF C PD (*) Power Dissipation Capacitance 184 pF (*) CPD is defined as the value of the IC’s internal equivalent capac itance which is calculated from the operating current consump tion without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC (opr) = CPD •VCC •fIN +ICC SWITCHING CHARACTERISTICS TEST WAVEFORM WAVEFORM 1 WAVEFORM 2 M54/M74HC595

TEST CIRCUIT ICC (Opr.) SWITCHING CHARACTERISTICS TEST WAVEFORM (continued) INPUT WAVEFORM M54/M74HC595

Plastic DIP16 (0.25) MECHANICAL DATA DIM. mm inch a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 P001C M54/M74HC595

Ceramic DIP16/1 MECHANICAL DATA DIM. mm inch A 20 0.787 B 7 0.276 D 3.3 0.130 E 0.38 0.015 e3 17.78 0.700 F 2.29 2.79 0.090 0.110 G 0.4 0.55 0.016 0.022 H 1.17 1.52 0.046 0.060 L 0.22 0.31 0.009 0.012 M 0.51 1.27 0.020 0.050 N 10.3 0.406 P 7.8 8.05 0.307 0.317 Q 5.08 0.200 P053D M54/M74HC595

SO16 (Narrow) MECHANICAL DATA DIM. mm inch A 1.75 0.068 a1 0.1 0.2 0.004 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 ° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.62 0.024 S8 ° (max.) P013H M54/M74HC595

DIM. mm inch A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 e3 5.08 0.200 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.045 P027A M54/M74HC595

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