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standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC02; 74HCT02 provides a quad 2-input NOR function. Table 1. Ordering information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP14 package: P tot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
- Recommended operating conditions
Table 3. Function table [1] Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 5. Recommended operating conditions
Table 5. Recommended operating conditions …continued Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
[1] t pd is the same as tPHL and tPLH. [2] t t is the same as tTHL and tTLH. (CL VCC2 fo) = sum of outputs. GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Table 8. Measurement points
Test data is given in Table 9. RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Table 9. Test data
Product data sheet Rev. 4 — 4 September 2012 8 of 16 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate 12. Package outline Fig 8. Package outline SOT27-1 (DIP14) UNIT A max. 1 2 (1) (1)b1 cD (1)ZEe M HL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT27-1 99-12-27 03-02-13 A min. A max. b max.wMEe1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 7.80 10.0 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.31 0.39 050G04 MO-001 SC-501-14 MH c (e )1 ME A L seating plane w M e D Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
Product data sheet Rev. 4 — 4 September 2012 9 of 16 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate Fig 9. Package outline SOT108-1 (SO14) UNIT A max. A1 A2 A3 bp cD (1) E(1) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT108-1 X w M θ AA1 bp D HE Lp Q detail X E Z e c L v M A (A )3 A y 076E06 MS-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.0410.244 0.228 0.028 0.024 0.028 0.0120.01 0.25 0.01 0.0040.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Product data sheet Rev. 4 — 4 September 2012 10 of 16 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate Fig 10. Package outline SOT337-1 (SSOP14) UNIT A1 A2 A3 bp cD (1) E (1) eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 7.6 1.03 0.63 0.9 0.7 1.4 0.9 o o0.13 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT337-1 99-12-27 03-02-19 (1) w M bp D HE E Z e c v M A X A y 1 7 14 8 θ AA1 Lp Q detail X L (A )3 MO-150 pin 1 index 0 2.5 5 mm scale SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 A max.
Product data sheet Rev. 4 — 4 September 2012 11 of 16 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate Fig 11. Package outline SOT402-1 (TSSOP14) UNIT A1 A2 A3 bp cD (1) E (2) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT402-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 14 8 θ AA1 Lp Q detail X L (A )3 HE E c v M A XA y 0 2.5 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 A max. 1.1 pin 1 index
Product data sheet Rev. 4 — 4 September 2012 12 of 16 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate Fig 12. Package outline SOT762-1 (DHVQFN14) terminal 1 index area 0.51 A1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.1 2.9 Dh 1.65 1.35 2.6 2.4 1.15 0.85 20.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT762-1 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm A(1) max. A c detail X yy1 Ce L Eh Dh e b 13 9 X D E C B A 02-10-17 03-01-27 terminal 1 index area A C C Bv M w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1)
Table 10. Abbreviations Table 11. Revision history
- Conditions for VOH, II and ICC updated to the family specification (errata). 74HC_HCT02 v.3 20080918 Product data sheet - 74HC_HCT02_CNV v.2 Modifications:
- The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
- Legal texts have been adapted to the new company name where appropriate.
- Added type numbers 74HC02BQ and 74HCT02BQ (DHVQFN14 package) 74HC_HCT02_CNV v.2 19970827 Product specification - -
Product data sheet Rev. 4 — 4 September 2012 14 of 16 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate 15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 4 — 4 September 2012 15 of 16 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 September 2012 Document identifier: 74HC_HCT02 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 17. Contents