74HC02 PHILIPS | Alldatasheet

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Technical content

Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT02 Quad 2-input NOR gate For a complete data sheet, please also download:

  • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Quad 2-input NOR gate 74HC/HCT02

FEATURES

  • Output capability: standard
  • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT02 provide the 2-input NOR function. QUICK REFERENCE DATA GND = 0 V; T amb =2 5°C; tr =tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi + ∑ (CL × VCC 2 × fO ) where: fi= input frequency in MHz fo = output frequency in MHz C L = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC 2 × fo) = sum of outputs 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay nA, nB to nY C L = 15 pF; VCC =5V 7 9 n s C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per gate notes 1 and 2 22 24 pF

Philips Semiconductors Product specification Quad 2-input NOR gate 74HC/HCT02 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 4, 10, 13 1Y to 4Y data outputs 2, 5, 8, 11 1A to 4A data inputs 3, 6, 9, 12 1B to 4B data inputs

7 GND ground (0 V)

CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram. Fig.5 Logic diagram (one gate). FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level INPUTS OUTPUT nA nB nY L L H H L H L H H L L L

Philips Semiconductors Product specification Quad 2-input NOR gate 74HC/HCT02 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) TEST CONDITIONS 74HC UNIT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay nA, nB to nY 115 135 ns 2.0 4.5 6.0 Fig.6 t THL / tTLH output transition time 110 ns 2.0 4.5 6.0 Fig.6

Philips Semiconductors Product specification Quad 2-input NOR gate 74HC/HCT02 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI Notes to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL = 50 pF AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. INPUT UNIT LOADCOEFFICIENT nA, nB 1.50 SYMBOL PARAMETER Tamb (°C) TEST CONDITIONS 74HCT UNIT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay nA, nB to nY 11 19 24 29 ns 4.5 Fig.6 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times. HC: VM = 50%; VI= GND to VCC HCT: VM = 1.3 V; VI= GND to 3 V.