74HC-HCT594-Q100 NEXPERIA | Alldatasheet

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74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register Rev. 4 — 27 September 2022 Product data sheet 1. General description The 74HC594-Q100; 74HCT594-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers. The device features a serial input (DS) and a serial output (Q7S) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the SHCP input, and the data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. A LOW level on one of the two register reset pins (SHR and STR) will clear the corresponding register. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Synchronous serial input and output
  • 8-bit parallel output
  • Shift and storage registers have independent direct clear and clocks
  • Independent clocks for shift and storage registers
  • 100 MHz (typical)
  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Input levels:
  • For 74HC594-Q100: CMOS level
  • For 74HCT594-Q100: TTL level
  • Complies with JEDEC standards
  • JESD8C (2.7 V to 3.6 V)
  • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
  • MIL-STD-883, method 3015 exceeds 2 kV
  • HBM JESD22-A114F exceeds 2 kV
  • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Applications
  • Serial-to parallel data conversion
  • Remote control holding register

Table 1. Ordering information

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register mbc321Q0 Q1 Q2 Q3 Q4 Q5 Q6 DS SHCP SHR STCP STR D Q CP FFSH0 R STAGE 0 D Q CP FFST0 R STAGES 1 TO 6 D Q D Q CP FFSH7 R STAGE 7 D Q CP FFST7 R Q7S Fig. 4. Logic diagram mbc323 Q7S STR SHR STCP DS SHCP Fig. 5. Timing diagram 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 3 / 22

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register 6. Pinning information 6.1. Pinning D package SOT109-1 (SO16) Q1 VCC Q2 Q0 Q3 DS Q4 STR Q5 STCP Q6 SHCP Q7 SHR GND Q7S aaa-035345 PW package SOT403-1 (TSSOP16) Q1 VCC Q2 Q0 Q3 DS Q4 STR Q5 STCP Q6 SHCP Q7 SHR GND Q7S aaa-035347 aaa-034033 BQ package SOT763-1 (DHVQFN16) Q7 SHR Q6 SHCP Q5 STCP Q4 STR Q3 DS Q2 Q0 GND Q7S VCC Transparent top view VCC(1) 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area (1) This is not a supply pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to VCC. 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 4 / 22

Table 2. Pin description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; X = don’t care.

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C.

  1. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V).

Table 6. Static characteristics type 74HC594-Q100 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Table 7. Static characteristics type 74HCT594-Q100 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register Symbol Parameter Conditions Min Typ Max Unit Tamb = -40 °C to +85 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VI = VIH or VIL Q7S; IO = -4.0 mA; VCC = 4.5 V 3.84 - - V VOH HIGH-level output voltage Qn; IO = -6.0 mA; VCC = 4.5 V 3.84 - - V VI = VIH or VIL Q7S; IO = 4.0 mA; VCC = 4.5 V - - 0.33 V VOL LOW-level output voltage Qn; IO = 6.0 mA; VCC = 4.5 V - - 0.33 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80 μA per input pin; VI = VCC - 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pins SHR, SHCP, STCP, STR - - 675 μA ΔICC additional supply current pin DS - - 112.5 μA Tamb = -40 °C to +125 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VI = VIH or VIL Q7S; IO = -4.0 mA; VCC = 4.5 V 3.7 - - V VOH HIGH-level output voltage Qn; IO = -6.0 mA; VCC = 4.5 V 3.7 - - V VI = VIH or VIL Q7S; IO = 4.0 mA; VCC = 4.5 V - - 0.4 V VOL LOW-level output voltage Qn; IO = 6.0 mA; VCC = 4.5 V - - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 160 μA per input pin; VI = VCC - 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pins SHR, SHCP, STCP, STR - - 735 μA ΔICC additional supply current pin DS - - 122.5 μA 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 9 / 22

Table 8. Dynamic characteristics type 74HC594-Q100 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; For test circuit see Fig. 12.

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register 25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions Min Typ Max Min Max Min Max Unit SHCP (HIGH or LOW); see Fig. 6 VCC = 2.0 V 80 10 - 100 - 120 - ns VCC = 4.5 V 16 4 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns STCP (HIGH or LOW); see Fig. 7 VCC = 2.0 V 80 10 - 100 - 120 - ns VCC = 4.5 V 16 4 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns SHR and STR (HIGH or LOW); see Fig. 10 and Fig. 11 VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns tW pulse width VCC = 6.0 V 14 4 - 17 - 20 - ns DS to SHCP; see Fig. 8 VCC = 2.0 V 100 10 - 125 - 150 - ns VCC = 4.5 V 20 4 - 25 - 30 - ns VCC = 6.0 V 17 3 - 21 - 26 - ns SHR to STCP; see Fig. 9 VCC = 2.0 V 100 14 - 125 - 150 - ns VCC = 4.5 V 20 5 - 25 - 30 - ns VCC = 6.0 V 17 4 - 21 - 26 - ns SHCP to STCP; see Fig. 7 VCC = 2.0 V 100 17 - 125 - 150 - ns VCC = 4.5 V 20 6 - 25 - 30 - ns tsu set-up time VCC = 6.0 V 17 5 - 21 - 26 - ns DS to SHCP; see Fig. 8 VCC = 2.0 V 25 -8 - 30 - 35 - ns VCC = 4.5 V 5 -3 - 6 - 7 - ns th hold time VCC = 6.0 V 4 -2 - 5 - 6 - ns SHR to SHCP and STR to STCP; see Fig. 10 and Fig. 11 VCC = 2.0 V 50 -14 - 65 - 75 - ns VCC = 4.5 V 10 -5 - 13 - 15 - ns trec recovery time VCC = 6.0 V 9 -4 - 11 - 13 - ns 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 11 / 22

[1] tpd is the same as tPHL and tPLH. ∑(CL × VCC 2 × fo) = sum of outputs. Table 9. Dynamic characteristics type 74HCT594-Q100 GND = 0 V; VCC = 4.5 V; tr = tf = 6 ns; CL = 50 pF; For test circuit see Fig. 12.

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register 25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions Min Typ Max Min Max Min Max Unit DS to SHCP; see Fig. 8 20 4 - 25 - 30 - ns SHR to STCP; see Fig. 9 20 6 - 25 - 30 - ns tsu set-up time SHCP to STCP; see Fig. 7 20 7 - 25 - 30 - ns th hold time DS to SHCP; see Fig. 8 5 -3 - 6 - 7 - ns trec recovery time SHR to SHCP and STR to STCP; see Fig. 10 and Fig. 11 10 -5 - 13 - 15 - ns SHCP or STCP; see Fig. 6 and Fig. 7 30 92 - 24 - 20 - MHzfmax maximum frequency VCC = 5.0 V; CL = 15 pF - 100 - - - - - MHz CPD power dissipation capacitance VI = GND to VCC - 1.5 V; VCC = 5 V; fi = 1 MHz [1] tpd is the same as tPHL and tPLH. [2] CPD is used to determine the dynamic power dissipation (PD in μW): PD = CPD × VCC 2 × fi × N + ∑(CL × VCC 2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC 2 × fo) = sum of outputs. 11.1. Waveforms and test circuit 001aae341 SHCP input Q7S output VM tPLH tTLH tTHL tPHL VM tW 1/fmax Measurement points are given in Table 10. Fig. 6. The shift clock (SHCP) to output (Q7S) propagation delays, the shift clock pulse width, the maximum shift clock frequency, and output transition times 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 13 / 22

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register VM tW 1/fmax VM VM tsu tPLH Qn outputs STCP input SHCP input tPHL mla512 Measurement points are given in Table 10. Fig. 7. The storage clock (STCP) to output (Qn), propagation delays, the storage clock pulse width, the maximum storage clock pulse frequency and the shift clock to storage clock set-up time 001aae342 th tsu th tsu VM VM VMQ7 output SHCP input DS input Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 8. The data set-up time and hold times for DS input to SHCP mbc326 VM tsu VM VM STCP input Qn outputs SHR input Measurement points are given in Table 10. Fig. 9. The set-up time shift reset (SHR) to storage clock (STCP) 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 14 / 22

Measurement points are given in Table 10. Measurement points are given in Table 10. Table 10. Measurement points

Test data is given in Table 11. Table 11. Test data

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register 12. Package outline X w M θ A A 1 A 2 b p D H E L p Q detail X E Z e c L v M A (A ) 3 A y pin 1 index UNIT A max. A 1 A 2 A 3 b p c D (1) E (1) (1) e H E L L p Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT109-1 99-12-27 03-02-19 076E07 MS-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 Fig. 13. Package outline SOT109-1 (SO16) 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 17 / 22

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register UNIT A 1 A 2 A 3 b p c D (1) E (2) (1) e H E L L p Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 o o 0.13 0.1 0.2 1 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M b p D Z e 0.25 1 8 16 9 θ A A 1 A 2 L p Q detail X L (A ) 3 H E E c v M A X A y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index Fig. 14. Package outline SOT403-1 (TSSOP16) 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 18 / 22

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register terminal 1 index area 0.5 1 A1 Eh b UNIT y e 0.2 c REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.6 3.4 Dh 2.15 1.85 2.6 2.4 1.15 0.85 2.5 0.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT763-1 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm A(1) max. A c detail X y y1 C e L Eh Dh e b 2 7 15 10 8 1 X D E C B A terminal 1 index area A C C B v M w M E (1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D (1) 02-10-17 03-01-27 Fig. 15. Package outline SOT763-1 (DHVQFN16) 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 19 / 22

Table 12. Abbreviations Table 13. Revision history Modifications: • Type number 74HC594BQ-Q100 (SOT763-1/DHVQFN16) added.

  • Legal texts have been adapted to the new company name where appropriate.
  • Section 1 and Section 2 updated.
  • Section 8: Derating values for Ptot total power dissipation updated.
  • Section 9: rise time and fall time replaced by input transition rise and fall rate. 74HC_HCT594_Q100 v.2 20160613 Product data sheet - 74HC_HCT594_Q100 v.1 Modifications: • Added type number 74HC594PW-Q100 (SOT403-1). 74HC_HCT594_Q100 v.1 20120802 Product data sheet - - 74HC_HCT594_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 — 27 September 2022 20 / 22

Nexperia 74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. 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