74HCHCT377 PHILIPS | Alldatasheet

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Technical content

Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT377 Octal D-type flip-flop with data enable; positive-edge trigger For a complete data sheet, please also download:

  • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74HC/HCT377

FEATURES

  • Ideal for addressable register applications
  • Data enable for address and data synchronization

applications

  • Eight positive-edge triggered D-type flip-flops
  • See “273” for master reset version
  • See “373” for transparent latch version
  • See “374” for 3-state version
  • Output capability: standard
  • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT377 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable ( E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Q n) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. QUICK REFERENCE DATA GND = 0 V; Tamb =2 5°C; tr =tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi+∑ (CL × VCC 2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay CP to Qn C L = 15 pF; VCC = 5 V 13 14 ns fmax maximum clock frequency 77 53 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per flip-flop notes 1 and 2 20 20 pF

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74HC/HCT377 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION

1 E data enable input (active LOW)

2, 5, 6, 9, 12, 15, 16, 19 Q 0 to Q7 flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D 0 to D7 data inputs

10 GND ground (0 V)

11 CP clock input (LOW-to-HIGH, edge-triggered)

CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74HC/HCT377 Fig.4 Functional diagram. FUNCTION TABLE Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition ↑ = LOW-to-HIGH CP transition X = don’t care OPERATING MODES INPUTS OUTPUTS CP ED n Q n load “1” ↑ lh H load “0” ↑ ll L hold (do nothing) ↑ X h H X X no change no change Fig.5 Logic diagram.

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74HC/HCT377 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL =5 0p F SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Qn 160 200 240 ns 2.0 4.5 6.0 Fig.6 t THL / tTLH output transition time 19 110 ns 2.0 4.5 6.0 Fig.6 t W clock pulse width HIGH or LOW 100 120 ns 2.0 4.5 6.0 Fig.6 t su set-up time D n to CP ns 2.0 4.5 6.0 Fig.7 t su set-up time E to CP ns 2.0 4.5 6.0 Fig.7 t h hold time D n to CP ns 2.0 4.5 6.0 Fig.7 t h hold time E to CP ns 2.0 4.5 6.0 Fig.7 f max maximum clock pulse frequency MHz 2.0 4.5 6.0 Fig.6

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74HC/HCT377 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL =5 0p F INPUT UNIT LOAD COEFFICIENT E CP D n 1.50 0.50 0.20 SYMBOL PARAMETER T amb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Qn 17 32 40 48 ns 4.5 Fig.6 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 20 8 25 30 ns 4.5 Fig.6 tsu set-up time D n to CP 12 4 15 18 ns 4.5 Fig.7 tsu set-up time E to CP 22 12 28 33 ns 4.5 Fig.7 th hold time D n to CP 2 −4 2 2 ns 4.5 Fig.7 th hold time E to CP 3 −2 3 3 ns 4.5 Fig.7 fmax maximum clock pulse frequency 27 48 22 18 MHz 4.5 Fig.6

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74HC/HCT377 AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.7 Waveforms showing the data set-up and hold times from the data input (Dn) and from the data enable input (E) to the clock (CP). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V.